DETAILED ACTION
This action is responsive to the amendment filed July 10, 2026. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
The prior claim objections are withdrawn in view of the amended claims.
Claim Rejections - 35 USC § 112
The prior §112 rejections of claims 1-14 are withdrawn in view of the amended claims and Applicant’s remarks.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 10, recites “the dies”, lacking antecedence.
Claim 2 recites “the bonding surface of the wafer”, lacking antecedence.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 7, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Di Cioccio (US 2020/0020665) in view of Yu et al. (US 2017/0148756), all of record.
(Re Claim 1) Di Cioccio teaches a die-to-wafer stacking method (see Figs. 1-4 and supporting text in ¶¶89-187), comprising:
picking up dies to be bonded from the wafer to be processed and pre-arranging the dies to be bonded on an electrostatic chuck (dies 2 are picked and arranged on the electrostatic chuck 1); and
bonding the dies pre-arranged on the electrostatic chuck, as a whole, to a wafer to be bonded (Fig. 4, dies 2 are bonded to “a wafer to be bonded” 3, see ¶¶61,89,101-104,129,155-159,162-169,183,186-187).
Di Cioccio is silent regarding details of the wafer to be processed, which comprises a substrate, a dielectric layer on the substrate and a metal layer embedded in the dielectric layer, and forming a bonding layer, the bonding layer covering the dielectric layer, and dicing the wafer to be processed into dies to be bonded. Di Cioccio is also silent regarding coating a bonding surface of each of the dies to be bonded with a metal antioxidant after being diced and cleaning the dies to remove the metal antioxidant remaining on the bonding surface. Di Cioccio discloses generic IC/3DIC dies are used (¶¶2-3,26-27,89,129), however lacks details with respect to the individual layers, materials, and structure of the dies. A PHOSITA would understand that conventional IC dies comprise many different layers, materials, and structures to provide functional integrated circuits. A PHOSITA would be motivated to look to related art to teach details of conventional IC dies for use in Di Cioccio’s die transfer/bonding process. Related art from Yu discloses conventional dies are diced from a wafer having a substrate 201a/401a, a dielectric layer 201b/401b and a metal layer 201c/206/401d embedded in the dielectric layer, and forming a bonding layer 203/404 (and optionally 405), on the dielectric layer 201b (e.g. see Fig. 2, ¶18-26, also see sequence in Figs. 4A-4L, dicing in Fig. 4H, ¶¶33-49). In addition, Yu teaches coating a bonding surface of each of the dies to be bonded with a metal antioxidant after being diced (¶47: sulfuric acid and ammonium hydroxide are metal antioxidants). While Yu is silent regarding cleaning the dies to remove the metal antioxidant remaining on the bonding surface, this step would be obvious to a PHOSITA since the wet chemicals described are not only dangerous to people, the wet chemicals must be removed and the surfaces made clean and dry prior to bonding. Thus the cleaning to remove the antioxidant would be both obvious and necessary. A PHOSITA would find it obvious to treat the surfaces of the dies with either sulfuric acid or ammonium hydroxide, as taught by Yu, in order to render the surfaces suitable for subsequent bonding (Yu: ¶46). A PHOSITA would find it obvious to fabricate conventional IC dies as taught by Yu, having conventional layers such as a substrate, dielectric layers and embedded metal layers for the purpose of providing interconnects and a substrate to support forming semiconductor devices, for bonding in Di Cioccio’s process. With respect to the bonding layer, this additional layer is used when a carrier wafer is attached to support the device wafer when processing the opposite side of the wafer, e.g. thinning, forming interconnects, pads, etc. (see Yu’s Figs. 4A-4Q). Since Di Cioccio provides no details of forming the dies, a PHOSITA would find it obvious to look to related art from Yu to teach processes for forming the dies.
(Re Claim 2) after the dies to be bonded are pre-arranged on the electrostatic chuck and before the dies are bonded to the wafer to be bonded, the method further comprising: subjecting the bonding surface of the wafer to be bonded and/or bonding surfaces of the arranged dies to plasma activation (Di Cioccio ¶104; Yu ¶50).
(Re Claim 11) wherein plasma used in the plasma activation is produced from a gas comprising any one of oxygen, nitrogen, argon or hydrogen, or a combination of two or more thereof (Di Cioccio ¶104; Yu ¶50).
(Re Claim 3) wherein the dies to be bonded comprise dies of different functions and/or sizes (Di Cioccio teaches dies of different sizes/functions may be used, ¶¶66,130,171-179, also note Fig. 8).
(Re Claim 7) wherein a plurality of electrostatic chucks are provided, wherein the dies to be bonded are pre-arranged on the plurality of electrostatic chucks and then bonded to the wafer to be bonded.
While Di Cioccio is silent regarding a plurality of electrostatic chucks, a PHOSITA would find a plurality of chucks to be an obvious modification to enable higher throughput. The duplication of parts, i.e. a plurality of electrostatic chucks, is deemed obvious and would not lead to any new or unexpected result (see MPEP §2144.04). A plurality of chucks would provide the expected and obvious advantage of increased, parallel, throughput.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Di Cioccio (US 2020/0020665) and Yu et al. (US 2017/0148756) as applied above, and further in view of Cok et al. (US 2020/0235059), Chandrasekaran et al. (US 2011/0049694), Wang et al. (EP 3029725), and Boss et al. (US 2022/0231193), all of record.
(Re Claim 4) wherein the dies to be bonded are picked up from a first wafer to be processed to an N-th wafer to be processed, where N is an integer ≥1, wherein when N=1, first dies are picked up from the first wafer to be processed; when N≥2, first dies are picked up from the first wafer to be processed, i-th dies from ani-th wafer to be processed and N-th dies from the N-th wafer to be processed, where 1<i<N, and wherein the first, i-th and N-th dies are arranged and combined to form reconstructed dies on the electrostatic chuck, the reconstructed dies corresponding in position to dies on the wafer to be bonded.
Di Cioccio is silent regarding picking dies from a plurality of wafers, although a PHOSITA would find a plurality of wafers obvious in view of Figs. 7-8 showing two different dies (2 and 6) are picked and assembled together. This is because in conventional semiconductor fabrication, it is common practice to form 10’s to 1000’s of identical dies, simultaneously, on a single wafer as this batch processing is what makes semiconductor device fabrication economical. Based on the disclosure of two different dies, it is obvious these would come from two different device wafers. Looking to related art, Cok teaches different dies having different functions and/or sizes, etc, can be picked from a plurality of source wafers (10, 40, e.g. first dies picked from a first wafer, second dies picked from a second wafer, Nth dies from an Nth wafer, etc.) and assembled onto a single destination substrate, and matching up with dies already on the destination substrate, to provide a packaged system having increased functionality (see Figs. 1-8A and ¶¶13-14,40-76). Related art from Chandrasekaran similarly teaches selecting dies of different functions and sizes from a plurality of source wafers to be assembled onto a destination wafer wherein the dies match with dies on the destination substrate (see Figs. 3A-3D and 7A-7D). With respect to the dies arranged and combined to form reconstructed dies on the chuck, related art from Wang teaches a plurality of different dies can be assembled on a chuck and then transferred and collectively bonded to a destination wafer (see Figs. 2-3). In view of the prior art from Cok and Chandrasekaran teaching a plurality of different dies may be selected from a plurality of different device/source wafers, and that the different dies can be assembled onto a single chuck for collective bonding to a target wafer according to Wang, a PHOSITA would recognize this is applicable to Di Cioccio’s process wherein instead of performing the arranging on the chuck and bonding in subsequent steps as shown in Figs. 7 and 8, one could populate the chuck with different dies from different source wafers and then collectively bond them according to Wang. One would only need to modify the chuck to have different heights if dies of different thicknesses are used, however if dies having the same thickness are used and only have different functions, then this can be accomplished without modifying Di Cioccio’s electrostatic chuck. Also, in view of Boss teaching a chuck (Fig. 14B) shaped like Di Cioccio’s can be used to simultaneously pick dies having different sizes, larger dies spanning a plurality of protrusions. This would allow for the collective bonding of a group of diverse dies to provide increased system functionality, e.g. multi-die system in package configurations enable superior performance, higher yields, and improved cost-efficiency by disaggregating monolithic dies into specialized dies that leverage the optimal process node for each function.
(Re Claim 5) wherein the reconstructed dies are periodically arranged on the electrostatic chuck (see Di Cioccio Figs. 1-4 and 7, see Wang Figs. 2-3, see Cok Figs. 3-6A, see Boss Fig. 14B, all showing how dies are periodically arranged on the chuck).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Di Cioccio (US 2020/0020665) and Yu et al. (US 2017/0148756) as applied above, and further in view of Lee et al. (US 2022/0037235), all of record.
(Re Claim 8) after the bonding layer is formed and before the dies to be bonded are picked up from the wafer to be processed, the method further comprising (as discussed above, see Yu’s sequence in Figs. 4A-4L): bonding the bonding layer (404 or 404+405) of the wafer to be processed to a carrier wafer (Fig. 4C, carrier 403a); attaching a blue tape or an ultraviolet (UV) tape to a back side of the wafer to be processed adjacent through openings of the TSVs (Fig. 4J, 409 is a tape frame, the wafer tapes used are conventionally blue in color); debonding the carrier wafer and the wafer to be processed (carrier 403a is removed in Fig. 4K), and removing the carrier wafer (Fig. 4K).
Di Cioccio and Yu are silent regarding after the bonding layer is formed and before the dies to be bonded are picked up from the wafer to be processed, forming through-silicon vias (TSVs), which extend through the substrate and a partial thickness of the dielectric layer and expose the metal layer, and an interconnect layer in the TSVs, wherein the interconnect layer is electrically connected to the first metal layer. Yu uses a different sequence when forming the TSVs (noting Figs. 4A-4F). A PHOSITA desiring to make, use, and improve upon Yu’s process would be motivated to look to alternatives for the processes for forming the TSVs to determine if alternative sequences provide advantages. Related art from Lee (see Figs. 1-10) teaches after forming the FEOL features 150 and the interconnect layers 110 on the frontside of the wafer 100, the TSVs can be etched and filled from the backside of the wafer (Figs. 8-11), allowing the TSVs to extend into the interconnect layers and directly contact the embedded metal layers instead of depending on pad/surface wiring (as in Yu) requiring valuable area on the device surface of the semiconductor substrate, while also taking advantage of the natural via hole taper. Rather than having a wider, real estate wasting, TSV opening at the device surface, the wider opening can be formed on the less-critical backside of the wafer while allowing for smaller and precise connections within and directly to the embedded interconnect layers. Lee’s TSV process is clearly advantageous over Yu’s process and can easily be integrated into Yu’s process flow wherein at Fig. 4A in Yu, Lee’s wafer (Lee: Fig. 7) is provided and then the TSVs can be etched and filled from the backside and the smaller ends can connect directly to the wiring in the interconnect structure while significantly reducing wasted space. A PHOSITA would find it obvious to form the TSVs according to Lee’s sequence for the advantages discussed above.
(Re Claim 10) wherein picking up the dies to be bonded from the wafer to be processed comprises: picking up the dies to be bonded from the blue tape or from the UV tape; and directly placing the dies to be bonded on the electrostatic chuck.
As discussed above, the dies are formed according to Yu and Lee, in Yu’s Fig. 4K, the dies are singulated, still attached to the tape frame 409, and ready to be picked from the tape 409 and then placed onto Di Cioccio’s chuck for bonding.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Di Cioccio (US 2020/0020665) and Yu et al. (US 2017/0148756) and applied above, and further in view of Golda et al. (US 2014/0241843) , all of record.
(Re Claim 12) wherein the electrostatic chuck is charged or discharged under a control of external commands, thereby retaining the arranged dies thereon by attraction or releasing the arranged dies.
Di Cioccio discloses an electrostatic chuck, however does not discuss any obvious or well-known control thereof. A PHOSITA would recognize every electrostatic chuck known in the field of semiconductors requires some form of external commands to charge and discharge the electrodes to clamp or release the article from the chuck. No known electrostatic chuck operates randomly on its own accord, sans any control or commands, choosing when to turn itself on or off. A PHOSITA may require additional details for Di Cioccio’s disclosed electrostatic chuck regarding its function, operation, and control thereof. Looking to related art, Golda discloses an electrostatic chuck having external control via a computer (e.g. ¶¶108-113,121-122, 130). It is obvious for a conventional electrostatic chuck to use external control commands to charge and discharge the electrostatic chuck. This is preferred to a chuck having no control or a chuck randomly turning itself on/off with no external control/commands. This will improve process repeatability and increase yields. A PHOSITA would find it obvious to control Di Cioccio’s electrostatic chuck using a computer employing commands according to Golda.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Di Cioccio (US 2020/0020665) and Yu et al. (US 2017/0148756) and applied above, and further in view of Okada (US 2007/0110917), all of record.
(Re Claim 13) wherein the bonding of the arranged dies on the electrostatic chuck as a whole with the wafer to be bonded is accomplished using a method based on both thermal and mechanical loads.
Di Cioccio and Yu disclose direct/hybrid bonding, however do not provide details of such bonding. A PHOSITA desiring to perform the plasma activation followed by direct/hybrid bonding may be motivated to look to related bonding art to provide additional details of the bonding process. Related art from Okada teaches related a direct bonding process and teaches using both heat and pressure (¶¶91,179,212,238,244). This would be obvious and well known to a PHOSITA as this improves the overall mechanical, thermal, and electrical stability of the bond interfaces disclosed by Di Cioccio and Yu.
Allowable Subject Matter
Claim 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 9 recites the allowable subject matter “…wherein the bonding layer of the wafer to be processed is bonded to the carrier wafer by a bonding adhesive, and wherein when the carrier wafer is debonded from the wafer to be processed and the carrier wafer is removed, the bonding adhesive remains”.
Response to Arguments
Applicant’s amendments overcome the prior claim objections and the prior §112 rejections. The recited blue tape of claim 8 is broadly understood to include any blue colored tape. The Examiner acknowledges most conventional wafer tapes used in dicing are blue in color. Applicant asserts claim 1 is allowable after amending to include some, but not all of the limitations of claims 6 and 14, such that the application and removal of the metal antioxidant can occur at any time. Amended claim 1 is unpatentable over Di Cioccio and Yu et al. as discussed above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
Prosecution Insights