DETAILED ACTION
This action is responsive to the application No. 18/266,528 filed on June 9, 2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Objections
Claims 4-10, and 14 are objected to because of the following informalities:
In claim 4, line 2, “from first wafer” should be changed to -- from a first wafer --.
In claim 4, line 2, “to N-th wafer” should be changed to -- to an N-th wafer --.
In claim 4, line 2, “Integer” should be changed to -- integer --.
In claim 8, line 4, “towards” should be changed to -- to --.
In claim 9, line 2, “boned with” should be changed to -- bonded to--.
In claim 9, line 4, “debonded with” should be changed to -- debonded from --.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the dies pre-arranged on the electrostatic chuck”, lacking antecedence. Previously, only “dies to be bonded” are introduced.
Claim 1 recites “picking up dies to be bonded from the wafer to be processed”. This limitation is confusing since “a wafer” is generally understood to refer to a whole, uncut wafer, sliced from a boule or ingot, i.e. before dicing, while after dicing one refers to dies, chips, or singulated dies, etc. Referring to “dies” implies a wafer has been diced and is no longer in the form of a wafer, and was cut into a plurality of dies. Adding to the confusion, claim 1 recites no dicing step, making it unclear if the wafer recited is supposed to be a whole, uncut wafer, or if Applicant is using the terms “wafer” and “dies” in an unconventional manner. It is unclear if the “picking up dies to be bonded from the wafer to be processed” means an entire uncut wafer, comprising dies that have not yet been singulated, is picked up and arranged on the electrostatic chuck, as a whole, or if one is supposed to interpret the wafer to be a diced wafer that was cut into plurality of singulated dies. If the latter is Applicant’s intent, it is suggested Applicant clarify this by at least reciting a diced wafer or a singulated wafer.
Claim 2 recites “the dies” and “the arranged dies”, lacking antecedence.
Claim 4 recites “N is an integer ≥ 1, wherein first dies are picked up from the first wafer to be processed, i-th dies from the i-th wafer to be processed and N-th dies from the N-th wafer to be processed, where 1<i<N, and wherein the first, i-th and N-th dies are arranged and combined to form reconstructed dies on the electrostatic chuck, the reconstructed dies match respective dies on the wafer to be bonded”. When N= 1, the limitations with respect to the i-th dies and i-th wafer make no sense as the 1<i<N cannot be met.
Claim 4 recites “the reconstructed dies match respective dies on the wafer to be bonded”. This limitation is confusing because this implies the reconstructed dies on the chuck match respective dies, previously arranged and already on the wafer to be bonded, i.e. reconstructed dies matching other dies already present on the wafer to be bonded. This is confusing because it is unclear if this refers to dies already bonded, as a whole (claim 1) to “a wafer to be bonded”, or if the steps in claim 4 further define the picking up dies in claim 1 are from a plurality of wafers to be processed and the end result is still an electrostatic chuck with arranged dies and there is still one step of bonding the dies as a whole to the wafer to be processed. It is unclear if the wafer to be bonded already comprises dies. Also, it is unclear what is required or excluded for the dies to “match”. Does a “match” require a same, identical, die in terms of size, shape, and function, or does “match” mean a same position or alignment or orientation, etc.?
Claim 6 recites “for each of the first wafers to be processed” (plural, emphasis added), however claim 4 introduces [a] first wafer to be processed (singular), making the required number of first wafer(s) to be processed in claim 6, confusing. As best understood, there is only one first wafer.
Claim 6 recites “the dies”, lacking antecedence.
Claim 6 recites “coating a bonding surface of each wafer to be processed with a metal antioxidant after being diced”. This limitation is confusing since after a wafer is diced, the individual pieces are generally referred to as dies, chips, or singulated dies. Also see discussion above regarding claim 1. Also, it is confusing when the recited dicing supposedly occurs since no claims clarify when any of the recited wafers are actually diced into dies.
Claim 7 recites “the dies”, lacking antecedence.
Claim 8 recites “to a surface of the wafer to be processed close with through openings of the TSVs”. This limitation is confusing since no “through openings of the TSVs” are defined making it unclear which end of a TSV is considered a through opening as both ends of a TSV can be considered a through opening, or what Applicant considers “close” since “close” is a subjective term of degree.
Also in claim 8, it is not clear what Applicant intends to require or exclude by the recited “blue tape” as many different tapes may be blue, e.g. painter’s masking tape is blue. It is unclear how any step in the method would depend on or be affected by the color of the tape. It is not clear if Applicant is using the term “blue tape” to refer to any conventional wafer tape, regardless of color, as the recited “blue tape” appears to be a generic term used to refer to conventional wafer tapes. Looking to the art for guidance, out of the >51k documents classified in the semiconductor dicing art (wafer tapes are mostly used in dicing processes), only ~200 documents use the term “blue tape” and only add to the confusion as the art uses the term to describe any wafer tape, regardless if it is clear/transparent and also to refer to UV tapes. For example, Liu et al. (US 2003/0226832) uses the terms interchangeably in ¶6 “In one common method, the sapphire substrate having an array of semiconductor structures such as laser diodes formed thereon is placed on an adhesive known as "blue tape," or "wafer tape."” Howard et al. (US 2004/0232524) similarly notes in ¶33, “In addition, the flexible tape, which supports the wafer during the sawing operation (customarily referred to as the "blue tape"), is transparent in the wavelength range of visible light.” If the “blue” tape is transparent for the entire range of visible wavelengths, this means the “blue” tape is clear, and not actually blue. Jeng et al. (US 2007/0267724) in ¶29 recites “FIG. 2b illustrates the wafer of FIG. 2a after a protective film 16, often called blue tape or UV tape…”, using “blue tape” and “UV tape” as synonymous terms. Lai et al. (US 202/0161182) in ¶38 recites “In some examples, the dicing tape 370 may be a blue tape (i.e., blue UV tape).” If a blue tape can also be a UV tape, the claimed “blue tape or an ultraviolet (UV) tape” is confusing with respect to what is supposed to be different between the two alternative recited. Since Applicant provides no definitions or guidance, for the purpose of examination, the claimed “blue tape”, will be understood to describe any conventional wafer/dicing tape, regardless of color, and includes UV tapes, and while many wafer tapes are blue, the color of a tape is not relevant and would have no significance with respect to the claimed method.
Claim 12 recites “the arranged dies”, lacking antecedence.
Claim 13 recites “the pre-arranged dies”, lacking antecedence.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Di Cioccio (US 2020/0020665) in view of Yu et al. (US 2017/0148756).
(Re Claim 1) Di Cioccio teaches a die-to-wafer stacking method (see Figs. 1-4 and supporting text in ¶¶89-187), comprising:
picking up dies to be bonded from the wafer to be processed and pre-arranging the dies to be bonded on an electrostatic chuck (dies 2 are picked and arranged on the electrostatic chuck 1); and
bonding the dies pre-arranged on the electrostatic chuck, as a whole, to a wafer to be bonded (Fig. 4, dies 2 are bonded to “a wafer to be bonded” 3, see ¶¶61,89,101-104,129,155-159,162-169,183,186-187).
Di Cioccio is silent regarding details of the wafer to be processed, which comprises a substrate, a dielectric layer on the substrate and a metal layer embedded in the dielectric layer, and forming a bonding layer, the bonding layer covering the dielectric layer. Di Cioccio discloses generic IC/3DIC dies are used (¶¶2-3,26-27,89,129), however lacks details with respect to the individual layers, materials, structure, of the dies. A PHOSITA would understand that conventional IC dies comprise many different layers, materials, and structures to provide functional integrated circuits. A PHOSITA would be motivated to look to related art to teach details of conventional IC dies for use in Di Cioccio’s die transfer/bonding process. Related art from Yu discloses conventional dies are diced from a wafer having a substrate 201a/401a, a dielectric layer 201b/401b and a metal layer 201c/206/401d embedded in the dielectric layer, and forming a bonding layer 203/404 (and optionally 405), on the dielectric layer 201b (e.g. see Fig. 2, ¶18-26, also see sequence in Figs. 4A-4L). A PHOSITA would find it obvious to fabricate conventional IC dies as taught by Yu, having conventional layers such as a substrate, dielectric layers and embedded metal layers for the purpose of providing interconnects and a substrate to support forming semiconductor devices, for bonding in Di Cioccio’s process. With respect to the bonding layer, this additional layer is used when a carrier wafer is attached to support the device wafer when processing the opposite side of the wafer, e.g. thinning, forming interconnects, pads, etc. (see Yu’s Figs. 4A-4Q). Since Di Cioccio provides no details of forming the dies, a PHOSITA would find it obvious to look to related art from Yu to teach processes for forming the dies.
(Re Claim 2) after the dies to be bonded are pre-arranged on the electrostatic chuck and before the dies are bonded to the wafer to be bonded, the method further comprising: subjecting a bonding surface of the wafer to be bonded and/or bonding surfaces of the arranged dies to plasma activation (Di Cioccio ¶104; Yu ¶50).
(Re Claim 11) wherein plasma used in the plasma activation is produced from a gas comprising any one of oxygen, nitrogen, argon or hydrogen, or a combination of two or more thereof (Di Cioccio ¶104; Yu ¶50).
(Re Claim 3) wherein the dies to be bonded comprise dies of different functions and/or sizes (Di Cioccio teaches dies of different sizes/functions may be used, ¶¶66,130,171-179, also note Fig. 8).
(Re Claim 7) wherein a plurality of electrostatic chucks are provided, wherein the dies are pre-arranged on the plurality of electrostatic chucks and then bonded to the wafer to be bonded.
While Di Cioccio is silent regarding a plurality of electrostatic chucks, a PHOSITA would find a plurality of chucks to be an obvious modification to enable higher throughput. The duplication of parts, i.e. a plurality of electrostatic chucks, is deemed obvious and would not lead to any new or unexpected result (see MPEP §2144.04). A plurality of chucks would provide the expected and obvious advantage of increased, parallel, throughput.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Di Cioccio (US 2020/0020665) and Yu et al. (US 2017/0148756) as applied above, and further in view of Cok et al. (US 2020/0235059), Chandrasekaran et al. (US 2011/0049694), Wang et al. (EP 3029725), and Boss et al. (US 2022/0231193).
(Re Claim 4) wherein the dies to be bonded are picked up from first wafer to be processed to N-th wafer to be processed, where N is an Integer 1, wherein first dies are picked up from the first wafer to be processed, i-th dies from the i-th wafer to be processed and N-th dies from the N-th wafer to be processed, where 1<i<N, and wherein the first, i-th and N-th dies are arranged and combined to form reconstructed dies on the electrostatic chuck, the reconstructed dies match respective dies on the wafer to be bonded.
Di Cioccio is silent regarding picking dies from a plurality of wafers, although a PHOSITA would find a plurality of wafers obvious in view of Figs. 7-8 showing two different dies (2 and 6) are picked and assembled together. This is because in conventional semiconductor fabrication, it is common practice to form 10’s to 1000’s of identical dies, simultaneously on a single wafer as this batch processing is what makes semiconductor device fabrication economical. Based on the disclosure of two different dies, it is obvious these would come from two different device wafers. Looking to related art, Cok teaches different dies having different functions and/or sizes, etc, can be picked from a plurality of source wafers (10, 40, e.g. first dies picked from a first wafer, second dies picked from a second wafer, Nth dies from an Nth wafer, etc.) and assembled onto a single destination substrate, and matching up with dies already on the destination substrate, to provide a packaged system having increased functionality (see Figs. 1-8A and ¶¶13-14,40-76). Related art from Chandrasekaran similarly teaches selecting dies of different functions and sizes from a plurality of source wafers to be assembled onto a destination wafer wherein the dies match with dies on the destination substrate (see Figs. 3A-3D and 7A-7D). With respect to the dies arranged and combined to form reconstructed dies on the chuck, related art from Wang teaches a plurality of different dies can be assembled on a chuck and then transferred and collectively bonded to a destination wafer (see Figs. 2-3). In view of the prior art from Cok and Chandrasekaran teaching a plurality of different dies may be selected from a plurality of different device/source wafers, and that the different dies can be assembled onto a single chuck for collective bonding to a target wafer according to Wang, a PHOSITA would recognize this is applicable to Di Cioccio’s process wherein instead of performing the arranging on the chuck and bonding in subsequent steps as shown in Figs. 7 and 8, one could populate the chuck with different dies from different source wafers and then collectively bond them according to Wang. One would only need to modify the chuck to have different heights if dies of different thicknesses are used, however if dies having the same thickness are used and only have different functions, then this can be accomplished without modifying Di Cioccio’s electrostatic chuck. Also, in view of Boss teaching a chuck (Fig. 14B) shaped like Di Cioccio’s can be used to simultaneously pick dies having different sizes, larger dies spanning a plurality of protrusions. This would allow for the collective bonding of a group of diverse dies to provide increased system functionality, e.g. multi-die system in package configurations enable superior performance, higher yields, and improved cost-efficiency by disaggregating monolithic dies into specialized dies that leverage the optimal process node for each function.
(Re Claim 5) wherein the reconstructed dies are periodically arranged on the electrostatic chuck (see Di Cioccio Figs. 1-4 and 7, see Wang Figs. 2-3, see Cok Figs. 3-6A, see Boss Fig. 14B, all showing how dies are periodically arranged on the chuck).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Di Cioccio (US 2020/0020665), Yu et al. (US 2017/0148756), Cok et al. (US 2020/0235059), Chandrasekaran et al. (US 2011/0049694), Wang et al. (EP 3029725), and Boss et al. (US 2022/0231193), as applied above, and further in view of Wakabayashi et al. (US 2001/0042902).
(Re Claim 6) for each of the first wafers to be processed to N-th wafer to be processed, before the dies are picked up from a corresponding wafer to be processed, the method further comprising: coating a bonding surface of each wafer to be processed with a metal antioxidant after being diced.
Di Cioccio and Yu are silent regarding coating a bonding surface of each wafer to be processed with a metal antioxidant after being diced. A PHOSITA would recognize that metal parts of the device are susceptible to oxidation and that forming a protective coating to prevent oxidation of metals can be beneficial. Related art from Wakabayashi teaches forming a protective film 3+7, after dicing, and before the dies are picked from the dicing tape, which covers the bonding surfaces (e.g. see Fig. 15), and this “antioxidant” coating prevents oxidation of metal wiring 5 (see ¶¶60,76). In view of Wakabayashi, a PHOSITA would find it obvious to similarly protect Di Cioccio’s dies after dicing by coating the bonding surfaces, and that this may efficiently performed as a batch process with the singulated dies still on the dicing tape.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Di Cioccio (US 2020/0020665) and Yu et al. (US 2017/0148756) as applied above, and further in view of Lee et al. (US 2022/0037235).
(Re Claim 8) after the bonding layer is formed and before the dies to be bonded are picked up from the wafer to be processed, the method further comprising (as discussed above, see Yu’s sequence in Figs. 4A-4L): bonding the bonding layer (404 or 404+405) of the wafer to be processed towards a carrier wafer (Fig. 4C, carrier 403a); attaching a blue tape or an ultraviolet (UV) tape to a surface of the wafer to be processed close with through openings of the TSVs (Fig. 4J, 409 is a tape frame, the wafer tapes used are conventionally blue in color); debonding the carrier wafer and the wafer to be processed (carrier 403a is removed in Fig. 4K), and removing the carrier wafer (Fig. 4K); and dicing the wafer to be processed (dicing in Fig. 4H).
Di Cioccio and Yu are silent regarding after the bonding layer is formed and before the dies to be bonded are picked up from the wafer to be processed, forming through-silicon vias (TSVs), which extend through the substrate and a partial thickness of the dielectric layer and expose the metal layer, and an interconnect layer in the TSVs, wherein the interconnect layer is electrically connected to the first metal layer. Yu uses a different sequence when forming the TSVs (noting Figs. 4A-4F). A PHOSITA desiring to make, use, and improve upon Yu’s process would be motivated to look to alternatives for the processes for forming the TSVs to determine if alternative sequences provide advantages. Related art from Lee (see Figs. 1-10) teaches after forming the FEOL features 150 and the interconnect layers 110 on the frontside of the wafer 100, the TSVs can be etched and filled from the backside of the wafer (Figs. 8-11), allowing the TSVs to extend into the interconnect layers and directly contact the embedded metal layers instead of depending on pad/surface wiring (as in Yu) requiring valuable area on the device surface of the semiconductor substrate, while also taking advantage of the natural via hole taper. Rather than having a wider, real estate wasting, TSV opening at the device surface, the wider opening can be formed on the less-critical backside of the wafer while allowing for smaller and precise connections within and directly to the embedded interconnect layers. Lee’s TSV process is clearly advantageous over Yu’s process and can easily be integrated into Yu’s process flow wherein at Fig. 4A in Yu, Lee’s wafer (Lee: Fig. 7) is provided and then the TSVs can be etched and filled from the backside and the smaller ends can connect directly to the wiring in the interconnect structure while significantly reducing wasted space. A PHOSITA would find it obvious to form the TSVs according to Lee’s sequence for the advantages discussed above.
(Re Claim 10) wherein picking up the dies to be bonded from the wafer to be processed comprises: picking up the dies to be bonded from the blue tape or from the UV tape; and directly placing the dies to be bonded on the electrostatic chuck.
As discussed above, the dies are formed according to Yu and Lee, in Yu’s Fig. 4K, the dies are singulated, still attached to the tape frame 409, and ready to be picked from the tape 409 and then placed onto Di Cioccio’s chuck for bonding.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Di Cioccio (US 2020/0020665) and Yu et al. (US 2017/0148756) and applied above, and further in view of Golda et al. (US 2014/0241843).
(Re Claim 12) wherein the electrostatic chuck is charged or discharged under a control of external commands, thereby retaining the arranged dies thereon by attraction or releasing the arranged dies.
Di Cioccio discloses an electrostatic chuck, however does not discuss any obvious or well-known control thereof. A PHOSITA would recognize every electrostatic chuck known in the field of semiconductors requires some form of external commands to charge and discharge the electrodes to clamp or release the article from the chuck. No known electrostatic chuck operates randomly on its own accord, sans any control or commands, choosing when to turn itself on or off. A PHOSITA may require additional details for Di Cioccio’s disclosed electrostatic chuck regarding its function, operation, and control thereof. Looking to related art, Golda discloses an electrostatic chuck having external control via a computer (e.g. ¶¶108-113,121-122, 130). It is obvious for a conventional electrostatic chuck to use external control commands to charge and discharge the electrostatic chuck. This is preferred to a chuck having no control or a chuck randomly turning itself on/off with no external control/commands. This will improve process repeatability and increase yields. A PHOSITA would find it obvious to control Di Cioccio’s electrostatic chuck using a computer employing commands according to Golda.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Di Cioccio (US 2020/0020665) and Yu et al. (US 2017/0148756) and applied above, and further in view of Okada (US 2007/0110917).
(Re Claim 13) wherein the bonding of the pre-arranged dies on the electrostatic chuck as a whole with the wafer to be bonded is accomplished using a method based on both thermal and mechanical loads.
Di Cioccio and Yu disclose direct/hybrid bonding, however do not provide details of such bonding. A PHOSITA desiring to perform the plasma activation followed by direct/hybrid bonding may be motivated to look to related bonding art to provide additional details of the bonding process. Related art from Okada teaches related a direct bonding process and teaches using both heat and pressure (¶¶91,179,212,238,244). This would be obvious and well known to a PHOSITA as this improves the overall mechanical, thermal, and electrical stability of the bond interfaces disclosed by Di Cioccio and Yu.
Allowable Subject Matter
Claims 9 and 14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 9 recites the allowable subject matter “…wherein the bonding layer of the wafer to be processed is boned with the carrier wafer by a bonding adhesive, and wherein when the carrier wafer is debonded with the wafer to be processed and the carrier wafer is removed, the bonding adhesive remains”.
Claim 14 recites the allowable subject matter “…wherein after the dies to be bonded are pre-arranged on the electrostatic chuck and before the dies are subjected to the plasma activation, the method further comprising: cleaning the dies to remove the metal antioxidant remaining on the bonding surface”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches picking-and-placing dies using electrostatic chucks, bonding and de-bonding wafers from various carriers, picking and bonding a plurality of dies simultaneously, forming TSVs, and forming protective/passivation layers on devices.
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
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