CTNF 18/267,247 CTNF 71715 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The U.S. Patent Publication Application Publication Cite. No. 1 “20030009370” listed to McConaghy, Trent was not considered because the Publication Number appears to be in error. Drawings 06-22-06 AIA The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: PDK 180 [page 15, lines 5 and 9]; PDK 28 [page 19, lines 6 and 7]; 513 [page 34, line 6] . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. 06-22-07 AIA The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 524 [FIG. 5] . Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections 07-29-01 AIA Claim s 1 and 13 are objected to because of the following informalities: perhaps the first comma in step (f) [after “select” and “selecting”] is unnecessary . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 2, 14, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph , as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Taking claim 2 as exemplary of claims 2 and 14, the boundaries of claim scope are not clear. The terms “how well” [step (i)] and “best meets” [step (l)] are relative terms which render the claim indefinite. The terms are not defined by the claim, the terms are subjective. Thus, the claims are vague and indefinite. As per claim 19, the boundaries of claim scope are not clear. There is no antecedent basis for “simulated behavior” [lines 3 and 4]. Thus, the claim is incomplete, vague and indefinite. The following rejections are based on the Examiner’s best interpretation of the claims in view of the indefiniteness identified above. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-4, 6, 8-15, 17-21, 25-26 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more . The claims recite mental processes that can be performed in the human mind or by a human using a pen and paper. Taking claim 1 as exemplary, based on the plain meaning of the words in the claim, a broadest reasonable interpretation of the broadly claimed subject matter is an apparatus to design an analogue circuit configured to receive information, identify potential architectures, select an initial architecture, produce a design, determine whether the design will meet requirements and if so, output a design, if not, select another architecture and repeat the steps accordingly to output a design. This judicial exception is not integrated into a practical application because there are no meaningful details of the analogue circuit, the technical requirements, etc., that are recited beyond observation, evaluation, judgement, and opinion. For example, given a broadest reasonable interpretation of the broadly claimed subject matter, taking claim 1 as exemplary, step (a) is an observation of input in the form of requirements; step (b) involves observation, evaluation, judgement, and opinion to identify potential architectures, being based on the received information, and for satisfying requirement; step (c) involves evaluation, judgement, and opinion to select an initial architecture dependent on requirements; step (d) involves opinion to produce a design; step (e) involves evaluation, judgement, and opinion to determine whether the design meets the requirement; step (f) involves evaluation, judgement, and opinion to select another architecture dependent on requirements; step (g) involves observation, evaluation, judgement, and opinion as reasoned above; and step (h) involves observation, evaluation, judgement, and opinion to output a design. The limitations recited in the dependent claims similarly follow. The limitations recited as generic computer elements [a processor, a communications interface, to control, etc., also claim 26] do not add meaningful limitations to the abstract idea because they amount to simply implementing the abstract idea on a computer. Furthermore, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because a processor being configured to control the communication interface, to receive information, etc. are well-understood, routine, conventional computer functions. Further regarding claim 25, the limitation of fabricating is merely adding insignificant extra-solution activity to the judicial exception. Thus, the claims do not recite eligible subject matter, the claimed invention is directed toward an abstract idea without significantly more. Therefore, the claims are rejected under 35 U.S. C. 101. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3, 13-14, 25-26 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by M. Liu et al. [“Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis”] . Taking claim 1 as exemplary of claims 1, 13 and 26, an analogue circuit design apparatus [section IV. Performed on a Linux workstation], the apparatus comprising at least one design unit comprising a processor and a communications interface [inherent], the processor being configured to: (a) control the communications interface to receive information representing technical requirements for the analogue circuit [Fig. 2 INPUTS], wherein the technical requirements comprise (i) at least one circuit performance requirement [Fig. 2 Circuit Netlist, Default Parameters], and (ii) at least one manufacturing requirement for the analogue circuit to satisfy a specific set of manufacturing process related rules [Fig. 2 PDK]; (b) identify, based on the received information, a plurality of potential analogue circuit design architectures, for satisfying the circuit performance requirement, that will satisfy the at least one manufacturing requirement [a plurality of potential architectures are identified through the iterative process]; (c) select, as a current analogue circuit design architecture, an initial analogue circuit design architecture from among the plurality of potential analogue circuit design architectures, wherein the selection of the initial analogue circuit design is dependent on the set of manufacturing process related rules [the Initialize lines in Algorithms 2 and 3 indicate an initial architecture is selected as a current architecture for the iterative process]; (d) produce a current design for the analogue circuit that satisfies the current analogue circuit design architecture [Algorithm 3 lines 4 and 5 indicated a current design is generated]; (e) determine, for the current design for the analogue circuit, whether the current design will meet the at least one circuit performance requirement [Algorithm 2 lines 7-8 indicate the criteria are true if the requirement is met for the current design at lines 7-8 in Algorithm 3]; in the event that the current design for the analogue circuit is determined not to meet the circuit performance requirement [Algorithm 3 line 3 while the criteria is false indicates the event]: (f) select, a further analogue circuit design architecture as the current analogue circuit design architecture, wherein the selection of the further analogue circuit design architecture is dependent on the set of manufacturing process related rules [line 9 in Algorithm 3 indicates an iteration loop that provides a further architecture as the current architecture for processing], and (g) repeat steps (d) and (e) [line 3 in Algorithm 3 indicates a loop]; and (h) in the event that the current design for the analogue circuit design architecture is determined to meet the circuit performance requirement, output a design for the analogue circuit [Fig. 2 OUTPUT indicates a GDSII Layout is output in accordance with line 14 of Algorithm 2 and line 11 of Algorithm 3]. Taking claim 2 as exemplary of claims 2 and 14, wherein the processor is further configured to: (i) determine, for each current design for the analogue circuit, how well the current design meets the at least one circuit performance requirement and the set of manufacturing process related rules [the Objective function (8) determines how well the current design meets circuit performance requirements and manufacturing process related rules depicted as INPUTS in Fig. 2]; (j) select, a further analogue circuit design architecture as the current analogue circuit design architecture, wherein the selection of the further analogue circuit design architecture is dependent on the set of manufacturing process related rules [line 9 in Algorithm 3 indicates an iteration loop that provides a further architecture as the current architecture for processing], and (k) repeat steps (d) and (e) to produce a plurality of produced analogue circuit designs [line 3 in Algorithm 3 indicates a loop, lines 4 and 5 indicated a plurality of designs are generated through looping]; and (l) choose and output a design for the analogue circuit from the plurality of produced analogue circuit designs that best meets the at least one circuit performance requirement and the set of manufacturing process related rules [line 10 in Algorithm 3 indicates an optimized layout L is chosen, Fig. 2 depicts the OUTPUT]. As per claim 3, wherein the selection of the analogue circuit design architecture at step (c) and/or step (f) is based on a prioritisation of the plurality of potential architectures that creates a prioritised list of potential analogue circuit design architectures that have been determined to meet the set of manufacturing process related rules [Pareto set P in Algorithms 2 and 3 provides prioritization accordingly]. As per claim 25, further comprising fabricating an analogue circuit to the output design [the GDSII Layout output in Fig. 2 is the file for fabrication] . 07-15 AIA Claim s 1-3, 13-14, 25-26 are rejected under 35 U.S.C. 102( a)(1) and (a)(2 ) as being anticipated by Nitta et al. [US 2011/0239182 A1] . Taking claim 1 as exemplary of claims 1, 13 and 26 an analogue circuit design apparatus [FIG. 43], the apparatus comprising at least one design unit comprising a processor and a communications interface [FIG. 43], the processor being configured to: (a) control the communications interface to receive information representing technical requirements for the analogue circuit [0101 input unit 21], wherein the technical requirements comprise (i) at least one circuit performance requirement [0101 specification data], and (ii) at least one manufacturing requirement for the analogue circuit to satisfy a specific set of manufacturing process related rules [0064 process constraint condition, the designer may desire to carry out the optimization considering the manufacturing cost, 0101 process constraint condition]; (b) identify, based on the received information, a plurality of potential analogue circuit design architectures, for satisfying the circuit performance requirement, that will satisfy the at least one manufacturing requirement [0078 a set of pareto optimal solutions is generated for each combination, 0091, 0114 provisional optimal solution search processing]; (c) select, as a current analogue circuit design architecture, an initial analogue circuit design architecture from among the plurality of potential analogue circuit design architectures, wherein the selection of the initial analogue circuit design is dependent on the set of manufacturing process related rules [0066 and 0068 individual is interpreted as the initial for processing, 0104 select one optimization case is interpreted as the current]; (d) produce a current design for the analogue circuit that satisfies the current analogue circuit design architecture [0069 for the identified circuit configuration, 0105-0106 carries out the optimal solution generation processing according to this setting]; (e) determine, for the current design for the analogue circuit, whether the current design will meet the at least one circuit performance requirement [0073 judges whether or not constitutes a pareto optimal solution in the solution space]; in the event that the current design for the analogue circuit is determined not to meet the circuit performance requirement [0076 when the pareto generation conditions are not satisfied, 0097 when an unprocessed function exists, the processing returns]: (f) select, a further analogue circuit design architecture as the current analogue circuit design architecture, wherein the selection of the further analogue circuit design architecture is dependent on the set of manufacturing process related rules [0076 processing returns to step S17, 0079 and 0090 entire parent processing is interpreted to select further architectures as the current as per the processing for all combinations], and (g) repeat steps (d) and (e) [0091 for all combinations, 0108 carried out for every execution]; and (h) in the event that the current design for the analogue circuit design architecture is determined to meet the circuit performance requirement, output a design for the analogue circuit [0101 output unit that outputs data]. Taking claim 2 as exemplary of claims 2 and 14, wherein the processor is further configured to: (i) determine, for each current design for the analogue circuit, how well the current design meets the at least one circuit performance requirement and the set of manufacturing process related rules [0059 individual pareto and entire pareto]; (j) select, a further analogue circuit design architecture as the current analogue circuit design architecture, wherein the selection of the further analogue circuit design architecture is dependent on the set of manufacturing process related rules [0076 processing returns to step S17, 0079 and 0090 entire parent processing is interpreted to select further architectures as the current as per the processing for all combinations], and (k) repeat steps (d) and (e) to produce a plurality of produced analogue circuit designs [0091 for all combinations, 0108 carried out for every execution]; and (l) choose and output a design for the analogue circuit from the plurality of produced analogue circuit designs that best meets the at least one circuit performance requirement and the set of manufacturing process related rules [0075 multi-objective optimization processing, investigating tradeoff, 0101 output unit that outputs data]. As per claim 3, wherein the selection of the analogue circuit design architecture at step (c) and/or step (f) is based on a prioritisation of the plurality of potential architectures that creates a prioritised list of potential analogue circuit design architectures that have been determined to meet the set of manufacturing process related rules [pareto inherently based on prioritization]. As per claim 25, further comprising fabricating an analogue circuit to the output design [0182 a chip is manufactured] . Allowable Subject Matter 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See, for example, T. Dhar et al.’s “ALIGN” [NPL] at entire document, particularly Input: PDK in Fig. 2 and section 2.5 . Claims 4, 6, 8-11, 15, 17-21 are being identified as objected to as being dependent upon an art rejected base claim, but may be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and rewritten to recite eligible subject matter . 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: M. Liu et al. appear to teach bottom-up design methodology, the top-level layouts are implemented after all dependent circuit layouts are complete [section III.A.]. Thus, considering that a primary design unit is defined as a parent block [see, for example, page 12, lines 2-8], the prior art of record does not appear to anticipate or render obvious, taking claim 4 and exemplary of claims 4 and 15, wherein the apparatus comprises a primary design unit and a secondary design unit, wherein the primary design unit is configured to: (m) identify, based on the received information, the plurality of potential analogue circuit design architectures, for satisfying the circuit performance requirement, that will satisfy the manufacturing requirement; and (n) select, as the current analogue circuit design architecture, the initial analogue circuit design architecture from among the plurality of potential analogue circuit design architectures, wherein each circuit design architecture comprises a respective plurality of circuit portions; (o) determine, for each circuit portion of the plurality of circuit portions, respective circuit performance requirements for that circuit portion, wherein the respective circuit performance requirements for each circuit portion are determined based on the specific set of manufacturing process related rules; and (p) provide the respective circuit performance requirements for each circuit portion to at least one of a plurality of secondary design units; and wherein each of the plurality of secondary design units of the analogue circuit design apparatus is configured to: (q) design a respective circuit portion of the plurality of circuit portions based on the circuit performance requirements for that respective circuit portion provided by the primary design unit; and (r) output a resulting initial design of the respective circuit portion; wherein the primary design unit is further configured to: (s) receive a respective design for each circuit portion from each of the plurality of secondary design units; and (t) produce the current analogue circuit design for the analogue circuit that satisfies the current analogue circuit design architecture based on the respective designs for each circuit portion; wherein the primary design unit is further configured to: (u) simulate an analogue circuit based on the current analogue circuit design to produce at least one simulation output; (v) verify whether or not the analogue circuit meets the circuit performance requirement, and when the analogue circuit meets the circuit performance requirement, output the generated design; and when the analogue circuit does not meet the circuit performance requirement: select, a further analogue circuit design architecture as the current analogue circuit design architecture, wherein the selection of the further analogue circuit design is dependent on the set of manufacturing process related rules; and repeat steps (d) to (e) and (m) to (v). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LEIGH M GARBOWSKI/ Primary Examiner, Art Unit 2851 Application/Control Number: 18/267,247 Page 2 Art Unit: 2851 Application/Control Number: 18/267,247 Page 3 Art Unit: 2851 Application/Control Number: 18/267,247 Page 4 Art Unit: 2851 Application/Control Number: 18/267,247 Page 5 Art Unit: 2851 Application/Control Number: 18/267,247 Page 6 Art Unit: 2851 Application/Control Number: 18/267,247 Page 7 Art Unit: 2851 Application/Control Number: 18/267,247 Page 8 Art Unit: 2851 Application/Control Number: 18/267,247 Page 9 Art Unit: 2851 Application/Control Number: 18/267,247 Page 10 Art Unit: 2851 Application/Control Number: 18/267,247 Page 11 Art Unit: 2851 Application/Control Number: 18/267,247 Page 12 Art Unit: 2851