DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed November 6, 2025.
Claims 14 and 16-27 are pending. Claims 1-13 and 15 are canceled. Claim 27 is new. Claims 14, 20 and 23 are independent.
Continued Examination Under 37 CFR 1.114 After Final Rejection
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 6, 2025 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on June 16, 2023.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14, 20-21, 23-24 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Slesazeck et al. (U.S. 2019/0172539; hereinafter “Slesazeck”) in view of Eliason et al. (U.S. 2006/0118841; hereinafter “Eliason”).
Regarding independent claim 14, Slesazeck teaches an electric circuit assembly (Fig. 1c), comprising a ferroelectric field effect transistor (Fig. 1c: 100), and electric energy source (Fig. 1c: supply circuitries (not shown in Figures) that apply voltages to terminals for example: I/O1 and I/O3, see page 3, par. 0035), and a resistive element (Fig. 1c: 130) having a minimum electric resistance of 100 kOhm (see page 4, par. 0042), wherein the resistive element (Fig. 1c: 130) is electrically connected to a drain terminal (Fig. 1c: I/O4) of the ferroelectric field effect transistor (Fig. 1c: 100), and the electric energy source (Fig. 1c: supply circuitries (not shown in Figures) that apply voltages to terminals for example: I/O1 and I/O3) is electrically connected to a gate terminal (Fig. 1c: I/O1) and a source terminal (Fig. 1c: I/O3) of the ferroelectric field effect transistor (Fig. 1c: 100).
However, Slesazeck is silent with respect to wherein the electric resistance of the resistive element is 1 MOhm to 100 MOhm.
Similar to Slesazeck, Eliason teaches an electric circuit assembly comprising a ferroelectric memory and a resistive element (Fig. 1C).
Furthermore, Eliason teaches wherein the electric resistance of the resistive element is 1 MOhm to 100 MOhm (see page 2, par. 0011).
Since Eliason and Slesazeck are from the same field of endeavor, the teachings described by Eliason would have been recognized in the pertinent art of Slesazeck.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Eliason with the teachings of Slesazeck for the purpose of provide a substantially linear I-V characteristic, see Eliason’s page 2, par. 0011.
Regarding independent claim 20, Slesazeck teaches a memory cell, comprising an electric circuit assembly (Fig. 1c), comprising a ferroelectric field effect transistor (Fig. 1c: 100), an electric energy source (Fig. 1c: supply circuitries (not shown in Figures) that apply voltages to terminals for example: I/O1 and I/O3, see page 3, par. 0035), and a resistive element (Fig. 1c: 130) having a minimum electric resistance of 100 kOhm (see page 4, par. 0042), wherein the resistive element (Fig. 1c: 130) is electrically connected to a drain terminal (Fig. 1c: I/O4) of the ferroelectric field effect transistor (Fig. 1c: 100), and the electric energy source (Fig. 1c: supply circuitries (not shown in Figures) that apply voltages to terminals for example: I/O1 and I/O3) is electrically connected to a gate terminal (Fig. 1c: I/O1) and a source terminal (Fig. 1c: I/O3) of the ferroelectric field effect transistor (Fig. 1c: 100).
However, Slesazeck is silent with respect to wherein the electric resistance of the resistive element is 1 MOhm to 100 MOhm.
Similar to Slesazeck, Eliason teaches an electric circuit assembly comprising a ferroelectric memory and a resistive element (Fig. 1C).
Furthermore, Eliason teaches wherein the electric resistance of the resistive element is 1 MOhm to 100 MOhm (see page 2, par. 0011).
Since Eliason and Slesazeck are from the same field of endeavor, the teachings described by Eliason would have been recognized in the pertinent art of Slesazeck.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Eliason with the teachings of Slesazeck for the purpose of provide a substantially linear I-V characteristic, see Eliason’s page 2, par. 0011.
As discussed above, Slesazeck’s memory cell in combination with Eliason is substantially identical in structure to the claimed “memory cell,” where the differences reside only in the remaining limitations relating to function of “the ferroelectric field effect transistor is replaced by a flash transistor.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Slesazeck’s apparatus in combination with Eliason appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 21, Slesazeck in combination with Eliason teaches the limitations with respect to claim 20.
As discussed above, Slesazeck’s memory cell in combination with Eliason is substantially identical in structure to the claimed “memory cell and electric circuit assembly,” where the differences reside only in the remaining limitations relating to characteristic of “having an on/off ratio of greater than 102.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Slesazeck’s apparatus in combination with Eliason appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding independent claim 23, Slesazeck teaches a method for programming (see page 3, par. 0038) an electric circuit assembly (Fig. 1c) comprising a ferroelectric field effect transistor (Fig. 1c: 100), an electric energy source (Fig. 1c: supply circuitries (not shown in Figures) that apply voltages to terminals for example: I/O1 and I/O3, see page 3, par. 0035), and a resistive element (Fig. 1c: 130) having a minimum electric resistance of 100 kOhm (see page 4, par. 0042), the resistive element (Fig. 1c: 130) being electrically connected to a drain terminal (Fig. 1c: I/O4) of the ferroelectric field effect transistor (Fig. 1c: 100), and the electric energy source (Fig. 1c: supply circuitries (not shown in Figures) that apply voltages to terminals for example: I/O1 and I/O3) being electrically connected to the gate terminal (Fig. 1c: I/O1) and a source terminal (Fig. 1c: I/O3) of the ferroelectric field effect transistor (Fig. 1c: 100), wherein the ferroelectric field effect transistor is transferred into a state of logic one or logic zero (see page 3, par. 0038) by applying an electric voltage of a defined level to one of the terminals of the ferroelectric field effect transistor (Fig. 2a: Vdd) and connecting the further terminals to electric zero potential (Fig. 2a: GND).
However, Slesazeck is silent with respect to wherein the electric resistance of the resistive element is 1 MOhm to 100 MOhm.
Similar to Slesazeck, Eliason teaches an electric circuit assembly comprising a ferroelectric memory and a resistive element (Fig. 1C).
Furthermore, Eliason teaches wherein the electric resistance of the resistive element is 1 MOhm to 100 MOhm (see page 2, par. 0011).
Since Eliason and Slesazeck are from the same field of endeavor, the teachings described by Eliason would have been recognized in the pertinent art of Slesazeck.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Eliason with the teachings of Slesazeck for the purpose of provide a substantially linear I-V characteristic, see Eliason’s page 2, par. 0011.
Regarding claim 24, Slesazeck in combination with Eliason teaches the limitations with respect to claim 23.
Furthermore, Slesazeck teaches wherein that, when a plurality of ferroelectric field effect transistors are arranged in a matrix arrangement (see page 8, par. 0082), only the ferroelectric field effect transistor to be programmed is supplied with the electric voltage of a defined level (Fig. 2a: Vdd).
Regarding claim 27, Slesazeck in combination with Eliason teaches the limitations with respect to claim 14.
Furthermore, Slesazeck discloses wherein a voltage at the drain terminal of the ferroelectric field effect transistor is adjusted only by the resistive element (the value of the drain terminal is only adjusted by the resistive element 130 when Vdd is applied and an output value is shown in I/O 4, see page 4, par. 0042).
Claims 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Slesazeck and Eliason as applied to claim 14 above, and further in view of Nishimura et al. (U.S. 5,633,821; hereinafter “Nishimura”).
PNG
media_image1.png
610
805
media_image1.png
Greyscale
Regarding claim 16, Slesazeck in combination with Eliason teaches the limitations with respect to claim 14.
However, the combination is silent with respect to wherein the resistive element is composed of a current mirror and a current generator.
Similar to the combination, Nishimura teaches an electric circuit assembly comprising a ferroelectric field effect transistor and a resistive element (Fig. 5).
Furthermore, Nishimura teaches wherein the resistive element is composed of a current mirror and a current generator (see Examiner’s Markup Nishimura Figure 10).
Since Nishimura, Eliason and Slesazeck are from the same field of endeavor, the teachings described by Nishimura would have been recognized in the pertinent art of Slesazeck in combination with Eliason.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Nishimura with the teachings of Slesazeck in combination with Eliason for the purpose of cancel error caused by electric characteristics changes, see Nishimura’s col. 7, ll. 55-56.
Regarding claim 18, Slesazeck in combination with Eliason teaches the limitations with respect to claim 14.
However, the combination is silent with respect to a plurality of ferroelectric field effect transistors are arranged in a matrix arrangement including at least two rows and at least two columns, the gate terminals of all ferroelectric field effect transistors of a single row being electrically con-nected to a shared word line, all source outputs of the ferroelectric field effect transistors arranged in a single column being connected to a shared source line, and all drain terminals of the ferroelectric field effect transistors arranged in a single column being connected to a shared drain line.
Similar to Slesazeck, Nishimura’871 teaches an electric circuit assembly comprising a ferroelectric field effect transistor (Fig. 2: Ms).
Furthermore, Nishimura’871 teaches a plurality of ferroelectric field effect transistors (Fig. 2: Ms) are arranged in a matrix arrangement including at least two rows and at least two columns (Fig. 2: array comprising plurality of rows and columns of Ms), the gate terminals of all ferroelectric field effect transistors of a single row being electrically connected to a shared word line (Fig. 2: CGL1), all source outputs of the ferroelectric field effect transistors arranged in a single column being connected to a shared source line (Fig. 2: SL1), and all drain terminals of the ferroelectric field effect transistors arranged in a single column being connected to a shared drain line (Fig. 2: DL couple to R).
Since Nishimura’871, Eliason and Slesazeck are from the same field of endeavor, the teachings described by Nishimura’871 would have been recognized in the pertinent art of Slesazeck in combination with Eliason.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Jang with the teachings of Slesazeck for the purpose of increase calculation performance, see Jang’s page 11, par. 0173.
Claims 17 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Slesazeck and Eliason as applied to claims 14 and 23 above, and further in view of Jang et al. (U.S. 2021/0125048; hereinafter “Jang”).
Regarding claim 17, Slesazeck in combination with Eliason teaches the limitations with respect to claim 14.
However, the combination is silent with respect to the at least two ferroelectric field effect transistors are arranged in series with an analog-to-digital converter.
Similar to Slesazeck, Jang teaches an electric circuit assembly (Fig. 1) comprising a ferroelectric memory (see page 7, par. 0104-0105).
Furthermore, Jang teaches at least two ferroelectric memory are arranged in series with an analog-to-digital converter (Fig. 6: 352).
Since Jang, Eliason and Slesazeck are from the same field of endeavor, the teachings described by Jang would have been recognized in the pertinent art of Slesazeck in combination with Eliason.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Jang with the teachings of Slesazeck in combination with Eliason for the purpose of increase calculation performance, see Jang’s page 11, par. 0173.
Regarding claim 26, Slesazeck in combination with Eliason the limitations with respect to claim 23.
However, the combination is silent with respect to wherein that VT states of the ferroelectric field effect transistor are measured with the aid of an analog-to-digital converter and adapted by means of a further adaptation step using a further programming step.
Similar to Slesazeck, Jang teaches a method for programming an electric circuit assembly comprising a ferroelectric memory (see page 7, par. 0103-0104).
Furthermore, Jang teaches VT states of the ferroelectric memory are measured with the aid of an analog-to-digital converter (Fig. 6: 352) and adapted by means of a further adaptation step using a further programming step (see page 8, par. 0086-0087).
Since Jang, Eliason and Slesazeck are from the same field of endeavor, the teachings described by Jang would have been recognized in the pertinent art of Slesazeck in combination with Eliason.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Jang with the teachings of Slesazeck in combination with Eliason for the purpose of increase calculation performance, see Jang’s page 11, par. 0173.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Slesazeck, Eliason and Nishimura’871 as applied to claim 18 above, and further in view of Jang et al. (U.S. 2021/0125048; hereinafter “Jang”).
Regarding claim 19, Slesazeck in combination with Eliason and Nishimura’871 teaches the limitations with respect to claim 18.
However, the combination is silent with respect to wherein that all drain lines of each column are connected to a dedicated analog-to-digital converter, and all source lines of each column are connected to the respective resistive element.
Similar to Slesazeck, Jang teaches an electric circuit assembly (Fig. 1) comprising a ferroelectric memory (see page 7, par. 0104-0105).
Furthermore, Jang teaches drain lines of each column are connected to a dedicated analog-to-digital converter, and all source lines of each column are connected to the respective resistive element (Fig. 6: 352 electrically connected to the columns of the array 310).
Since Jang, Eliason, Nishimura’871 and Slesazeck are from the same field of endeavor, the teachings described by Jang would have been recognized in the pertinent art of Slesazeck in combination with Eliason and Nishimura’871.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Jang with the teachings of Slesazeck in combination with Eliason and Nishimura’871 for the purpose of increase calculation performance, see Jang’s page 11, par. 0173.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Slesazeck and Eliason as applied to claim 14 above, and further in view of Noack et al. (U.S. 2020/0357455; hereinafter “Noack”).
Regarding claim 22, Slesazeck in combination with Eliason and teaches the limitations with respect to claim 14.
However, the combination is silent with respect to forming a multi-bit content-addressable memory, a positively programmed ferroelectric field effect transistor and negatively programmed ferroelectric field effect transistor are interconnected.
Similar to Slesazeck, Noack teaches an electric assembly comprising ferroelectric field effect transistor.
Furthermore, Noack teaches forming a multi-bit content-addressable memory (see page 3, par. 0030), a positively programmed ferroelectric field effect transistor and negatively programmed ferroelectric field effect transistor are interconnected (see pages 6-7, par. 0059-0060).
Since Noack, Eliason and Slesazeck are from the same field of endeavor, the teachings described by Noack would have been recognized in the pertinent art of Slesazeck in combination with Eliason.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Noack with the teachings of Slesazeck in combination with Eliason for the purpose of save area on chip of wafer to handle full programming voltage, see Noack’s page 10, par. 0089.
Allowable Subject Matter
Claim 25 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 25, there is no teaching or suggestion in the prior art of record to provide the recited steps for a programming, an electric voltage of +/- 4V is applied to a single ferroelectric field effect transistor, the source line and the drain line of the same row being supplied with a low voltage, preferably with a voltage of +/- 2.7V, and the word line of the same column being supplied with a lower voltage, preferably +/- 1.3V.
Response to Arguments
Applicant's arguments filed with respect to independent claims have been fully considered but they are not persuasive.
With respect to independent claims 14, 20 and 23, Applicant asserts that the combination of references requires using a plurality of input/output terminals which would not make it possible to adjust the voltage at the drain terminal of the FeFET by the resistive element only, see Applicant’s Remarks page 6. This remark is not considered persuasive since it appears that it is directed to subject matter not present in the claims. While raising an interesting point, the rejected claims do not appear to be drafted to recite a resistive element connected to the drain terminal and switched to ground on the other side to achieve a voltage adjustment at the drain terminal.
Furthermore, Applicant asserts that combining Slesazeck and Eliason would not have predictably resulted in the same function as the setup of the independent claims as a person of ordinary skill in the art would have expected such a combined setup to show a significantly higher electrical resistance, see Applicant’s Remarks page 6. This particular remark is not considered persuasive.
The teaching, suggestion or motivation test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Further, the teaching, suggestion, or motivation test is flexible and an explicit suggestion to combine the prior art is not necessary, see MPEP 2143(I)(G).
Finally, Applicant asserts that it is dubious whether or not the skilled person would combine the teachings of Slesazeck and Eliason since one of them is directed towards a FeFET while the other aims at a MOSFET and a ferroelectric capacitor, see Applicant’s Remarks page 7. This particular remark is not considered persuasive.
Eliason is not necessarily relied upon to show the features of the FeFET, although it should be appreciated that Eliason is directed to show an electric circuit with an electric resistance of a resistive element of 1MOhm to 100MOhm. Eliason is relied upon as a secondary reference to show desirable electrical resistance of a resistive element. In this regard, it appears that the remark is directed at singling out the limitations of the secondary reference as opposed to appreciate the combined teaches of the primary reference with the secondary reference.
For the above reasons, the previously applied rejections are considered proper and maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825