DETAILED ACTION
This Action is responsive to the Amendment filed on 03/27/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c).
In the present instance, Claim 3 recites the broad recitation “a total area of all recesses of the plurality of spaced apart recesses is less than half an area of the mirror surface,” and the claim also recites “in particular less than 10% of the mirror surface” which is the narrower statement of the range/limitation.
The claim is considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 8-9, 11-13, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe (US 2020/0089057).
Regarding claim 1, Watanabe (see, e.g., FIG. 1) discloses a mirror display comprising:
a mirror surface 42A having a mirror layer 42 comprising a plurality of spaced apart recesses 43 (see also FIG. 2) (Para 0068); and
a plurality of optoelectronic components 30 disposed on a drive layer 32, LED driver circuit board comprising at least leads 34 for driving the optoelectronic components 30 of the plurality of optoelectronic components 30 (Para 0056-Para 0057, Para 0061-Para 0062, Para 0067-Para 0068),
wherein:
the mirror layer 42 is arranged in an electrically insulated manner e.g., by 41 on the drive layer 32, LED driver circuit board (Para 0061), and
in a top view of the mirror surface 42A, in each case at least one optoelectronic component 30 of the plurality of optoelectronic components 30 is arranged in a recess 43 (see also FIG. 2) of the plurality of spaced apart recesses 43 (see also FIG. 2), an emission surface 30A of the at least one optoelectronic 30 in the recess 43 (see also FIG. 2) of the plurality of spaced apart recesses 43 (see also FIG. 2) projects beyond the mirror surface 42A.
Regarding claim 2, Watanabe (see, e.g., FIG. 1) teaches the mirror display according to claim 1, wherein the recesses 43 (see also FIG. 2) of the plurality of spaced apart recesses 43 (see also FIG. 2) correspond optoelectronic components 30 of the plurality of optoelectronic components 30 (Para 0067), or three optoelectronic components of the plurality of optoelectronic components are arranged in the recesses of the plurality of spaced apart recesses.
Regarding claim 4, Watanabe (see, e.g., FIG. 1) teaches the mirror display according to claim 1, wherein the recesses 43 (see also FIG. 2) of the plurality of spaced apart recesses 43 (see also FIG. 2) are arranged in rows and columns (Para 0067).
Regarding claim 8, Watanabe (see, e.g., FIG. 1) teaches the mirror display according to claim 1, wherein, in plan view, the optoelectronic components 30 of the plurality of optoelectronic components 30 arranged in the recesses 43 (see also FIG. 2) of the plurality of spaced apart recesses 43 (see also FIG. 2) lie at least partially in a plane of the mirror surface 42A.
Regarding claim 9, Watanabe (see, e.g., FIG. 1) teaches the mirror display according to claim 1, further comprising a planarization layer 41 on which the mirror layer 42 is deposited and which is arranged between the optoelectronic components 30 of the plurality of optoelectronic components 30 (Para 0061-Para 0063).
Regarding claim 11, Watanabe (see, e.g., FIG. 1) teaches the mirror display according to claim 1, wherein an emission area 30A of the at least one optoelectronic component 30 in the recess 43 (see also FIG. 2) of the plurality of spaced apart recesses 43 (see also FIG. 2) is smaller than an area of the recess 43 (see also FIG. 2) of the plurality of spaced apart recesses 43 (see also FIG. 2).
Regarding claim 12, Watanabe (see, e.g., FIG. 1) teaches the mirror display according to claim 1, further comprising at least one of: a transparent filler material that at least partially fills at least one recess of the plurality of spaced apart recesses such that a surface of the mirror layer is planarized; a partially transparent mirror layer disposed on the mirror layer and the recesses of the plurality of spaced apart recesses in plan view; a transparent protective layer 23 arranged in front of the mirror surface 42 in plan view (Para 0042-Para 0043); or a transparent protective layer arranged in front of the mirror surface in plan view, and a protective glass arranged in front of the mirror surface and the transparent protective layer in plan view.
Regarding claim 13, Watanabe (see, e.g., FIG. 1) teaches the mirror display according to claim 1, further comprising a supporting substrate 22 on which the driving layer 32, LED driver circuit board is deposited (Para 0042-Para 0045).
Regarding claim 18, Watanabe (see, e.g., FIG. 1) teaches the mirror display according to claim 1, in which the drive layer 32, LED driver circuit board comprises a plurality of electronic components e.g., base, conductive pattern in thin-film technology for supplying the optoelectronic components 30 of the plurality of optoelectronic components 30 (Para 0054-Para 0057).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 2020/0089057), in view of Brodoceanu (US 11,579,182).
Regarding claim 17, although Watanabe shows substantial features of the claimed invention, Watanabe fails to expressly teach the mirror display according to claim 1, in which the optoelectronic components of the plurality of optoelectronic components are formed with µ-LEDs whose edge length is less than 70 µm.
Brodoceanu (see, e.g., FIG. 5B) teaches the optoelectronic components of the plurality of optoelectronic components 254 are formed with µ-LEDs whose edge length is less than 70 µm for the purpose of utilizing light emitting sources with lower power requirements (col. 3, lines 55-64; col. 17, lines 36-45).
Examiner note: The Examiner notes Brodoceanu teaches that a LED may be an LED with feature sizes between sub-micron to hundreds of microns, and that sub-micron refers to structures smaller than 1 micrometer but typically larger than 0.1 µm.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the plurality of optoelectronic components of Watanabe to be formed with µ-LEDs whose edge length is less than 70 µm as described by Brodoceanu for the purpose of utilizing light emitting sources with lower power requirements (col. 3, lines 55-64).
Allowable Subject Matter
Claims 5-7, 10, and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571)270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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