Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement filed 11/05/2024 included a copy of “Written Opinion of ISA International Application PCT/US2021063568, dated 23 October 2024 ” and was included on the Notice of References Cited (PTO-892). Drawings Figures 1A-1E should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 10 -1 3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph , as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As per claim 10, the boundaries of claim scope are not clear. The claim recites “a second solution to the SMT routing problem” [lines 9-10] yet “SMT routing problem” does not appear to have clear antecedent basis. Thus, the claim is indefinite. As per claim 13, the boundaries of claim scope are not clear. What is meant by “if” [line 2] within the context of the claim is not recited. Thus, the claim is indefinite. The remaining claims, although not specifically mentioned, are rejected for incorporating the indefiniteness of their respective base claim by dependency. The following rejections are based on the Examiner’s best interpretation of the claims in view of the indefiniteness identified above. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claims 1- 6 and 14-19 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by D. Park et al. [“SP&R: Simultaneous Placement and Routing framework for standard cell synthesis”]. Taking claim 1 as exemplary of claims 1 and 14 [section III. implemented and validated on a Linux workstation with 2.4GHz Intel Xeon E3-2620 CPU and 256 GB memory] , a method for placement and routing of intra-cell transistors in an integrated circuit (IC) [Abstract Standard cell synthesis] , the method comprising: receiving inputs including a netlist [Fig. 1 Schematic of Cell Logic (Netlist Information)] , template definitions and technology design rules [ Layout Specification (Cell Architecture)] ] ; creating a first instance of a Satisfiability Modulo Theory (SMT) problem for placement and routing [section II.D. SMT Formulation] by translating the inputs into a set of SMT constraints [section II.C. Combination of Multiple Objectives] relating to the placement of a number of intra-cell transistors [section D. 1) Placement Formulation describes objectives and constraints relating to placement ] and routing for interconnects to the number of intra-cell transistors [ section D. 3) Routing Formulation describes objectives and constraints relating to Routing Formulation ] ; calling a SMT solver and using the set of SMT constraints generating a first solution to the SMT problem [ section II.A. executes, section II.C. explores the optimal standard cell layout that satisfies the complicated constraints, a first solution is inherently generated ] ; and if [section II.C. explores connotes if ] the first solution satisfies requirements of the inputs and a predetermined area requirement specified by a user [II.A. solve the given optimization problem , g iven netlist information and cell architecture, our framework executes concurrently with various DRV check through conditional design rule formulation , a predetermined area requirement being specified by a user is interpreted as inherent to the 7nm cell architecture for cell size and total metal length ] , creating and outputting a first layout for placement and routing of intra-cell transistors in the IC [section II.C. the optimal standard cell layout , section III. generates the “design layout” file ] . Taking claim 2 as exemplary of claims 2 and 15, wherein if the first solution does not satisfy requirements of the inputs and the predetermined area requirement, the method ends and the user notified [ this is interpreted as inherent to the SMT not being satisfiable for given requirements, inputs, constraints, objectives, etc. ] . Taking claim 3 as exemplary of claims 3 and 16, wherein if the first solution satisfies requirements of the inputs and the predetermined area requirement, the method ends and the SMT solver is not called again in an attempt to find another, more optimal solution satisfying the requirements of the input and the predetermined area requirement [ section II.C. the optimal standard cell layout ] . Taking claim 4 as exemplary of claims 4 and 17, further comprising if a predetermined number of layouts has not been created [ section III.C. In SMT formulation, the number of variables and constraints with respect to P&R dominantly relies on the number of FETs and nets] : creating another instance of the SMT problem [ section II.C. SP&R explores is interpreted to provide for another instance, section III. A . exhaustively searches the solution inherently creates another instance ] ; calling the SMT solver and generating another solution, and, if the solution satisfies the input and the predetermined area requirements, creating and outputting another layout for placement and routing of intra-cell transistors in the IC [ section II.C. SP&R explores is interpreted to provide for generating another solution, the function of if, section III.A. exhaustively searches the solution inherently generates another solution for creating and outputting another layout as cited above in claim 1 ] ; and repeating the creating of instances of the SMT problem, generating another solution, and creating and outputting another layout for placement and routing of intra-cell transistors in the IC [ section II.C. SP&R explores is interpreted to provide for repeating, section III.A. exhaustively searches the solution inherently provides for repeating] until the predetermined number of layouts has been created [section III.C. In SMT formulation, the number of variables and constraints with respect to P&R dominantly relies on the number of FETs and nets is interpreted as providing a predetermined number]. Taking claim 5 as exemplary of claims 5 and 18, further comprising determining from the layouts created and output, an optimal solution based on an area required or on the netlist or the technology design rules, and identifyi n g to the user the layout relating to the optimal solution [ if the SMT is satisfied the optimal solution is determined, see, also, the above citations, identifying to the user is inherently interpreted as the “design” layout” file the user would see ] . Taking claim 6 as exemplary of claims 6 and 19, fu rther comprising ranking the layouts created and output based on predefined metrics [section III.A. exhaustively searches the solution inherently provides a ranking to ultimately result in the optimal standard cell layout that satisfies complicated constraints of section II.C.] including one or more of a number of masks needed for the layout [section III.C. In SMT formulation, the number of variables and constraints with respect to P&R dominantly relies on the number of FETs and nets, section II . D. 4) multi-pattern-aware design rules, manufacturing SADP mask] , area required for the layout [supra] , and/or performance of the IC [Table I] , and outputting a list of ranked solutions [Table II] . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 7-13 are rejected under 35 U.S.C. 103 as being unpatentable over D. P ark et al. [“SP&R: Simultaneous Placement and Routing framework for standard cell synthesis”] in view of S. Banerjee et al. [Satisfiability Modulo Theory Based Methodology for Floorplanning in VLSI Circuits”]. As per claim 7 , D. Park et al. teach the features from which the claim depends. However, Park et al. do not teach further comprising prior to creating the first instance of the SMT problem for placement and routing: creating a SMT placement problem for the number of intra-cell transistors; calling the first SMT solver; generating a solution to the SMT placement problem; and if the solution to the SMT placement problem satisfies the requirements of the inputs, creating the first instance of the SMT problem for placement and routing with limited placement for the number of intra-cell transistor s. S. Banerjee et al. teach a method [section III. All experiments have been performed on a machine with 128 GB memory] for floorplanning with hard, soft and rotating blocks of an integrated circuit (IC) [Abstract] , the method comprising: creating a SMT placement problem [section II. Problem Formulation] for the number of blocks [blocks are interpreted to abstractly represent intra-cell transistors] ; calling the first SMT solver [section I. B. using Satisfiability Modulo Theory (SMT) ; generating a solution to the SMT placement problem [section I. B. find a satisfying assignment to a set of constraints that minimizes a given objective function]. A person having ordinary skill in the art to which the claimed invention pertains would have been motivated to perform these steps prior to creating the first instance of the SMT problem for placement and routing because” reduction in area occupied on a chip is of vital importance in obtaining a good circuit design” [Abstract lines 9-11]. A nd if the solution to the SMT placement problem satisfies the requirements of the inputs [a satisfying assignment to a set of constraints that minimizes a given objective function is found], a person having ordinary skill in the art to which the claimed invention pertains would have been motivated to creat e the first instance of the SMT problem for placement and routing with limited placement for the number of intra-cell transistor s because “Floorplanning helps to provide tentative location of IC building blocks. It is v itally important because it helps to determine size and yield of VLSI chips” [I. Introduction lines 1-4]. Therefore, given that floorplanning is well-known as a beneficial step early in the design process, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because cost of silicon is ultimately reduced. As per claim 8 , D. Park et al. teach a method for placement and routing of intra-cell transistors in an integrated circuit (IC) [Abstract Standard cell synthesis] , the method comprising: receiving inputs including a netlist of components available for use in the IC [Fig. 1 Schematic of Cell Logic (Netlist Information)] , template definitions of the components [Layout Specification (Cell Architecture)] and a predetermined area requirement for the IC specified by a user [interpreted as inherent to the 7nm cell architecture for cell size and total metal length] , and technology design rules specifying design requirements for the components [ section II. D. 4) Design Rule Constraints, Table I ] ; creating a first instance of a SMT placement and routing problem [ section II.D. SMT Formulation ] ; calling a second SMT solver and generating a first solution to the SMT placement and routing problem [ considering the disclosure and claim 13, section II.A. executes, section II.C. explores the optimal standard cell layout that satisfies the complicated constraints, a first solution is inherently generated ] ; and if [section II.C. explores connotes if] the first solution to the SMT placement and routing problem satisfies requirements of the inputs [II.A. solve the given optimization problem, given netlist information and cell architecture, our framework executes concurrently with various DRV check through conditional design rule formulation] , creating and outputting a first layout for placement and routing of intra-cell transistors in the IC [ [section II.C. the optimal standard cell layout, section III. generates the “design layout” file] . However, D. Park et al. do not teach creating a first instance of a Satisfiability Modulo Theory (SMT) placement problem by translating the inputs into a first set of SMT constraints relating to the placement of a number of intra-cell transistors in the IC; calling a first SMT solver and generating a first solution to the SMT placement problem; if the first solution to the SMT placement problem satisfies requirements of the inputs, using the first solution to the SMT placement problem. S. Banerjee et al. teach a method [section III. All experiments have been performed on a machine with 128 GB memory] for floorplanning with hard, soft and rotating blocks of an integrated circuit (IC) [Abstract] , the method comprising: creating a first instance of an SMT placement problem by translating the inputs into a first set of SMT constraints relating to the placement of a number of blocks [section II. Problem Formulation, blocks are interpreted to abstractly represent intra-cell transistors] ; calling a first SMT solver [section I. B. using Satisfiability Modulo Theory (SMT) ] and generating a first solution to the SMT placement problem [section I. B. find a satisfying assignment to a set of constraints that minimizes a given objective function]. A person having ordinary skill in the art to which the claimed invention pertains would have been motivated to perform these steps for using the first solution of the SMT placement problem because ”reduction in area occupied on a chip is of vital importance in obtaining a good circuit design” [Abstract lines 9-11]. A nd if the solution to the SMT placement problem satisfies the requirements of the inputs [a satisfying assignment to a set of constraints that minimizes a given objective function is found], a person having ordinary skill in the art to which the claimed invention pertains would have been motivated to creat e a first instance of the SMT problem for placement and routing with the first solution to the SMT placement problem because “Floorplanning helps to provide tentative location of IC building blocks. It is v itally important because it helps to determine size and yield of VLSI chips” [I. Introduction lines 1-4]. Therefore, given that floorplanning is well-known as a beneficial step early in the design process, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because cost of silicon is ultimately reduced. As per claims 9, wherein if the first solution to the SMT placement problem does not satisfy requirements of the inputs the method ends and the user notified [ this is interpreted as inherent to the SMT not being satisfiable for given requirements, inputs, constraints, objectives, etc. ] . As per claim 10, further comprising determining if a predetermined number of layouts have been created [ D. Park et al. section III.C. In SMT formulation, the number of variables and constraints with respect to P&R dominantly relies on the number of FETs and nets] , and if not: creating a second instance of the SMT placement problem [ S. Banerjee et al. section IV. Conclusion exploring all possibilities ] ; calling the first SMT solver [ S. Banerjee et al. section I. B. using Satisfiability Modulo Theory (SMT)] and generating a second solution to the SMT placement problem [ S. Banerjee et al. section I. B. find a satisfying assignment to a set of constraints that minimizes a given objective function] ; if the second solution to the SMT placement problem satisfies the requirements of the inputs [ S. Banerjee et al. section IV. Conclusion exploring all possibilities , A SMT based solution provides an optimal solution to the problem ] , creating a second instance of the SMT placement and routing problem using the second solution to the SMT placement problem [ following the combination, D. Park et al. section II.C. SP&R explores is interpreted to provide for a second instance, section III.A. exhaustively searches the solution inherently creates a second instance] ; calling the second SMT solver and generating a second solution to the SMT routing problem [ D. Park et al. section II.C. SP&R explores is interpreted to provide for generating another solution ] ; if [ D. Park et al. section II.C. explores connotes if] the second solution to the SMT placement and routing problem satisfies requirements of the inputs, creating and outputting a second layout for placement and routing of intra-cell transistors in the IC [ D. Park et al. section III.A. exhaustively searches the solution inherently generates another solution for creating and outputting another layout ] ; and repeating the above steps until the predetermined number of layouts has been created [ D. Park et al. section II.C. SP&R explores is interpreted to provide for repeating, section III.A. exhaustively searches the solution inherently provides for repeating , section III.C. In SMT formulation, the number of variables and constraints with respect to P&R dominantly relies on the number of FETs and nets is interpreted as providing a predetermined number ] . As per claim 11 , further comprising determining from the layouts created and output, an optimal solution based on an area required or on the netlist or the technology design rules and identifying to the user the layout relating to the optimal solution [ if the SMT is satisfied the optimal solution is determined, see, also, the above citations, identifying to the user is inherently interpreted as the “design” layout” file the user would see ] . As per claim 12, fu rther comprising ranking the layouts created and output based on predefined metrics [D. Park et al. section III.A. exhaustively searches the solution inherently provides a ranking to ultimately result in the optimal standard cell layout that satisfies complicated constraints of section II.C.] including one or more of a number of masks needed for the layout [D. Park et al. section III.C. In SMT formulation, the number of variables and constraints with respect to P&R dominantly relies on the number of FETs and nets, section II . D. 4) multi-pattern-aware design rules, manufacturing SADP mask] , area required for the layout [supra] , and/or performance of the IC [D. Park et al. Table I] , and outputting a list of ranked solutions [D. Park et al. Table II] . As per claim 13 , wherein if the first SMT solver and second SMT solver are the same SMT solver [ inherent, an SMT solver, although it is a user’s choice to use the solver available ] . The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See, for example, the additional NPL provided on PTO-892. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT LEIGH M GARBOWSKI whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1893 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 9-5 EST . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Jack Chiang can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-7483 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LEIGH M GARBOWSKI/ Primary Examiner, Art Unit 2851