DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 and 10-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by van Kervinck (US 2018/0068047; IDS, 01/22/2024).
van Kervinck is directed to a method of creating electronic devices such as semiconductor chips using a maskless lithographic exposure system such as charged particle multi-beamlet lithography. (Abstract). van Kervinck discloses the process performed by charged particle multi-beamlet lithography is also being referred to as an electron beam or e-beam exposure, which is a maskless exposure method. (Para, 0062). van Kervinck explains unique chips are designed to be unique with respect to other chips but does not exclude the possibility that more than one unique chip can be made using the invention, for example to create a spare unique chip for use in case the original unique chip is damaged, to create batches of the same chip or for any other reason. (Para, 0063). van Kervinck explains, a unique semiconductor chip that is functionally different from any other semiconductor chip may be referred to as a truly unique chip just as the creation of a visually readable unique ID on a chip may also be regarded as creating a unique chip. (Para, 0063). van Kervinck discloses that copies of the unique chip may be made by repeating the creation of the chip on different wafers or a single wafer may include one or more copies of the unique chip. (Para, 0063).
van Kervinck illustrates in Figure 1 an exemplary simplified unique chip 100 containing a common part 101 and an individualized area 102. (Para, 0064; Fig.1). van Kervinck explains the common part 101 may be replicated in other chips created on the wafer 24 resulting in multiple chips having the same identical part and the individualized area 102 may be different from other chips created on the wafer 24. (Para, 0064). van Kervinck illustrates this in the top of FIG. 1, where a wafer 24 is shown containing a unique chip 100 and 39 other unique chips, each unique chip having a different individualized area, where the combined common part 101 and individualized area 102 may result in a unique chip 100. (Para, 0064). van Kervinck discloses the individualized area 102 may be realized by selecting and writing specific structures, such as vias as illustrated in the middle part by the black dots. (Para, 0065; Fig.1). van Kervinck discloses other unique chips may have different structures such as vias resulting in the realization of different interconnections within a layer or between layers of the electronic circuit. van Kervinck also discloses that alternatively or additionally to specific structures, other connections between metal layers, connections between a metal layer and a gate e.g. in a contact layer, connections in a local interconnect layer, and/or P or N implants of certain parts of a transistor or diode may be selected and written to realize the individualized area 102. (Para, 0066). These disclosures and the illustrations of Figure 1 teach the limitation of claims 4-5.
van Kervinck discloses the common part 101 may be created using photolithography or charged particle multi-beam lithography and the individualized area is typically created using charged particle multi-beam lithography. (Para, 0067). van Kervinck discloses the pattern data used to control the beamlets in the charged particle lithography system may be designed to include a common chip design part that is used for multiple chips on the wafer and a unique part that is used for the individualized area. (Para, 0067). Van Kervinck explains it is undesirable to generate the pattern data including the common chip design part and the unique chip design part at once; therefore, the lithography system has been adapted to enable insertion of the unique chip design part into the pattern data at a later stage, i.e. close to the actual patterning of the wafer. (Para, 0067). Van Kervinck also explains unique chip design data can describe at least a portion of a chip layout design applicable for a single chip of the plurality of chips, wherein the unique chip design data includes design data describing at least one of a plurality of electrical circuit elements and a plurality of connections between electrical circuit elements, for at least one layer of the chip layout. (Para, 0036). Moreover, van Kervinck discloses the unique chip design data can include design data describing at least one of a plurality of electrical circuit elements and a plurality of connections between electrical circuit elements, for only one layer of the chip layout. (Para, 0037).
van Kervinck illustrates an exemplary process of creating a unique chip. (Para, 0140; Fig.7). van Kervinck shows a process of creating a unique chip according to another exemplary embodiment of the invention. (Para, 0140). van Kervinck discloses in this embodiment the identical part (e.g. common part 101) of the chip may be created using photolithography and the unique part (e.g. individualized area 102) of the chip may be created using charged particle multi-beamlet lithography. (Para, 0140). van Kervinck discloses at the beginning of the process of FIG. 7 the wafer may comprise five layers: a bottom metal layer 201, an isolation layer 202 (for example SiO2), under layers 203 and 204 (e.g. SOC+SiARC HM) and a top resist layer 205 (e.g. KrF resist). (Para, 0141;Fig.7). van Kervinck discloses that advantageously, the under layers 203 and 204 may be used for both the photolithography and the charged particle multi-beamlet lithography phase, thereby eliminating the need for a CMP step in the photolithography phase. (Para, 0141; Fig.7).
van Kervinck discloses for the creation of the identical part, the top layer 205 may undergo a mask exposure, e.g. using KrF laser, followed by a development step wherein structures defined by the mask may be removed from the resist layer 205. In an etching and stripping step these structures may be etched into the SOC under layer 204 and the resist is removed. (Para, 0142; Fig.7). These disclosures and the illustrations of Figure 7 teach the limitation of claim 1. ‘A method for manufacturing a semiconductor integrated circuit in each of a plurality of regions on a substrate, the method comprising: forming an electronic circuit as a part of the semiconductor integrated circuit in each of the plurality of regions by using a mask pattern fixed to a mask substrate…’ and the limitation of claim 3, ‘ The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the electronic circuit is formed on each of the plurality of regions which are disposed along a first direction and a second direction crossing the first direction on the substrate…’
van Kervinck discloses next, for the creation of the unique part, the wafer may receive an e-beam resist layer 206, covering the SOC under layer 204 including the etched part from the photolithography phase. (Para, 0143; Fig.7). van Kervinck discloses the top layer 206 may undergo an e-beam exposure followed by a development step wherein structures defined by the e-beams may be removed from the resist layer 206. (Para, 0143; Fig.7). These disclosures and the illustrations of Figure 7 teach the limitation of claim 1, ‘ A method for manufacturing a semiconductor integrated circuit in each of a plurality of regions on a substrate, the method comprising: … and forming a specific circuit, which expresses specific information specific to each of the semiconductor integrated circuits, on a part of each of the plurality of regions by using a variable shaping exposure apparatus having a variable shaping mask, wherein the specific circuits formed on the plurality of regions are different from each other.’ Moreover, these disclosures and illustrations teach the limitation of claim 3, ‘The method for manufacturing a semiconductor integrated circuit according to claim 1, …wherein a formation of the specific circuit includes relatively scanning the substrate on which a photosensitive film is formed with respect to a projection optical system of the variable shaping exposure apparatus in the first direction so as to expose the plurality of regions disposed along the first direction among the plurality of regions, the projection optical system projecting a pattern formed by the variable shaping mask.’
van Kervinck discloses in an etching and stripping step these structures may be etched into the SOC under layer 204 and the resist is removed. (Para, 0143; Fig.7). van Kervinck discloses next, the structures that are created in the SOC under layer 204 in both the photolithography phase and the charged particle multi-beamlet lithography phase may be etched into the SiARC under layer 203 and subsequently into the isolation layer 202, and the under layers 203, 204 may be stripped. (Para, 0143; Fig.7). van Kervinck discloses next a conductive layer 207 may be applied onto the etched and stripped isolation layer for both the identical part and the unique part of the chip. (Para, 0144; Fig.7). van Kervinck discloses a chemical vapor deposition with Tungsten (CVD-W) may be used and then chemical-mechanical planarization (CMP) may remove superfluous conductive material resulting in the wafer having the bottom metal layer and a layer comprising isolation material and conductive material as defined by the mask exposure and the e-beams. (Para, 0144; Fig.7). These disclosures and illustrations of Figure 7 as well as the disclosures of van Kervinck discussed above teach the limitations of claims 24-25.
van Kervinck discloses the maskless lithographic exposure system can comprise a data processing system and the pattern writer can be controlled by the data processing system. (Para, 0013). van Kervinck discloses the data processing system can be adapted to be fed by software data relating to a pattern to be transferred to a target such as a wafer in which the electronics devices are to be effected. (Para, 0013). van Kervinck discloses that provision of the patterning data to the pattern writer by said data processing system can be realized on the basis of said pattern data fed to the exposure system. (Para, 0013). van Kervinck discloses the method can comprise feeding a common part of the pattern data for electronics devices to be effected on the target at a first data entry of the data processing system, in particular at an instance thereof related to processing pattern data per target. (Para, 0013). van Kervinck discloses the method can comprise feeding unique pattern data or information at a second data entry of the data processing system at an instance thereof downstream the data flow in the data processing system relative to the first data entry, in particular capable of processing pattern data per part, such as field, of the target. (Para, 0013).
van Kervinck discloses the maskless lithographic exposure system can comprise an input generator for inputting a generated unique chip pattern or related information to a process job generator of the execution system in an encrypted manner, a machine control part of the pattern writer converting the encrypted code into patterning data, intermixed with the patterning data in an obfuscated manner. (Para, 0014). van Kervinck discloses the unique pattern data or related information can be generated at, or integral with the entry of unique chip pattern or related information, in particular in an obfuscated manner, e.g. utilizing encrypted association with a device number of the unique device created with said such created unique data or information. (Para, 0014). van Kervinck explains the pattern data processing system 318 may be configured to receive unique chip design data 430 from a unique data generator 330 and to insert the unique chip design data into the pattern data. (Para, 0125). Van Kervinck explains the pattern streamer 319 may be configured to receive unique chip design data 430 from a unique data generator 330 and to insert the unique chip design data into the pattern data. (Para, 0126; Fig.4B). van Kervinck discloses the unique chip design data may be transmitted to a lithography subsystem 316 with a process job and generally may be in a format that enables direct insertion into the pattern data. (Para, 0129). Van Kervinck discloses the unique chip design data 430 may be generated by the unique data generator 330 based on secret data 440 received from an external provider 340. (Para, 0130). Van Kervinck also discloses the secret data may be generated within the unique data generator 330 and it may be encrypted and decryptable by the unique data generator 330. (Para, 0130). Van Kervinck discloses the secret data 440 may include secret keys and/or secret IDs. (Para, 0130). These disclosures and the disclosures of van Kervinck as discussed above teach the limitations of claims 2 and 6-8.
van Kervinck discloses the unique data generator 330 may be realized as a black box device and the unique chip design data 430 may be generated by the back box device. (Para, 0131). van Kervinck discloses the black box device may be a source external to the maskless lithographic exposure system and is preferably located within a manufacturing part of the fab. (Para 0131). van Kervinck discloses the black box may be owned by a third party, e.g. an IP block owner or the owner of the manufactured chip, or a key management infrastructure owner. (Para, 0131). van Kervinck discloses, advantageously the black box can be located within the fab close to the operations of the lithography machine, thereby minimizing public exposure of the unique chip design data. (Para, 0131).
van Kervinck also illustrates a conceptual diagram of an exemplary charged particle lithography system 1A, divided into three high level sub-systems: a wafer positioning system 25, an electron optical column 20, and data path 30. (Para, 0085; Fig.3). van Kervinck discloses the wafer positioning system 25 moves the wafer 24 under the electron optical column 20 in the x-direction and it may be provided with synchronization signals from the data path sub-system 30 to align the wafer with the electron beamlets generated by the electron-optical column 20. (Para, 0085; Fig.3). van Kervinck discloses the electron-optical column 20 may include the charged particle multi-beamlet lithography machine 1. (Para, 0085; Fig.2-3). van Kervinck discloses switching of the beamlet blanker array 9 may also be controlled via the data path sub-system 30, using pattern bitmap data. (Para, 0085; Fig.3). These disclosures, the illustrations of Figure 3 and the disclosures of van Kervinck discussed above teach the limitations of claims 10-11, 16 and 20-23.
van Kervinck discloses and illustrates exemplary embodiments of a data path sub-system 30 are shown for a lithography system 301A-301D with control and data interfaces forming the data path sub-system 30. (Para, 0086; Fig.4A-4D). van Kervinck explains the diagrams show a hierarchical arrangement with three interfaces, a cluster interface 303, cluster element interface 305, and the lithography subsystem interfaces 307. (Para, 0086; Fig.4A-4D). van Kervinck discloses the subsystems 316 include, for example, a wafer load subsystem (WLS), wafer positioning subsystem (WPS), an illumination optics subsystem (ILO) for generating electron beamlets, a pattern streaming subsystem (PSS) for streaming beam switching data to the lithography element, a beam switching subsystem (BSS) for switching the electron beamlets on and off, a projection optics subsystem (POS) for projecting beamlets onto the wafer, a beam measurement subsystem (BMS), and a metrology subsystem (MES). (Para, 0086; Fig. 4A-4D). These disclosures, the illustrations of Figures 3 and 4A-4D and the disclosures of van Kervinck discussed above teach the limitations of claims 12-15 and 17-19.
Therefore, claims 1-8 and 10-25 are anticipated by the disclosures and illustrations of van Kervinck as discussed above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over van Kervinck as applied to claims 1-8 and 10-25 in paragraph 3 above, and further in view of Matsumoto (US 2006/0187719; IDS, 01/22/2024).
The disclosures of van Kervinck as discussed above fail to teach and/or suggest the limitation of claim 9, ‘ A method for manufacturing a semiconductor device comprising: packaging a plurality of semiconductor integrated circuits, which are manufactured by the method for manufacturing a semiconductor integrated circuit according to claim 6, to provide a plurality of semiconductor devices; and generating second interrelationship data expressing correspondence between the plurality of packaged semiconductor devices and the specific information expressed by the specific circuit of the semiconductor integrated circuit included in the plurality of semiconductor devices, based on the interrelationship data.’ However, the disclosures of van Kervinck further in view of the disclosures of Matsumoto provides such teachings.
Matsumoto is directed to ID generation for a semiconductor package or a semiconductor integrated circuit chip, a topographic characteristic to be utilized as specific information is selected from at least one topographic characteristic that the semiconductor package or the semiconductor integrated circuit has. (Abstract). Matsumoto discloses the selected topographic characteristic is measured as the specific information and an ID for identification is generated for the semiconductor package or the semiconductor integrated circuit chip based on the measured specific information. (Abstract).
Matsumoto outlines this process in Figure 2.
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Matsumoto discloses in a step S101, a topographic characteristic of a semiconductor package to be utilized as the physically random specific information is selected and a measurement point of the thus selected topographic characteristic (i.e., the specific information) is set, using the evaluation measurement section/evaluation information setting tool 101. (Para, 0064). Matsumoto explains the topographic characteristic of a semiconductor package herein means, for example, roughness that the surface of the package forms (in general, a plastic resin with which a silicon filler is mixed is used as a resin for packaging, forming roughness in the surface portion of a package), an angle of a lead wire (a bonding wire) connected to a semiconductor chip in a package, a contour of a bonding portion where a lead wire is connected to a bonding pad of a semiconductor chip, a shape of a bump (a bump connection part) used in lieu to a lead wire, and the like, and is not limited specifically only if it can be utilized as the physically random specific information. (Para, 0064). Matsumoto discloses next in a step S102, the topographic characteristic selected in the step S101, that is, the physically random specific information of the semiconductor package is measured and extracted using the measurement tool 102. (Para, 0065). Matsumoto discloses in step S103, the information (data) measured and extracted in the step S102 is processed for identification using the image processor (specific ID generating tool) 103, thereby generating a specific ID (package ID) for the target semiconductor package. (Para, 0066; Fig.2). Matsumoto explains the image processor 103 performs image processing of the data (for example, an image of a photo or the like obtained through observation by a surface SEM) measured by the measurement tool 102 and relating to the physically random specific information to allow the thus processed data to be used as a package ID. (Para, 0066; Fig.2). Matsumoto discloses, in this way, the specific ID generation for the semiconductor package is performed. (Para, 0066; Fig.2). The disclosures of van Kervinck as discussed above further in view of these disclosures and iilustrations of Matsumoto teach and/or suggest the limitations of claim 9.
It would have been obvious to one of ordinary skill in the art at the time of filing of the present application by Applicant to modify the disclosures of van Kervinck further in vie wo the disclosures of Matsumoto because both are directed to analogous methods of patterning semiconductor chips with unique IDs and the disclosures of Matsumoto disclose a method and tools that can be used to implement pattering of unique ID’s and/or chips such as the method of van Kervinck as the semiconductor package level.
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
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