DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 5 August 2026 of Applicants’ amendments in which claims 1, 5, 8, and 15 are amended.
Response to Arguments
Applicants’ arguments filed 5 August 2026 have been fully considered but they are not persuasive.
Applicants argue in the last paragraph of page 7 and with respect to claim 1 (and similarly with respect to independent claim 15) that Onozawa does not teach the subject matter newly added to the claim of “a sub-region of the power semiconductor device extending between the at least one first trench and the at least one second trench is located within an active region of the power semiconductor device, and a charge carrier extraction contact is arranged in the sub-region between the at least one first trench and the at least one second trench within the active region and is electrically connected to the base layer, wherein the sub-region is free of a source region.” Claim 1 (and claim 15) is rejected as being anticipated by Onozawa. A claim is anticipated only if each and every element as set forth in the claim is found, either expressly or inherently described, in a single prior art reference. MPEP §2131. As this principle applies to the present circumstance, Onozawa teaches in Fig. 6 a sub-region (region around 42 excluding 4) of the power semiconductor device extending between the at least one first trench (5) and the at least one second trench (35 or 35, 15) is located within an active region (e.g., active region of Fig. 6) of the power semiconductor device, and a charge carrier extraction contact (42) is arranged in the sub-region (region around 42 excluding 4) between the at least one first trench (5) and the at least one second trench (35 or 35, 15) within the active region (e.g., active region of Fig. 6) and is electrically connected to the base layer (11, 41) {see annotated copy of Onozawa’s Fig. 6, below; ¶0076}, wherein the sub-region (region around 42 excluding 4) is free of the source region (4).
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Applicants’ further argue in the first paragraph of page 8 and with respect to claim 1 that “[t]he region around element 42 in Onozawa’s Figure 6, which the Examiner relies upon, is not a sub-region between the first trench and the second trench within the active region as claimed.” However, as discussed in the preceding paragraph, Onozawa teaches in Fig. 6 a sub-region (region around 42 excluding 4) is between the at least one first trench (5) and the at least one second trench (35 or 35, 15) within the active region (e.g., active region identified by Onozawa within Fig. 6).
Applicants further argue in the last sentence of each of the first and penultimate paragraphs of page 8 and with respect to claim 1 that Onozawa does not teach “a sub-region between active trenches within the repeating cell structure of the active region.” Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. MPEP §2145(VI). As this principle applies to the present circumstance, claim 1 does not recite “a sub-region between active trenches within the repeating cell structure of the active region.”
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following subject matter must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 18 recites “the at least one second trench forms a closed loop enclosing the portion of the base layer when seen in the vertical direction,” which is not illustrated by the drawings. Paragraph [0081] of the PG-Pub discloses this feature is illustrated by Fig. 1F. But, as may be determined by inspection of Fig. 1F, this drawing does not illustrate a closed loop.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 4-11, and 13-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, last line, recites “a source region,” which is indefinite because it is unclear whether this refers to the source region recited in line 7. For the purpose of compact prosecution and to better comport with the remainder of the claim, this will be interpreted as “the source region.” Claims 2, 4-11, 13, 14, and 17-22 are rejected due to their dependence from base claim 1.
Claim 15, last line, recites “a source region,” which is indefinite because it is unclear whether this refers to the source region recited in line 15. For the purpose of compact prosecution and to better comport with the remainder of the claim, this will be interpreted as “the source region.” Claim 16 is rejected due to its dependence from base claim 15.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 19 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 19 recites “a voltage at the charge carrier extraction contact differs for different states during operation of the power semiconductor device,” which is a feature that is directed to a manner in which the claimed subject matter is intended to be employed and, accordingly, does not further limit the scope of the claim from which it depends.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 5, 8, 9, 14, 15, 19, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Onozawa et al. (US20150349103A1).
Regarding claim 1, as interpreted in view of the indefiniteness rejection, Onozawa teaches in Fig. 6 a power semiconductor device with a semiconductor body (2, 41, 43) extending in a vertical direction between an emitter side (top side) with an emitter electrode (9) and a collector side (bottom side) opposite the emitter side (top side) {¶0076}, the power semiconductor device comprising:
a drift layer (2) of a first conductivity type (N-type) {¶0046, 0075};
a base layer (11, 41) of a second conductivity type (P-type) different than the first conductivity type (N-type) extending between the drift layer (2) and the emitter side (top side) {¶0048};
a source region (4) of the first conductivity type (N-type) arranged on a side of the base layer (11, 41) facing away from the drift layer (1) {¶0046};
at least one first trench (5) extending from the emitter side (top side) into the drift layer (2) {¶0046};
an insulated trench gate electrode (7) extending into the first trench (5) {¶0047};
at least one second trench (35 or 35, 15) extending from the emitter side (top side) into the drift layer (2), the at least one second trench (35 or 35, 15) being arranged on a side of the at least one first trench (5) facing away from the source region (4) {¶0075};
an electrically conductive layer (37) extending into the second trench (35 or 35, 15), the electrically conductive layer being electrically insulated (by 36) from the base layer (11, 41) and the drift layer (2) {¶0075};
wherein
a portion (41) of the base layer (11, 41) arranged on a side of the at least one second trench (35 or 35, 15) facing away from the at least one first trench (5) extends from the emitter side (top side) at least as deep in the vertical direction towards the collector side (bottom side) as the at least one second trench (35 or 35, 15) {¶0076}; and
a sub-region (region around 42 excluding 4) of the power semiconductor device extending between the at least one first trench (5) and the at least one second trench (35 or 35, 15) is located within an active region (e.g., active region of Fig. 6) of the power semiconductor device, and a charge carrier extraction contact (42) is arranged in the sub-region (region around 42 excluding 4) between the at least one first trench (5) and the at least one second trench (35 or 35, 15) within the active region (e.g., active region of Fig. 6) and is electrically connected to the base layer (11, 41) {see annotated copy of Onozawa’s Fig. 6, below; ¶0076},
wherein the sub-region (region around 42 excluding 4) is free of the source region (4).
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Regarding claim 4, Onozawa teaches the power semiconductor device according to claim 1, and Onozawa further teaches wherein the charge carrier extraction contact (42) is electrically connected to the emitter electrode (9) {¶0076}.
Regarding claim 5, Onozawa teaches the power semiconductor device according to claim 1, and Onozawa further teaches wherein the electrically conductive layer (37) is configured to be at a same voltage as the emitter electrode (9) or at a positive voltage (unselected alternative) with respect to the emitter electrode during operation of the power semiconductor device {¶0072}.
Regarding claim 8, Onozawa teaches the power semiconductor device according to claim 1, and Onozawa further teaches wherein the at least one first trench (5) and the at least one second trench (35 or 35, 15) have a same depth in the vertical direction {¶0075, depth … of the first to third trenches 5 … and 35}.
Moreover, “[t]he Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
Regarding claim 9, Onozawa teaches the power semiconductor device according to claim 1, and Onozawa further teaches wherein the portion (41) extends below the at least one second trench (35 or 35, 15) towards the at least one first trench (5) {Fig. 6}.
Regarding claim 14, Onozawa teaches the power semiconductor device according to claim 1, and Onozawa further teaches wherein the power semiconductor device is an insulated gate bipolar transistor (IGBT) {¶0045}.
Regarding claim 15, as interpreted in view of the indefiniteness rejection, Onozawa teaches in Fig. 6 a method of producing a power semiconductor device comprising:
a) providing a semiconductor body (2, 41, 43) extending in a vertical direction between an emitter side (top side) and a collector side (bottom side) opposite the emitter side (top side) {¶0076};
b) forming at least one first trench (5) extending from the emitter side (top side) into the semiconductor body (2, 41, 43) {¶0046};
c) forming at least one second trench (35 or 35, 15) extending from the emitter side (top side) into the semiconductor body (2, 41, 43) {¶0075}; and
d) forming an electrically conductive layer (37) extending into the at least one second trench (35 or 35, 15) {¶0075};
wherein the power semiconductor device comprises:
an emitter electrode (9) at the emitter side (top side) {¶0076};
a drift layer (2) of a first conductivity type (N-type) {¶0046, 0075};
a base layer (11, 41) of a second conductivity type (P-type) different than the first conductivity type (N-type) extending between the drift layer (2) and the emitter side (top side) {¶0048};
a source region (4) of the first conductivity type (N-type) arranged on a side of the base layer (11, 41) facing away from the drift layer (2) {¶0046};
an insulated trench gate electrode (7) extending into the first trench (5) {¶0047};
wherein
the at least one first trench (5) extends from the emitter side (top side) into the drift layer (2) {Fig. 6};
the at least one second trench (35 or 35, 15) extends from the emitter side (top side) into the drift layer (2), the at least one second trench (35 or 35, 15) being arranged on a side of the at least one first trench (5) facing away from the source region (4) {Fig. 6};
the electrically conductive layer (37) is electrically insulated (by 36) from the base layer (11, 41) and the drift layer (2) {Fig. 6};
a portion (41) of the base layer (11, 41) arranged on a side of the at least one second trench (35 or 35, 15) facing away from the at least one first trench (5) extends from the emitter side (top side) at least as deep in the vertical direction towards the collector side (bottom side) as the at least one second trench (35 or 35, 15) {¶0076}; and
a sub-region (region around 42 excluding 4) of the power semiconductor device extending between the at least one first trench (5) and the at least one second trench (35 or 35, 15) is located within an active region (e.g., active region of Fig. 6) of the power semiconductor device, and a charge carrier extraction contact (42) is arranged in the sub-region (region around 42 excluding 4) between the at least one first trench (5) and the at least one second trench (35 or 35, 15) within the active region (e.g., active region of Fig. 6) and is electrically connected to the base layer (11, 41) {see annotated copy of Onozawa’s Fig. 6, below; ¶0076},
wherein the sub-region (region around 42 excluding 4) is free of the source region (4).
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Regarding claim 19, Onozawa teaches the power semiconductor device according to claim 1, and Onozawa further teaches wherein a voltage at the charge carrier extraction contact (42) differs for different states during operation of the power semiconductor device {[0010, 0012, 0054]}.
Examiner’s Note: The limitation whereby “a voltage at the charge carrier extraction contact differs for different states during operation of the power semiconductor device” is directed to a manner in which the claimed subject matter is intended to be employed and, accordingly, does not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding claim 20, Onozawa teaches the power semiconductor device according to claim 1, and Onozawa further teaches wherein the portion (41) of the base layer (11, 41) directly adjoins a bottom of the at least one second trench (35) in regions (regions in which 41 adjoins bottom of 35).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 10, 11, 13, 16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onozawa as applied to claim 1 (for claims 2 and 10, 11, 13, and 18) and claim 15 (for claim 16) above, and further in view of Naito (US20190148532A1).
Regarding claim 2, Onozawa teaches the power semiconductor device according to claim 1, and Onozawa further teaches wherein the at least one second trench (35 or 35, 15) is electrically inactive {see Examiner’s Note}.
Onozawa does not teach:
an enhancement layer of the first conductivity type is arranged in regions between the drift layer and the base layer, wherein the enhancement layer is more heavily doped than the drift layer; and
the enhancement layer is arranged between the at least one first trench and the at least one second trench.
In an analogous art, Naito teaches in Fig. 3 and paragraphs [0065] and [0078] an enhancement layer (60) of a first conductivity type (N-type) is arranged in regions between a drift layer (18) and a base layer (14), wherein the enhancement layer (60) is more heavily doped (N+) than the drift layer (18, N-); and the enhancement layer (60) is arranged between at least one first trench (30) and at least one second trench (40). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s power semiconductor device based on the teachings of Naito – such that an enhancement layer of the first conductivity type is arranged in regions between the drift layer and the base layer, wherein the enhancement layer is more heavily doped than the drift layer; and the enhancement layer is arranged between the at least one first trench and the at least one second trench – so a carrier injection enhancement effect (Injection Enhancement Effect: IE effect) can be increased, which can reduce Von. Naito ¶0083.
Examiner’s Note: The instant application defines electrically inactive to mean there is no electrically conductive channel formed along the at least one second trench in an on-state of the power semiconductor device {paragraph bridging pages 2 and 3}.
Regarding claim 10, Onozawa teaches the power semiconductor device according to claim 1, but Onozawa does not teach wherein the portion of the base layer extends in a cross-sectional view of the power semiconductor device in a lateral direction between two partial regions of the at least one second trench.
Naito teaches in Figs. 1-4 and paragraph [0075] a portion of a base layer (14) extends in a cross-sectional view of a power semiconductor device in a lateral direction between two partial regions (left and right portions of U-shaped 30) of at least one second trench (30). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s power semiconductor device based on the teachings of Naito – such that the portion of the base layer extends in a cross-sectional view of the power semiconductor device in a lateral direction between two partial regions of the at least one second trench – because all the claimed elements (e.g., base layer, two partial regions of a second trench) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Naito) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Regarding claim 11, Onozawa as modified by Naito teaches the power semiconductor device according to claim 10, but Onozawa does not teach wherein the at least one second trench contiguously forms the two partial regions of the at least one second trench.
Naito teaches in Fig. 1 at least one second trench (30) contiguously forms two partial regions (left and right portions of U-shaped 30) of the at least one second trench (30). The motivation for this modification is identified with respect to intermediate claim 10.
Regarding claim 13, Onozawa as modified by Naito teaches the power semiconductor device according to claim 10, but Onozawa does not teach wherein the two partial regions of the at least one second trench are arranged between two partial regions of the at least one first trench in a cross-sectional view of the power semiconductor device.
Naito teaches in Figs. 1, 3, and 4 two partial regions (left and right portions of U-shaped 30) of at least one second trench (30) are arranged between two partial regions (left and right portions of U-shaped 40) of at least one first trench (30) in a cross-sectional view of the power semiconductor device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s power semiconductor device based on the teachings of Naito – such that the two partial regions of the at least one second trench are arranged between two partial regions of the at least one first trench in a cross-sectional view of the power semiconductor device – because all the claimed elements (e.g., the specific arrangement of two partial regions of first and second trenches) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Naito) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Regarding claim 16, Onozawa teaches the method according to claim 15, but Onozawa does not expressly teach further comprising producing the power semiconductor device.
Naito teaches in Fig. 10 and paragraph [0034] manufacturing a power semiconductor device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s method based on the teachings of Naito – to include producing the power semiconductor device – because the skilled artisan could have applied Naito’s manufacturing technique in the same way (i.e., performing a manufacture so as to produce a product) to the method taught by Onozawa and the results (a produced power semiconductor device) would have been predictable to the skilled artisan. MPEP §2143(I)(C).
Regarding claim 18, Onozawa teaches the power semiconductor device according to claim 1, but Onozawa does not teach in the embodiment illustrated by Fig. 6 wherein the at least one second trench forms a closed loop enclosing the portion of the base layer when seen in the vertical direction.
Naito teaches in Fig. 1 at least one second trench (30) forms a closed loop enclosing a portion of a base layer (14) when seen in the vertical direction (downward). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s power semiconductor device based on the teachings of Naito, to achieve the above-identified subject matter, because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Furthermore, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
Examiner’s Note: Naito’s illustration of this feature is the same as Applicants’ illustration in Fig. 1F. Specifically, both illustrations show a U-shaped loop, which Applicants’ characterize as a “closed loop.” Moreover, “when seen in the vertical direction,” as recited in the claim, the loop appears closed when viewed looking down from the top of Naito’s drawing toward the bottom.
Claim(s) 6 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onozawa.
Regarding claim 6, Onozawa teaches the power semiconductor device according to claim 1, but Onozawa does not expressly teach in a single embodiment wherein the charge carrier extraction contact is subdivided in a plurality of segments, wherein the segments are arranged beside one another in a direction extending in parallel to a main extension direction of the at least one first trench.
Onozawa teach in an embodiment illustrated by Fig. 4 wherein a charge carrier extraction contact (42) is subdivided in a plurality of segments, wherein the segments are arranged beside one another in a direction (e.g., x1) extending in parallel to a main extension direction (x1) of at least one first trench (5) {see Annotated Copy of Onozawa’s Fig. 4, below}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s power semiconductor device based on the further of Onozawa – such that the charge carrier extraction contact is subdivided in a plurality of segments, wherein the segments are arranged beside one another in a direction extending in parallel to a main extension direction of the at least one first trench – because all the claimed elements (e.g., charge carrier extraction contact, segments, first trench) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Onozawa) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
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Regarding claim 17, Onozawa teaches the power semiconductor device according to claim 1, but Onozawa does not teach in the embodiment illustrated by Fig. 6 wherein the charge carrier extraction contact is configured to be electrically addressable separately from the emitter electrode during operation of the power semiconductor device.
Onozawa teaches in Figs. 4 and 6 wherein a charge carrier extraction contact (42) is configured to be electrically addressable separately from an emitter electrode (9) during operation of a power semiconductor device {see Examiner’s Note}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s power semiconductor device based on the further of Onozawa – such that the charge carrier extraction contact is configured to be electrically addressable separately from the emitter electrode during operation of the power semiconductor device – because all the claimed elements (e.g., charge carrier extraction contact, segments, emitter electrode, power semiconductor device) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Onozawa) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Furthermore, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
Examiner’s Note: Onozawa illustrates in Figs. 4 and 6 the first p-type base region (11) is separately addressable (using wire and the terminal end identified by label E) through charge carrier extraction contact (42), in the nearly identical manner that Applicants’ p-type base region (28) portion (6) is putatively separately addressable (using wire and the terminal end identified by label Ve) through charge carrier extraction contact (61) as illustrated by Applicants’ Figs. 1A, 1B, 1D, 1F, and 4.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onozawa as applied to claim 1 above, and further in view of Onozawa (US20130037853A1).
Regarding claim 7, Onozawa teaches the power semiconductor device according to claim 1, but Onozawa does not teach wherein an edge-to-edge distance between the at least one first trench and the at least one second trench is between 0.5 μm and 5 μm inclusive.
In an analogous art, Onozawa ‘853 teaches in Fig. 2 and paragraph [0132] an edge-to-edge distance between at least one first trench and at least one second trench is 2 μm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s power semiconductor device based on the teachings of Onozawa ‘853 – such that an edge-to-edge distance between the at least one first trench and the at least one second trench is between 0.5 μm and 5 μm inclusive – because all the claimed elements (e.g., first and second trenches, edge-to-edge distance) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Onozawa ‘853) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onozawa as applied to claim 1 above, and further in view of Matsuura (US20170033206A1).
Regarding claim 21, Onozawa teaches the power semiconductor device according to claim 1, but Onozawa does not teach wherein an enhancement layer of the first conductivity type is arranged in the sub-region between the at least one first trench and the at least one second trench.
In an analogous art, Matsuura teaches in Fig. 3 an enhancement layer (NHB) of a first conductivity type (N-type) is arranged in a sub-region (sub-region between T1 and T2) between at least one first trench (T1) and at least one second trench (T2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s power semiconductor device based on the teachings of Matsuura, to achieve the above-identified subject matter, to keep the balance of an overall hole flow. Matsuura [0057]. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Still further, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onozawa as applied to claim 1 above, and further in view of Sadamatsu et al. (US20120273836A1).
Regarding claim 22, Onozawa teaches the power semiconductor device according to claim 1, but Onozawa does not teach wherein the sub-region completely overlaps with the portion of the base layer when seen in the vertical direction.
In an analogous art, Sadamatsu teaches in Fig. 2 a sub-region (region including right half of 4) [between a first trench 7 and a second trench 10] completely overlaps with a portion (portion of 11 between 7 and 10) of a base layer (11) when seen in the vertical direction. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s power semiconductor device based on the teachings of Sadamatsu, to achieve the above-identified subject matter, because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Furthermore, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID WARD whose telephone number is (703)756-1382. The examiner can normally be reached 6:30-3:30 EST.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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