DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12 February 2026 has been entered.
Response to Amendment
The Office acknowledges receipt on 12 February 2026 of Applicants’ amendments in which claims 1 and 15 are amended.
Response to Arguments
Applicants’ arguments filed 12 February 2026 have been fully considered but they are not persuasive.
Applicants argue in the third paragraph of page 6 through the third paragraph of page 7 and with respect to claim 1 (and similarly with respect to independent claim 15) that Onozawa does not teach a charge carrier extraction contact arranged in a sub-region between the at least one first trench and the at least one second trench within the active region. See page 7, second paragraph. More specifically, Applicants argue:
Onozawa explicitly distinguishes between an active region and a termination structure portion. Specifically, Onozawa at paragraph [0045] states that the semiconductor device includes "an active region (as shown in FIG. 1) through which current flows when in an on-state, and a termination structure portion (not shown) that relaxes an electrical field on the front surface side of a semiconductor chip." Furthermore, Onozawa at paragraph [0076] explicitly discloses that "[t]he third p-type base region 41 on the outermost periphery of the active region is connected to the emitter electrode 9 via a p+-type contact region 42." Onozawa further describes that the guard ring 43 is "provided in the termination structure portion." See Onozawa, paragraph [0076]. See paragraph bridging pages 6 and 7.
And based upon this argument, Applicants draw the inference that Onozawa’s contact region 42 … is not located in a sub-region between first and second trenches within the active region as now recited by amended claims 1 and 15 [but is instead] … is positioned at the outermost periphery of the active region where the active region transitions to the termination structure portion. See page 7, second paragraph.
Amended claim 1 is rejected as being anticipated by Onozawa and recites, in relevant part, “a sub-region … extending between the at least one first trench and the at least one second trench is located within an active region …, and a charge carrier extraction contact is arranged in the sub-region between the at least one first trench and the at least one second trench within the active region and is electrically connected to the base layer.” Arguments presented by applicant cannot take the place of evidence in the record. MPEP 2145(I). As this principle applies to the present circumstance, Onozawa teaches in Fig. 6 a sub-region (region around 42) … extending between the at least one first trench (5) and the at least one second trench (35) is located within an active region (e.g., active region of Fig. 6) …, and a charge carrier extraction contact (42) is arranged in the sub-region (region around 42) between the at least one first trench (5) and the at least one second trench (35) within the active region (e.g., active region of Fig. 6) and is electrically connected to the base layer (11, 41) {see annotated copy of Onozawa’s Fig. 6, below; ¶0076}.
PNG
media_image1.png
670
900
media_image1.png
Greyscale
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, 5, 8, 9, 14, and 15 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Onozawa et al. (US20150349103A1).
Regarding claim 1, Onozawa teaches in Fig. 6 a power semiconductor device with a semiconductor body (2, 41, 43) extending in a vertical direction between an emitter side (top side) with an emitter electrode (9) and a collector side (bottom side) opposite the emitter side (top side) {¶0076}, the power semiconductor device comprising:
a drift layer (2) of a first conductivity type (N-type) {¶0046, 0075};
a base layer (11, 41) of a second conductivity type (P-type) different than the first conductivity type (N-type) extending between the drift layer (2) and the emitter side (top side) {¶0048};
a source region (4) of the first conductivity type (N-type) arranged on a side of the base layer (11, 41) facing away from the drift layer (1) {¶0046};
at least one first trench (5) extending from the emitter side (top side) into the drift layer (2) {¶0046};
an insulated trench gate electrode (7) extending into the first trench (5) {¶0047};
at least one second trench (35) extending from the emitter side (top side) into the drift layer (2), the at least one second trench (35) being arranged on a side of the at least one first trench (5) facing away from the source region (4) {¶0075};
an electrically conductive layer (37) extending into the second trench (35), the electrically conductive layer being electrically insulated (by 36) from the base layer (11, 41) and the drift layer (2) {¶0075};
wherein
a portion (41) of the base layer (11, 41) arranged on a side of the at least one second trench (35) facing away from the at least one first trench (5) extends from the emitter side (top side) at least as deep in the vertical direction towards the collector side (bottom side) as the at least one second trench (35) {¶0076}; and
a sub-region (region around 42) of the power semiconductor device extending between the at least one first trench (5) and the at least one second trench (35) is located within an active region (e.g., active region of Fig. 6) of the power semiconductor device, and a charge carrier extraction contact (42) is arranged in the sub-region (region around 42) between the at least one first trench (5) and the at least one second trench (35) within the active region (e.g., active region of Fig. 6) and is electrically connected to the base layer (11, 41) {see annotated copy of Onozawa’s Fig. 6, below; ¶0076}.
PNG
media_image1.png
670
900
media_image1.png
Greyscale
Regarding claim 4, Onozawa teaches the power semiconductor device according to claim 1, and Onozawa further teaches wherein the charge carrier extraction contact (42) is electrically connected to the emitter electrode (9) {¶0076}.
Regarding claim 5, Onozawa teaches the power semiconductor device according to claim 1, and Onozawa further teaches wherein, the electrically conductive layer (37) is configured to be at the same voltage as the emitter electrode (9) or at a positive voltage (unselected alternative) with respect to the emitter electrode during operation of the power semiconductor device {¶0072}.
Regarding claim 8, Onozawa teaches the power semiconductor device according to claim 1, and Onozawa further teaches wherein the at least one first trench (5) and the at least one second trench (35) have the same depth in the vertical direction {¶0075, depth … of the first to third trenches 5 … and 35}.
Moreover, “[t]he Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
Regarding claim 9, Onozawa teaches the power semiconductor device according to claim 1, and Onozawa further teaches wherein the portion (41) extends below the at least one second trench (35) towards the at least one first trench (5) {Fig. 6}.
Regarding claim 14, Onozawa teaches the power semiconductor device according to claim 1, and Onozawa further teaches wherein the power semiconductor device is an insulated gate bipolar transistor (IGBT) {¶0045}.
Regarding claim 15, Onozawa teaches in Fig. 6 a method of producing a power semiconductor device comprising:
a) providing a semiconductor body (2, 41, 43) extending in a vertical direction between an emitter side (top side) and a collector side (bottom side) opposite the emitter side (top side) {¶0076};
b) forming at least one first trench (5) extending from the emitter side (top side) into the semiconductor body (2, 41, 43) {¶0046};
c) forming at least one second trench (35) extending from the emitter side (top side) into semiconductor body (2, 41, 43) {¶0075}; and
d) forming an electrically conductive layer (37) extending into the at least one second trench (35) {¶0075};
wherein the power semiconductor device comprises:
an emitter electrode (9) at the emitter side (top side) {¶0076};
a drift layer (2) of a first conductivity type (N-type) {¶0046, 0075};
a base layer (11, 41) of a second conductivity type (P-type) different than the first conductivity type (N-type) extending between the drift layer (2) and the emitter side (top side) {¶0048};
a source region (4) of the first conductivity type (N-type) arranged on a side of the base layer (11, 41) facing away from the drift layer (2) {¶0046};
an insulated trench gate electrode (7) extending into the first trench (5) {¶0047};
wherein
the at least one first trench (5) extends from the emitter side (top side) into the drift layer (2) {Fig. 6};
the at least one second trench (35) extends from the emitter side (top side) into the drift layer (2), the at least one second trench (35) being arranged on a side of the at least one first trench (5) facing away from the source region (4) {Fig. 6};
the electrically conductive layer (37) is electrically insulated (by 36) from the base layer (11, 41) and the drift layer (2) {Fig. 6};
a portion of the base layer (11, 41) arranged on a side of the at least one second trench (35) facing away from the at least one first trench (5) extends from the emitter side (top side) at least as deep in the vertical direction towards the collector side (bottom side) as the at least one second trench (35) {¶0076}; and
a sub-region (region around 42) of the power semiconductor device extending between the at least one first trench (5) and the at least one second trench (35) is located within an active region (e.g., active region of Fig. 6) of the power semiconductor device, and a charge carrier extraction contact (42) is arranged in the sub-region (region around 42) between the at least one first trench (5) and the at least one second trench (35) within the active region (e.g., active region of Fig. 6) and is electrically connected to the base layer (11, 41) {see annotated copy of Onozawa’s Fig. 6, below; ¶0076}.
PNG
media_image1.png
670
900
media_image1.png
Greyscale
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 10, 11, 13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onozawa as applied to claim 1 (for claims 2 and 10, 11, 13) and claim 15 (for claim 16) above, and further in view of Naito (US20190148532A1).
Regarding claim 2, Onozawa teaches the power semiconductor device according to claim 1, and Onozawa further teaches wherein the at least one second trench (35) is electrically inactive {see Examiner’s Note}.
Onozawa does not teach:
an enhancement layer of the first conductivity type is arranged in regions between the drift layer and the base layer, wherein the enhancement layer is more heavily doped than the drift layer; and
the enhancement layer is arranged between the at least one first trench and the at least one second trench.
In an analogous art, Naito teaches in Fig. 3 and paragraphs [0065] and [0078] an enhancement layer (60) of a first conductivity type (N-type) is arranged in regions between a drift layer (18) and a base layer (14), wherein the enhancement layer (60) is more heavily doped (N+) than the drift layer (18, N-); and the enhancement layer (60) is arranged between at least one first trench (30) and at least one second trench (40). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s power semiconductor device based on the teachings of Naito – such that an enhancement layer of the first conductivity type is arranged in regions between the drift layer and the base layer, wherein the enhancement layer is more heavily doped than the drift layer; and the enhancement layer is arranged between the at least one first trench and the at least one second trench – so a carrier injection enhancement effect (Injection Enhancement Effect: IE effect) can be increased, which can reduce Von. Naito ¶0083.
Examiner’s Note: The instant application defines electrically inactive to mean there is no electrically conductive channel formed along the at least one second trench in an on-state of the power semiconductor device {paragraph bridging pages 2 and 3}.
Regarding claim 10, Onozawa teaches the power semiconductor device according to claim 1, but Onozawa does not teach wherein the portion of the base layer extends in a cross-sectional view of the power semiconductor device in a lateral direction between two partial regions of the at least one second trench.
Naito teaches in Figs. 1-4 and paragraph [0075] a portion of a base layer (14) extends in a cross-sectional view of a power semiconductor device in a lateral direction between two partial regions (left and right portions of U-shaped 30) of at least one second trench (30). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s power semiconductor device based on the teachings of Naito – such that the portion of the base layer extends in a cross-sectional view of the power semiconductor device in a lateral direction between two partial regions of the at least one second trench – because all the claimed elements (e.g., base layer, two partial regions of a second trench) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Naito) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Regarding claim 11, Onozawa as modified by Naito teaches the power semiconductor device according to claim 10, but Onozawa does not teach wherein the at least one second trench contiguously forms the two partial regions of the at least one second trench.
Naito teaches in Fig. 1 at least one second trench (30) contiguously forms two partial regions (left and right portions of U-shaped 30) of the at least one second trench (30). The motivation for this modification is identified with respect to intermediate claim 10.
Regarding claim 13, Onozawa as modified by Naito teaches the power semiconductor device according to claim 10, but Onozawa does not teach wherein the two partial regions of the at least one second trench are arranged between two partial regions of the at least one first trench in a cross-sectional view of the power semiconductor device.
Naito teaches in Figs. 1, 3, and 4 two partial regions (left and right portions of U-shaped 30) of at least one second trench (30) are arranged between two partial regions (left and right portions of U-shaped 40) of at least one first trench (30) in a cross-sectional view of the power semiconductor device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s power semiconductor device based on the teachings of Naito – such that the two partial regions of the at least one second trench are arranged between two partial regions of the at least one first trench in a cross-sectional view of the power semiconductor device – because all the claimed elements (e.g., the specific arrangement of two partial regions of first and second trenches) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Naito) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Regarding claim 16, Onozawa teaches the method according to claim 15, but Onozawa does not expressly teach further comprising producing the power semiconductor device.
Naito teaches in Fig. 10 and paragraph [0034] manufacturing a power semiconductor device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s method based on the teachings of Naito – to include producing the power semiconductor device – because the skilled artisan could have applied Naito’s manufacturing technique in the same way (i.e., performing a manufacture so as to produce a product) to the method taught by Onozawa and the results (a produced power semiconductor device) would have been predictable to the skilled artisan. MPEP §2143(I)(C).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onozawa.
Regarding claim 6, Onozawa teaches the power semiconductor device according to claim 1, but Onozawa does not expressly teach in a single embodiment wherein the charge carrier extraction contact is subdivided in a plurality of segments, wherein the segments are arranged beside one another in a direction extending in parallel to a main extension direction of the at least one first trench.
Onozawa teach in an embodiment illustrated by Fig. 4 wherein a charge carrier extraction contact (42) is subdivided in a plurality of segments, wherein the segments are arranged beside one another in a direction (e.g., x1) extending in parallel to a main extension direction (x1) of at least one first trench (5) {see Annotated Copy of Onozawa’s Fig. 4, below}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s power semiconductor device based on the further of Onozawa – such that the charge carrier extraction contact is subdivided in a plurality of segments, wherein the segments are arranged beside one another in a direction extending in parallel to a main extension direction of the at least one first trench – because all the claimed elements (e.g., charge carrier extraction contact, segments, first trench) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Onozawa) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
PNG
media_image2.png
585
744
media_image2.png
Greyscale
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onozawa as applied to claim 1 above, and further in view of Onozawa (US20130037853A1).
Regarding claim 7, Onozawa teaches the power semiconductor device according to claim 1, but Onozawa does not teach wherein an edge-to-edge distance between the at least one first trench and the at least one second trench is between 0.5 μm and 5 μm inclusive.
In an analogous art, Onozawa ‘853 teaches in Fig. 2 and paragraph [0132] an edge-to-edge distance between at least one first trench and at least one second trench is 2 μm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Onozawa’s power semiconductor device based on the teachings of Onozawa ‘853 – such that an edge-to-edge distance between the at least one first trench and the at least one second trench is between 0.5 μm and 5 μm inclusive – because all the claimed elements (e.g., first and second trenches, edge-to-edge distance) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Onozawa ‘853) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nakamura (US20160254375A1) teaches a semiconductor substrate includes a drift region and a collector region. The drift region is provided across an active area, an interface area, and an edge termination area. The collector region is provided only in the active area and forms part of a second surface. An emitter electrode is provided in the active area and contacts a first surface of the semiconductor substrate. A collector electrode is provided on the second surface of the semiconductor substrate and contacts the collector region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID WARD whose telephone number is (703)756-1382. The examiner can normally be reached 6:30-3:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.W.W./ Examiner, Art Unit 2891
/MATTHEW C LANDAU/ Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights