CTNF 18/269,504 CTNF 86178 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement Information disclosure statements (IDS) were submitted on 6/23/23, 3/26/25, and 3/26/25. Accordingly, the information disclosure statements are being considered by the examiner and initialed copies of the forms are attached to this correspondence. Election/Restrictions Applicant’s traversal in the Election on 5/8/26 is found persuasive and the Restriction Requirement is withdrawn. The Examiner notes it appears a restriction for a different case was inadvertently included in the present case, although it is unclear how that happened. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1 and 2 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Aoyagi et al. (US Patent No. 8,987,763) (“Aoyagi”) . Regarding Claim 1, Aoyagi teaches a light emitting device (Figure 1), comprising: a first conductivity type semiconductor layer (Figure 1, item 11); an active layer (Figure 1, item 12) on the first conductivity type semiconductor layer; a second conductivity type semiconductor layer (Figure 1, item 13) on the active layer; at least one or more electrode layers (Figure 1, item 22+42) on the second conductivity type semiconductor layer; and an insulating layer (Figure 1, item 31) on the at least one or more electrode layers, wherein at least one of the second conductivity type semiconductor layer and the electrode layer is configured to be positioned in the central region of the light emitting device (see Figure 1, note the electrode layer 22+42 extends from the top to the bottom of the device and therefore is “configured to be positioned in the central region of the light emitting device”). Regarding Claim 2, Aoyagi further teaches the boundary between the second conductivity type semiconductor layer and the electrode layer is configured to be positioned in the central region of the light emitting device (see Figure 1, note the boundary between the bottom of 13 and the inner side of 42, separated by 31, is in the “central region” of the light emitting device) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-22-aia AIA Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Aoyagi as applied to Claim 1 above, and further in view of Wu et al. (US Patent Application Publication No. 2016/0172253) (“Wu”) . Regarding Claim 3, Aoyagi teaches Claim 1 as indicated above. Aoyagi does not specifically teach the electrode layer comprises a magnetic layer. However, Aoyagi does teach connecting individual LEDs into an array for (see Figures 12A and 12B and associated text). Wu teaches using magnetic materials as electrodes in LED structures (¶0048, see Figures 6A-6K). It would have been obvious to a person having ordinary skill in the art at the time of effective filing to use the magnetic electrode materials of Wu in the device of Aoyagi, as Wu teaches magnetic electrodes aid in bonding the LED chips to a future substrate (¶0048) and It has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp. , 325 U.S. 327, 65 USPQ 297 (1945). See also In re Leshin , 227 F.2d 197, 125 USPQ 416 (CCPA 1960). MPEP § 2144.07 . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 4-18 are allowed. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: None of the prior art, alone or in combination, teaches “ an insulating member comprising a plurality of assembly holes on the first wiring line and the second wiring line; a plurality of light emitting devices in each of the plurality of assembly holes; a first electrode line configured to cross the central region of each of the plurality of light emitting devices; and a second electrode line configured to cross both side regions of each of the plurality of light emitting devices, wherein the light emitting device comprises: a first conductivity type semiconductor layer; an active layer on the first conductivity type semiconductor layer; a second conductivity type semiconductor layer on the active layer; at least one or more electrode layers on the second conductivity type semiconductor layer; and an insulating layer on the at least one or more electrode layers, wherein at least one of the second conductivity type semiconductor layer and the electrode layer is configured to be positioned in the central region of the light emitting device ” of Claim 4, “ an insulating member comprising a plurality of assembly holes on the first wiring line and the second wiring line; a plurality of light emitting devices in each of the plurality of assembly holes; an electrode line configured to cross the central region of each of the plurality of light emitting devices; and contact electrodes disposed on the insulating member and configured to connect both side regions of each of the plurality of light emitting devices to the first wiring line and the second wiring line, wherein the light emitting device comprises: a first conductivity type semiconductor layer; an active layer on the first conductivity type semiconductor layer; a second conductivity type semiconductor layer on the active layer; at least one or more electrode layers on the second conductivity type semiconductor layer; and an insulating layer on the at least one or more electrode layers, wherein at least one of the second conductivity type semiconductor layer and the electrode layer is configured to be positioned in the central region of the light emitting device ” of Claim 9, and “ a third conductivity type semiconductor layer on the at least one or more electrode layers; a second active layer on the third conductivity type semiconductor layer; and a fourth conductivity type semiconductor layer on the second active layer, wherein the first conductivity type semiconductor layer and the fourth conductivity type semiconductor layer comprise the same dopant, wherein the second conductivity type semiconductor layer and the third conductivity type semiconductor layer comprise the same dopant, and wherein the at least one or more electrode layers are configured to be positioned in the central region of the light emitting device ” of Claim 14, “ a third conductivity type semiconductor layer on the at least one or more electrode layers; a second active layer on the third conductivity type semiconductor layer; and a fourth conductivity type semiconductor layer on the second active layer, wherein the first conductivity type semiconductor layer and the fourth conductivity type semiconductor layer comprise the same dopant, wherein the second conductivity type semiconductor layer and the third conductivity type semiconductor layer comprise the same dopant, and wherein the at least one or more electrode layers are configured to be positioned in the central region of the light emitting device ” of Claim 17, and “ an insulating member comprising a plurality of assembly holes on the first wiring line and the second wiring line; a plurality of light emitting devices in each of the plurality of assembly holes; and an electrode line configured to cross the central region of each of the plurality of light emitting devices; and contact electrodes disposed on the insulating member and configured to connect both side regions of each of the plurality of light emitting devices to the first wiring line and the second wiring line, wherein the light emitting device comprises: a first conductivity type semiconductor layer; a first active layer on the first conductivity type semiconductor layer; a second conductivity type semiconductor layer on the first active layer; at least one or more electrode layers on the second conductivity type semiconductor layer; a third conductivity type semiconductor layer on the at least one or more electrode layers; a second active layer on the third conductivity type semiconductor layer; and a fourth conductivity type semiconductor layer on the second active layer, wherein the first conductivity type semiconductor layer and the fourth conductivity type semiconductor layer comprise the same dopant, wherein the second conductivity type semiconductor layer and the third conductivity type semiconductor layer comprise the same dopant, and wherein the at least one or more electrode layers are configured to be positioned in the central region of the light emitting device ” of Claim 18 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Song et al. (US Patent Application Publication No. 2022/0085097) Jeon (US Patent Application Publication No. 2021/0057393) Do et al. (US Patent Application Publication No. 2017/0250168) Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK W TORNOW whose telephone number is (571)270-7534. The examiner can normally be reached M-Th 6:30-4:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MARK W. TORNOW Primary Examiner Art Unit 2891 /MARK W TORNOW/Primary Examiner, Art Unit 2891 Application/Control Number: 18/269,504 Page 2 Art Unit: 2891 Application/Control Number: 18/269,504 Page 3 Art Unit: 2891 Application/Control Number: 18/269,504 Page 4 Art Unit: 2891 Application/Control Number: 18/269,504 Page 5 Art Unit: 2891 Application/Control Number: 18/269,504 Page 6 Art Unit: 2891 Application/Control Number: 18/269,504 Page 7 Art Unit: 2891 Application/Control Number: 18/269,504 Page 8 Art Unit: 2891
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