DETAILED ACTION
This Office Action is in response to Application filed June 28, 2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 and Subspecies A drawn to the embodiment shown in Fig. 1 of current application, claims 1, 4, 5, 11-20, 24-26 and 28, in the reply filed on January 2, 2026 is acknowledged. The Examiner notes that claims 2, 3, 6, 21-23 and 27 are not directed to Applicants’ elected Subspecies A drawn to the embodiment shown in Fig. 1 of current application for the following reasons: (1) Claims 2 and 3 are directed to nonelected species, because as shown in PLAN VIEW of Fig. 1 of current application, “an effective portion” YS “located between the opening portion” KS “and a center of the mask portion” 5 has only one low-level defective region rather than a plurality of low-level defective regions in the first or second direction as recited in claims 2 and 3. (2) Claim 6 is directed to a species that Applicants do not elect, because Applicants’ elected species shown in Fig. 1 of current application does not comprise regions containing voids recited on lines 24-26 of claim 6, while Fig. 16 of current application comprise regions A1 and A2 containing voids. (3) Claim 21 and its dependent claims 22 and 23 are directed to a species that Applicants do not elect, because the seed layer comprising the first and second seed layer recited in claim 21 is shown in Fig. 31 of current application. (4) Claim 27 is not directed to Applicants’ elected species shown in Fig. 1 of current application, because the semiconductor layer 8 comprises an edge face on the mask portion with the gap GP as recited in claim 26 rather than an integrated shape comprising no edge face on the mask portion.
Specification
The disclosure is objected to because of the following informalities: “the mask layer 4” should be replaced with “the mask layer 6” in paragraph [0047] of current application. Appropriate correction is required.
Claim Objections
Claims 1 and 11 are objected to because of the following informalities:
On line 10 of claims 1 and 11, the phrase “in a plan view” should be replaced with “in the plan view”, because “in a plan view” has already been recited on line 6 of claims 1 and 11.
On line 13 of claim 1, “a size of” should be inserted between “and” and “10”.
On line 14 of claim 1, “CL” should be delineated, because meanings of acronyms can change over time.
On line 16 of claim 1 and on line 21 of claim 11, “a a-axis” should be replaced with “an a-axis”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4, 5, 11-20, 24-26 and 28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claims 1 and 11, it is not clear what the limitation “a main substrate having a lattice constant different from a lattice constant of a GaN-based semiconductor” recited on lines 2-3 of claims 1 and 11 suggests, because (a) there are an infinite number of GaN-based semiconductors such as GaN, AlxGa1-xN where x can be any real number from 0 to 1, InyGa1-yN where y can be any real number from 0 to 1, BzGa1-zN where z can be any real number from 0 to 1, InaAlbGa1-a-bN where a and b can be any real number from 0 and 1, etc., and (b) therefore, the limitation cited above is either inherent since there is always a GaN-based semiconductor whose lattice constant is different from the lattice constant of the main substrate, or the limitation cited above is an incomplete limitation that does not specify what “a GaN-based semiconductor” exactly refers to.
(2) Also regarding claims 1 and 11, it is not clear whether “a GaN-based semiconductor” recited on lines 2-3 of claims 1 and 11 is the same with or different from “a GaN-based semiconductor” recited on line 7 of claims 1 and 11, because (a) if they are the same with each other, “a GaN-based semiconductor” recited on line 7 should be replaced with “the GaN-based semiconductor”, (b) however, in this case, it is not clear what the “lattice constant of a GaN-based semiconductor” recited on lines 2-3 refers to since due to distinct underlying structural features, a lattice constant of the GaN-based semiconductor grown in the area A or the claimed opening portion would be different from a lattice constant of the GaN-based semiconductor grown in the area B illustrated below,
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and (c) if the two limitations of “a GaN-based semiconductor” are different from each other, “a main substrate having a lattice constant different from a lattice constant of a GaN-based semiconductor” recited on lines 2-3 is indefinite as discussed above.
(3) Further regarding claims 1 and 11, it is not clear what the limitation “the semiconductor layer comprises an effective portion located between the opening portion and a center of the mask portion in a plan view” recited on lines 9-10 of claims 1 and 11 refers to, because (a) this limitation does not appear to make sense in that (i) the opening portion is a portion of the mask layer as recited on line 4 of claims 1 and 11, and (ii) the center of the mask portion is also a portion of the mask layer, (b) therefore, the claimed “effective portion located between the opening portion and a center of the mask portion in a plan view” should be a portion marked by an oval in the illustration below, which is also a part of the mask layer rather than a part of the semiconductor layer,
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and (c) therefore, the claimed “effective portion” does not exactly refer to the effective portion YS Applicants labeled as in the original disclosure, but rather refers to a peripheral portion of the mask layer 6 indicated by the oval illustrated above.
(4) Regarding claim 1, it is not clear what “a line defect” recited on line 14 refers to, because (a) Applicants do not claim “a line defect” per se, but rather claim that “a line defect is not measured by a CL method” on line 14, (b) therefore, depending on whether the line defect is an edge dislocation, a screw dislocation, a mixed dislocation or another type of a line defect, even the same CL method may or may not be able to measure the line defect, (c) furthermore, depending on whether the line defect is formed in a (substantially) vertical direction or in a (substantially) planar direction, even the same CL method may or may not be able to measure the line defect, and (d) however, Applicants do not specifically claim any of the features of the claimed “line defect”, rendering claim 1 indefinite.
(5) Further regarding claim 1, it is not clear what the limitation “in the low-level defective region, a line defect is not measured by a CL method (emphasis added)” recited on line 14 suggests, because (a) Applicants did not disclose what the term “a CL method” refers to in the original disclosure, and (b) if the term “a CL method” refers to “a Cathodoluminescence method”, it is still not clear what “a CL method” refers to, i.e. how “a CL method” is performed since (i) the term “a CL method” Applicants used in the original disclosure appears to imply that Applicants performed a single CL method on the claimed semiconductor structure rather than performing a plurality of CL methods with variations of all the available parameters of “a CL method”, and (ii) if Applicants had performed a single CL method on the claimed semiconductor structure, and then “a line defect is not measured by a CL method”, that does not necessarily suggest that other ones of ordinary skill in the art would not be able to measure a line defect by varying parameters of the CL method since (ii-a) Applicants did not originally disclose how “a CL method” is performed, and (ii-b) therefore, other ones of ordinary skill in the art may still be able to measure a line defect by controlling and optimizing the measurement conditions for the line defect.
(6) Regarding claims 1 and 19, it is not clear how “in the low-level defective region, a line defect is not measured by a CL method” recited on line 14 of claim 1 when “a threading dislocation density in the upper surface of the effective portion is 5 × 106 pieces/cm2 or less” as recited in claim 19, because (a) “a threading dislocation” is one of line defects, (b) therefore, the limitation recited on line 14 of claim 1 and the limitation of claim 19 appear to be contradictory to each other, (c) it is not clear whether “a threading dislocation” recited in claim 19 is not “a line defect” recited on line 14 of claim 1, or even though there are threading dislocations recited in claim 19 in the effective portion whose upper surface comprises at least one low-level defective region as recited on lines 11-12 of claim 1, the threading dislocations could not be measured “by a CL method”.
(7) Regarding claim 11, it is not clear what the limitations “when a surface roughness of a peeled surface obtained when the first portion is peeled from the mask portion is defined as first surface roughness, and a surface roughness of a peeled surface obtained when the second portion is peeled from the mask portion is defined as second surface roughness, the first surface roughness is less than or equal to the second surface roughness” recited on lines 15-19 suggests, because (a) these limitations do not appear to be directed to the claimed semiconductor substrate since the claimed semiconductor substrate comprises the first and second portion as recited on line 11 rather than a semiconductor substrate without the first and second portion as recited in the limitations above, (b) the limitations cited above appear to be what one would do and then measure after forming the claimed semiconductor substrate, and therefore, the limitations may be directed to an intended use of the claimed semiconductor substrate, (c) furthermore, the roughness of the peeled surfaces should depend on numerous parameters such as (i) the material compositions of the mask portion recited on line 5 and the semiconductor layer recited on line 6, (ii) how the semiconductor layer is deposited on the mask portion, (iii) how the semiconductor layer is peeled off from the mask portion, i.e. whether the semiconductor layer is mechanically peeled off or the semiconductor layer is peeled by any other means such as a laser ablation, and (iv) if the semiconductor layer is mechanically peeled off, how the mechanical force is applied, i.e. whether the mechanical force is applied vertically or laterally, whether the mechanical force is applied uniformly during the peeling off process or the mechanical force is varied during the peeling off process, and so on, and (d) therefore, the limitations cited above are indefinite since no one would be able to tell what kinds of peeled off surfaces would be obtained from the claimed semiconductor substrate without first knowing all those relevant parameters.
Claims 4, 5, 18-20, 24-26 and 28 depend on claim 1, and claims 12-17 depend on claim 11, and therefore, claims 4, 5, 12-20, 24-26 and 28 are also indefinite.
(8) Regarding claim 5, it is not clear what “a thickness of the effective portion” refers to, because (a) as discussed above, there is no semiconductor layer located between the opening portion and the center of the mask portion in the plan view, and (b) furthermore, it is not clear whether the thickness of the effective portion is a thickness of the largest portion of the semiconductor layer where no line defect is measured by the CL method recited in claim 1, or a thickness of an arbitrary portion of the semiconductor layer.
(9) Regarding claims 12-14, 16 and 17, it is not clear what the limitation “a value of a ratio of the second surface roughness to the first surface roughness is from 1.0 to 10” recited in claim 12, the limitation “a peeled surface obtained when the effective portion is peeled from the mask portion comprises a flat region having a size of 10 µm in a first direction along a width direction of the opening portion and 10 µm in a second direction orthogonal to the first direction and comprising no recessed portion with a major axis of 0.1 µm or more” recited in claim 13, and the limitation “the second surface roughness is less than 10 nm” recited in claim 14, the limitation “such an area ratio that the recessed portions with a major axis of 0.1 µm or more contained in the peeled surface of the first portion occupy the peeled surface is defined as a first recessed portion occupancy ratio, and such an area ratio that the recessed portions with a major axis of 0.1 µm or more contained in the peeled surface of the second portion occupy the peeled surface is defined as a second recessed portion occupancy ratio, the first recessed portion occupancy ratio is equal to or less than the second recessed portion occupancy ratio” recited in claim 16, and the limitation “an impurity concentration in the peeled surface of the first portion is higher than an impurity concentration in the peeled surface of the second portion” recited in claim 17 refer to, and whether they are features of the claimed semiconductor substrate, because (a) as discussed above with regard to claim 1, the peeling off process and the peeled surfaces are not germane to the claimed semiconductor substrate, and (b) the limitations of claims 12-14, 16 and 17 cited above depend on numerous parameters that Applicants do not claim.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 20 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Amended claim 1 recites that “a first direction along a width direction” recited on line 12 of claim 1 is already “a a-axis direction” as recited on line 16 of the amended claim 1, which is a <11-0> direction recited in claim 20. Applicants may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 5, 11-20, 24-26 and 28, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Wunderer (US 9,490,119).
In the below prior art rejections, the claim limitation “seed” specifies an intended use or field of use, and is treated as non-limiting since it has been held that in device claims, intended use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ 2d 1647 (Bd. Pat. App. & Inter. 1987).
Regarding claim 1, Wunderer discloses a semiconductor substrate (Fig. 3), comprising: a main substrate (10) (col. 5, lines 51-53) having a lattice constant different from a lattice constant of a GaN-based semiconductor, because (a) as discussed above under 35 USC 112(b) rejections, this limitation is indefinite, and (b) at least one of a sapphire substrate, a silicon substrate and a silicon carbide substrate mentioned by Wunderer should have a lattice constant that would inherently be different from a lattice constant of an arbitrarily selected GaN-based semiconductor since lattice constants of sapphire, silicon and silicon carbide are all different from each other, while “a GaN-based semiconductor” may have a single lattice constant; a mask layer (composite structure of 13 and 14 in Fig. 2) (col. 5, line 56) located above the main substrate and comprising an opening portion (opening portion corresponding to encircling/enclosing growth pattern 13 in Fig. 2) and a mask portion (14); a seed portion (portion of initial GaN film 12 corresponding to 13) (col. 5, lines 50-51), which is directed to an intended use of the portion of the initial GaN film 12 corresponding to the encircling/enclosing growth pattern 13, overlapping the opening portion in a plan view; and a semiconductor layer (unlabeled GaN layer grown over mask layer 14) comprising a GaN-based semiconductor (col. 6, lines 13-14) and disposed on the seed portion and the mask portion, wherein the semiconductor layer comprises an effective portion (portion of unlabeled GaN layer grown over mask layer 14 between two adjacent ridges 16 where no threading dislocations 18 propagate) located between the opening portion (opening portion corresponding to encircling/enclosing growth pattern 13 in Fig. 2) and a center of the mask portion (14) in a plan view, because (a) as discussed above under 35 USC 112(b) rejections, this limitation is indefinite, and (b) therefore, the effective portion can be interpreted to be a portion of the unlabeled GaN layer between two adjacent ridges 16, an upper surface of the effective portion comprises at least one low-level defective region, because (a) the term “low-level defective” is relative without Applicants’ specifically claiming how low the level of defects should be, and (b) the portion of the unlabeled GaN layer between two adjacent ridges 16 do not have any threading dislocations inside it as illustrated in Fig. 3, in the low-level defective region, a line defect is not measured by a CL method, because (a) this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and (b) as illustrated by Wunderer, the low-level defect region disposed between two adjacent ridges 16 has no threading dislocations, and a first direction (direction perpendicular to m-direction 15 shown in Fig. 2) (col. 6, lines 9-10) is a a-axis direction of the GaN-based semiconductor, because (a) Wunderer discloses that the growth direction of the unlabeled GaN layer is a c-direction (col. 4, lines 62-66), and (b) the lateral direction perpendicular to both the growth direction or the c-direction and the m-direction 15 shown in Fig. 2 is an a-axis direction, and the second direction (15 in Fig. 2) is an m-axis direction of the GaN-based semiconductor.
Wunderer differs from the claimed invention by not showing that the at least one low-level defect region is with a size of 10 µm in the first direction along a width direction of the opening portion and 10 µm in the second direction orthogonal to the first direction.
Wunderer further discloses that “For example, the concepts may be used to create conventional-sized devices on the order of 1×1 mm2 or device chiplets on the order of 10×10 μm2” (col. 4, lines 10-12), and that “Depending on the specific mask design, individual GaN-based chiplets (5 µm to 100 µm in diameter, and height of 2 to 20 µm)” (col. 7, lines 23-25).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the at least one low-level defect region can be with a size of 10 µm in the first direction along the width direction of the opening portion and 10 µm in the second direction orthogonal to the first direction, because (a) Wunderer discloses a device size on the order of 1×1 mm2, and individual GaN-based chiplet size of up to 100 µm in diameter, (b) therefore, the larger the device or chiplet is, the larger the lateral size of the mask layer 14 can be, (c) in this case, when the lateral size of the mask layer 14 shown in Fig. 3 of Wunderer is much larger than 10 µm in diameter, the claimed at least one low-level defective region can have a size of 10 µm in the first direction along the width direction of the opening portion and 10 µm in the second direction orthogonal to the first direction since more than half of or most of the mask layer 14 is not directly underneath the adjacent ridges 16 as shown in Fig. 3 of Wunderer, and (d) the claim is prima facie obvious without showing that the claimed ranges of the two sizes in the first and second direction achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 4, Wunderer further discloses that a size in the first direction (direction perpendicular to m-direction 15 shown in Fig. 2) of the effective portion (portion of unlabeled GaN layer grown over mask layer 14 between two adjacent ridges 16 where no threading dislocations 18 propagate) is larger than the width of the opening portion (opening portion corresponding to encircling/enclosing growth pattern 13 in Figs. 1 and 2).
Regarding claim 5, Wunderer differs from the claimed invention by not showing that a ratio of the size in the first direction to a thickness of the effective portion is 2.0 or more.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a ratio of the size in the first direction to a thickness of the effective portion can be 2.0 or more, because (a) as discussed above under 35 USC 112(b) rejections, the claim limitation of claim 5 is indefinite, and (b) therefore, an arbitrary region can be selected to meet the claim limitation when the unlabeled GaN layer shown in Fig. 3 of Wunderer is at least twice as large as the size of the at least one low-level defective region in the first direction, which would have been obvious to one of ordinary skill in the art since the thickness of the GaN layer can be sufficiently large to improve quality of semiconductor material layers deposited on the unlabeled GaN layer.
Regarding claims 18-20, 24, Wunderer further discloses for the semiconductor substrate according to claim 1 that the mask portion (14) is made of silicon oxide (col. 5, lines 65-67) (claim 18), a threading dislocation density in the upper surface of the effective portion (portion of unlabeled GaN layer between adjacent ridges 16) is 5 × 10⁶ pieces/cm² or less, because there are no threading dislocations in the effective portion disclosed by Wunderer (claim 19), the width direction of the opening portion (13) is a <11-20> direction of the semiconductor layer, which is “a a-axis direction” recited on line 16 of the amended claim 1 (claim 20), and the main substrate (10) is a silicon substrate (claim 24).
Regarding claim 25, Wunderer differs from the claimed invention by not showing that the width of the mask portion is 20 µm to 200 µm.
As discussed above, Wunderer discloses that “For example, the concepts may be used to create conventional-sized devices on the order of 1×1 mm2 or device chiplets on the order of 10×10 μm2” (col. 4, lines 10-12), and that “Depending on the specific mask design, individual GaN-based chiplets (5 µm to 100 µm in diameter, and height of 2 to 20 µm)” (col. 7, lines 23-25).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the width of the mask portion can be 20 µm to 200 µm, because (a) Wunderer discloses a device size on the order of 1×1 mm2, and individual GaN-based chiplet size of up to 100 µm in diameter, (b) therefore, the larger the device or chiplet is, the larger the lateral size of the mask layer 14 can be, and (c) the claim is prima facie obvious without showing that the claimed range of the width of the mask portion achieves unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 26, Wunderer further discloses for the semiconductor substrate according to claim 1 that the semiconductor layer (unlabeled GaN layer) comprises an edge face (face of ridge 16) on the mask portion (14).
Regarding claim 28, Wunderer differs from the claimed invention by not further comprising: a function layer disposed on the semiconductor layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Wunderer can further comprise a function layer disposed on the semiconductor layer, because the semiconductor substrate disclosed by Wunderer can be employed to form a semiconductor device, which would require a function layer such as a channel layer of a field effect transistor or a light-emitting layer of a light emitting device.
Please refer to the explanations of the corresponding limitations above.
Regarding claim 11, Wunderer discloses a semiconductor substrate (Fig. 3), comprising: a main substrate (10) having a lattice constant different from a lattice constant of a GaN-based semiconductor; a mask layer (composite structure of 13 and 14) located above the main substrate and comprising an opening portion (13) and a mask portion (14); a seed portion (portion of 12 corresponding to 13) overlapping the opening portion in a plan view; and a semiconductor layer (unlabeled GaN layer) comprising a GaN-based semiconductor and disposed on the seed portion and the mask portion, wherein the semiconductor layer comprises an effective portion (portion of unlabeled GaN layer between adjacent ridges 16) located between the opening portion and a center of the mask portion in a plan view, the effective portion comprises a first portion (portion close to ridge 16), and a second portion (portion remote from ridge 16) farther from the opening portion than the first portion and having an interval with the opening portion, and when a surface roughness of a peeled surface obtained when the first portion is peeled from the mask portion is defined as first surface roughness, and a surface roughness of a peeled surface obtained when the second portion is peeled from the mask portion is defined as second surface roughness, the first surface roughness is less than or equal to the second surface roughness, because (a) these limitations are indefinite as discussed above under 35 USC 112(b) rejections, and (b) in addition, these are not germane to the claimed invention since the claimed invention of the semiconductor structure comprises the first and second portion rather than the first and second portion having been peeled from the mask portion, and a first direction (direction perpendicular to m-direction 15 shown in Fig. 2) is a a-axis direction of the GaN-based semiconductor.
Wunderer differs from the claimed invention by not showing that the interval is 10 µm or more in the first direction along a width direction of the opening.
Wunderer further discloses that “For example, the concepts may be used to create conventional-sized devices on the order of 1×1 mm2 or device chiplets on the order of 10×10 μm2” (col. 4, lines 10-12), and that “Depending on the specific mask design, individual GaN-based chiplets (5 µm to 100 µm in diameter, and height of 2 to 20 µm)” (col. 7, lines 23-25).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the interval between the second portion and the opening portion in the first direction along the width direction of the opening portion can be 10 µm or more, because (a) Wunderer discloses a device size on the order of 1×1 mm2, and individual GaN-based chiplet size of up to 100 µm in diameter, (b) therefore, the larger the device or chiplet is, the larger the lateral size of the mask layer 14 can be, and the larger the lateral size of the mask layer 14 is, the larger the claimed interval would be, and (c) the claim is prima facie obvious without showing that the claimed range of the interval between the second portion and the opening portion achieves unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claims 12-14, the limitation “a value of a ratio of the second surface roughness to the first surface roughness is from 1.0 to 10” is indefinite as discussed above under 35 USC 112(b) rejections as well as not being germane to the claimed invention as discussed above with regard to claim 11 (claim 12), the limitation “a peeled surface obtained when the effective portion is peeled from the mask portion comprises a flat region having a size of 10 µm in a first direction along a width direction of the opening portion and 10 µm in a second direction orthogonal to the first direction and comprising no recessed portion with a major axis of 0.1 µm or more” is indefinite as discussed above under 35 USC 112(b) rejections as well as not being germane to the claimed invention as discussed above with regard to claim 11 (claim 13), the limitation “the second surface roughness is less than 10 nm” is indefinite as discussed above under 35 USC 112(b) rejections as well as not being germane to the claimed invention as discussed above with regard to claim 11 (claim 14).
Regarding claim 15, Wunderer further discloses for the semiconductor substrate according to claim 11 that in a plan view, the first portion is adjacent to the opening portion, and an interval between the second portion and the center of the mask portion is 30% or less a width of the mask portion, because (a) Applicants do not specifically claim what the second portion refers to, and (b) therefore, the second portion can be arbitrarily selected to meet the claim limitation.
Regarding claims 16 and 17, the limitation “when such an area ratio that the recessed portions with a major axis of 0.1 µm or more contained in the peeled surface of the first portion occupy the peeled surface is defined as a first recessed portion occupancy ratio, and such an area ratio that the recessed portions with a major axis of 0.1 µm or more contained in the peeled surface of the second portion occupy the peeled surface is defined as a second recessed portion occupancy ratio, the first recessed portion occupancy ratio is equal to or less than the second recessed portion occupancy ratio” is indefinite as discussed above under 35 USC 112(b) rejections as well as not being germane to the claimed invention as discussed above with regard to claim 11 (claim 16), and the limitation “an impurity concentration in the peeled surface of the first portion is higher than an impurity concentration in the peeled surface of the second portion” is indefinite as discussed above under 35 USC 112(b) rejections as well as not being germane to the claimed invention as discussed above with regard to claim 11 (claim 17).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 February 26, 2026