Prosecution Insights
Last updated: August 16, 2026
Application No. 18/270,077

SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE

Final Rejection §112
Filed
Jun 28, 2023
Priority
Dec 29, 2020 — JP 2020-219850 +1 more
Examiner
KIM, JAY C
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kyocera Corporation
OA Round
2 (Final)
49%
Grant Probability
Moderate
3-4
OA Rounds
4m
Est. Remaining
71%
With Interview

Examiner Intelligence

Grants 49% of resolved cases
49%
Career Allowance Rate
424 granted / 865 resolved
-19.0% vs TC avg
Strong +22% interview lift
Without
With
+21.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
49 currently pending
Career history
923
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
41.0%
+1.0% vs TC avg
§102
13.9%
-26.1% vs TC avg
§112
43.4%
+3.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 865 resolved cases

Office Action

§112
DETAILED ACTION This Office Action is in response to Amendment filed June 1, 2026. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “at least one low-level defective region” elongated in the first and second direction with the sizes recited on lines 11-13 of the amended claim 1 for all of the silicon, sapphire, silicon carbide and ScAlMgO4 main substrate recited on line 2 of the amended claim 1 must be shown or the feature canceled from the claim, because (a) as discussed below under 35 USC 112(a) rejections, Applicants did not actually measure and observe the claimed sizes of the “at least one low-level defective region” elongated in the first and second direction for all of the main substrate materials recited in the amended claim 1, and (b) different main substrate materials would inherently result in different sizes of the “at least one low-level defective region” elongated in the first and second direction due to different kinetics of growth of the first semiconductor layer comprising the GaN-based semiconductor, not to mention different signs and magnitudes of strains between the main substrate and the GaN-based semiconductor. No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections Claims 1, 4, 5, 32 and 35 are objected to because of the following informalities: On lines 15-16 of claim 1, “a m-axis” should be replaced with “an m-axis”. On line 3 of claims 4 and 5 and on line 2 of claims 32 and 35, “comprising” should be replaced with “comprises” to be grammatically correct. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1, 4, 5, 18, 19, 24-26, 28, 29 and 31-35 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention. (1) Regarding claim 1, Applicants originally disclosed the claimed sizes of the “at least one low-level defective region” in the first and second direction recited on lines 11-13, but Applicants did not originally disclose that the claimed sizes of the “at least one low-level defect region” in the first and second direction would result from “a main substrate comprising silicon, sapphire, silicon carbide, or ScAlMgO4” as recited on line 2 of the amended claim 1, because (a) Applicants originally disclosed in paragraph [0053] of current application that “Examples of the heterogeneous substrate include a silicon (Si) substrate, a sapphire (Al2O3) substrate, a silicon carbide (SiC) substrate, and a ScAlMgO4 substrate”, and (b) however, Applicants did not originally disclose that the claimed sizes of the “at least one low-level defective region” in the first and second direction would also be measured and observed for all of the main substrate material compositions listed in paragraph [0053] of current application since the four material compositions for the main substrate are mere “Examples” or suggestions rather than the material compositions for the main substrate with which Applicants actually measured and observed the claimed sizes of the “at least one low-level defect region” in the first and second direction. (2) Also regarding claim 1, Applicants did not originally disclose that “the upper surface” of the first semiconductor layer comprising the GaN-based semiconductor recited on line 7 “comprises at least one low-level defective region with a size of 10 µm in a first direction along a width direction of the first opening portion and a size of 10 µm in a second direction orthogonal to the first direction” as recited on lines 11-13, because (a) as the deleted limitation “of the effective portion” on line 11 of the amened claim 1 clearly indicates, the claimed sizes in the first and second direction are sizes of the “effective portion” of the upper surface of the first semiconductor layer comprising the GaN-based semiconductor, (b) in other words, the originally disclosed sizes are associated with the effective portion YS shown in Fig. 1 of current application, (c) however, the newly claimed sizes are sizes of “the upper surface” of the first semiconductor layer comprising the GaN-based semiconductor, which is indicated by the arrow illustrated below, which does not have the claimed size at least along the x-direction, (d) this point is further substantiated by the amended claims 4, 5, 32 and 35 since Applicants claim “the first semiconductor comprising an effective portion located on the mask portion” on lines 3-4 of the amended claims 4 and 5, and on lines 2-3 of new claims 32 and 35, which at least implicitly indicates that the claimed sizes in the first and second direction recited on lines 11-13 of the amended claim 1 are the sizes of the upper surface of the first semiconductor layer comprising the GaN-based semiconductor recited on line 7 of the amended claim 1, and (e) in other words, Applicants originally disclosed that the width of the effective portion YS is 10 µm, while Applicants claim that the sum of the width of the two effective portions YS and the width of the non-effective portion is 10 µm in the amended claim 1, resulting in the currently claimed effective portion YS being a rectangle, while the originally disclosed effective portion YS is a square. PNG media_image1.png 368 488 media_image1.png Greyscale (3) Further regarding claim 1, Applicants did not originally disclose that “the low-level defect region is free from line defects extending in a [sic] m-axis direction of the GaN-based semiconductor” as recited on lines 15-16, because (a) Applicants originally disclosed in the Abstract and paragraph [0004] of current application that “a line defect is not measured by a CL method in the low-level defective region”, (b) however, Applicants’ inability to measure a line defect by “a CL method” does not necessarily suggest that there are no line defects whatsoever since (i) it does not appear that Applicants used all the available CL methods, and all the possible CL method parameters, and (ii) advancement of science and technology allows one to observe a feature that was not observed before, and therefore, even if Applicants may not have observed a line defect by a CL method, that does not necessarily suggest that there would not be any line defect measured with the advancement of science and technology that would improve resolution of “a CL method”, (c) Applicants did not originally disclose in which direction the line defect in the limitation “a line defect is not measured by a CL method in the low-level defective region” extends, (d) on the contrary, Applicants originally disclosed in paragraph [0110] of current application that “By suppressing the generation of voids in the back surface of the ELO semiconductor layer 8, line defects in the surface (surface layer) of the ELO semiconductor layer 8 may be reduced (emphases added)”, “An m-plane of the ELO semiconductor layer 8 is vulnerable to stress, and therefore defects are likely to be generated (emphasis added)”, “The line defects are assumed to have been generated due to a crystal slip along the m-plane”, and that “In a specific cross section parallel to the c-plane, a dislocation extending in the m-axis direction (assumed to be a mixed dislocation in which an edge dislocation and a screw dislocation are combined) may be observed as a line defect (emphases added)”, and (e) therefore, the limitation “the low-level defective region is free from line defects extending in a [sic] m-axis direction of the GaN-based semiconductor” as recited on lines 15-16 is contradictory to Applicants’ original disclosure cited above, and thus the amended claim 1 fails to comply with the written description requirement. Claims 4, 5, 18, 19, 24-26, 28, 29 and 31-35 depend on claim 1, and therefore, claims 4, 5, 18, 19, 24-26, 28, 29 and 31-35 also fail to comply with the written description requirement. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1, 4, 5, 18, 19, 24-26, 28, 29 and 31-35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. (1) Regarding claim 1, it is not clear what the limitation “the low defect region” recited on line 14 refers to, because (a) while Applicants claim “at least one low-level defective region” on lines 11-12, Applicants do not claim “a low defect region” before claiming “the low defect region”, and (b) therefore, the limitation “the low defect region” lacks the antecedent basis. (2) Also regarding claim 1, it is not clear what the limitation “the low-level defective region is free from line defects” recited on line 15 refers to, because (a) as discussed above under 35 USC 112(a) rejections, this limitation fails to comply with the written description requirement, and (b) therefore, it is not clear whether the limitation suggests that (i) the low-level defective region is free from a plurality of line defects, but there can be a single line defect, or (ii) the low-level defective region is free from any kind of line defects, which may also fail to comply with the Enablement requirement. (3) Further regarding claim 1, it is not clear what the “line defects” recited on line 15 refer to, and whether the “line defects” are a single type of line defects or can be different and a plurality of types of line defects, because Applicants do not claim what a single line defect is, not to mention what the “line defects” are. (4) Still further regarding claim 1, it is not clear what the limitation “line defects extending in a [sic] m-axis direction of the GaN-based semiconductor” recited on lines 15-16 suggests that all of the line defects are perfectly and entirely aligned with the m-axis direction, because (a) as discussed above under 35 USC 112(a) rejections, this limitation fails to comply with the written description requirement, and (b) therefore, it is not clear whether the entirety of the line defects are elongated in the m-axis direction, or the limitation cited above refers to a general direction of all of the line defects. Claims 4, 5, 18, 19, 24-26, 28, 29 and 31-35 depend on claim 1, and therefore, claims 4, 5, 18, 19, 24-26, 28, 29 and 31-35 are also indefinite. (5) Regarding claim 19, it is not clear whether “the low defective region” recited on line 3 refers to “the low-level defective region” recited on lines 11-12 of the amened claim 1, or “the low defect region” recited on line 14 of the amended claim 1. (6) Further regarding claim 19, it is not clear what the limitation “the threading dislocation is detected as a dark spot” recited on line 6 suggests, because (a) it is not clear whether the limitation suggests that the threading dislocation is detected as an absolutely dark spot regardless of the surrounding structure, or as a dark spot relative to the surrounding structure, (b) if it is the former, it is not clear whether Applicants observed the absolutely dark spot with a visible light, an infrared, an ultraviolet, or some other electromagnetic wave, and (c) if it is the latter, it is not clear what the measurement condition is or measurement conditions are in addition to whether Applicants observed the absolutely dark spot with a visible light, an infrared, an ultraviolet, or some other electromagnetic wave since a relative brightness or a relative darkness would depend on the measurement condition(s). Response to Arguments Applicants’ arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Choe et al. (US 2014/0077223) Chen et al. (US 10,340,421) Applicants' amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C KIM/Primary Examiner, Art Unit 2815 /J. K./Primary Examiner, Art Unit 2815 July 7, 2026
Read full office action

Prosecution Timeline

Jun 28, 2023
Application Filed
Jun 28, 2023
Response after Non-Final Action
Mar 03, 2026
Non-Final Rejection mailed — §112
Apr 24, 2026
Interview Requested
May 12, 2026
Examiner Interview Summary
May 12, 2026
Applicant Interview (Telephonic)
Jun 01, 2026
Response Filed
Jul 09, 2026
Final Rejection mailed — §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
49%
Grant Probability
71%
With Interview (+21.6%)
3y 6m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 865 resolved cases by this examiner. Grant probability derived from career allowance rate.

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