DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of 12/19/2025 of Group I (claims 1-7, 10-14, 16, 18, 19, 27, 30, 35, and 36) in the reply filed on 12/19/2025 is acknowledged.
Claim 33 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/19/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 10-12, 18, 30, 35, and 36 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ishii (US 2001/0040246).
Regarding claims 1, 35, and 36, Ishii discloses and electronic device comprising and electronic component comprising a semiconductor substrate comprising: a base substrate (Fig.4, numeral 1); a mask layer (4) that is located on the base substrate (1), and comprises an opening portion (B1) and a mask portion (B2); and a semiconductor layer (5) that comprises a GaN-based semiconductor located ([0075]) over the base substrate (1) exposed through the opening portion and over the mask portion, wherein the semiconductor layer (5) comprises a first portion (B2) located on the mask portion (4), and a second portion (B1) that is located on the opening portion and has a lower dislocation density of non-threading dislocations in a cross section of the semiconductor layer taken along a thickness direction than the first portion (B2) (Fig.4; [0077]; note: laterally bent dislocations in (B2) do not propagate in vertical direction, i.e. they are non-treading dislocations).
Regarding claim 2, Ishii discloses wherein in the first portion (Fig.4, numeral B2), a threading dislocation density on an upper surface of the semiconductor layer is lower than the non-threading dislocation density in the cross section of the semiconductor layer taken along the thickness direction ([0077]; note: dislocations in (B2) are non-threading dislocations).
Regarding claim 3, Ishii discloses in the second portion (Fig.4, numeral B1), a threading dislocation density in an upper surface of the semiconductor layer (5) is higher than the non-threading dislocation density in the cross section of the semiconductor layer taken along the thickness direction ([0077]; note: dislocations in (B1) are threading dislocations).
Regarding claim 5, Ishii discloses wherein the first portion is located between the opening portion and a center of the mask portion in plan view (Fig.4).
Regarding claim 10, Ishii discloses wherein a width of the opening portion is 0.1 mm or more and 30 mm or less ([0130]).
Regarding claim 11, Ishii discloses wherein the base substrate comprises: a main substrate (Fig. 4, numeral 1); and a semiconductor film (2) that is located on the main substrate (1), overlaps with at least the opening portion of the mask layer (4), and comprises GaN or a GaN-based semiconductor, and the semiconductor layer is in contact with the semiconductor film ([0093]).
Regarding claim 12, Ishii discloses wherein the semiconductor layer comprises, in the first portion (B2), a third portion located on the mask portion (4), and a fourth portion that is located closer to a surface of the semiconductor layer than the third portion is, and has a non-threading dislocation density lower than the third portion ([0077]).
Regarding claim 18, Ishii discloses wherein the semiconductor layer (5) comprises an edge on the mask portion (4).
Regarding claim 27, Ishii discloses wherein the semiconductor layer further comprises a dislocation region comprising threading dislocations located in the surface of the semiconductor layer (Fig.4; part of a surface of (5 ) in B1), and a difference region obtained by subtracting a surface region of the second portion (surface of (5) in (B1)) from the dislocation region is smaller than the surface region of the second portion (note: “a dislocation region” and “ and a surface region of the second portion” are not clearly defined and any parts of a surface of (5) can be considered as a “dislocation region” and “a surface region of the second portion”)..
Regarding claim 30, Ishii discloses wherein a dislocation density of threading dislocations is higher in the second portion (B1) than in the first portion (B2) ([0077]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii.
Regarding claim 4, Ishii discloses a semiconductor substrate comprising: a base substrate (Fig.4, numeral 1); a mask layer (4) that is located on the base substrate (1), and comprises an opening portion and a mask portion (Fig.4); and a semiconductor layer (5) that comprises a GaN-based semiconductor ([0077]) located over the base substrate (1) exposed through the opening portion and over the mask portion (4), wherein the semiconductor layer comprises a first portion (B2) located on the mask portion (4), the first portion comprises non-threading dislocations ([0077]; note: bent dislocations do not propagate in vertical direction, i.e. they are non-threading dislocations), and the semiconductor layer comprises, in the first portion (B2), a third portion located on the mask portion (center part of (B2)), and a fourth portion that is located closer to a surface of the semiconductor (side portions of (B2)).
Ishii does not disclose a threading dislocation density in the first portion is 5 x 106/cm2 or lower layer than the third portion is, and has a non-threading dislocation density lower than the third portion.
Ishi however discloses forming a high-quality GaN crystal region B2 containing a sharply reduced number of threading dislocations ([0077]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to have a threading dislocation density in the claimed range for the purpose of forming a high-quality GaN crystal.
Regarding claim 6, Ishii does not disclose a threading dislocation density in the first portion is 5 x 108/cm2 or lower layer than the third portion is, and has a non-threading dislocation density lower than the third portion.
Ishi however discloses forming a high-quality GaN crystal region B2 containing a sharply reduced number of threading dislocations ([0077]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to have a threading dislocation density in the claimed range for the purpose of forming a high-quality GaN crystal.
Claim(s) 7 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishii as applied to claim 5 above, and further in view of Hahn (US 2005/0003572).
Regarding claim 7, Ishii does not disclose wherein the base substrate comprises a monocrystalline silicon substrate.
Hahn however discloses that the base substrate comprises a silicon substrate ([0017]). Hahn further discloses epitaxially growing a buffer layer (2) on a substrate (1) ([0043]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Ishii with Hahn to have the base substrate comprises a monocrystalline silicon substrate for the purpose reducing the cost and increasing semiconductor yield (Hahn, [0017], [0020]).
Regarding claim 19, Ishii does not disclose wherein the semiconductor layer has an integrated shape without an edge on the mask portion, and comprises a hollow portion that overlaps with the center of the mask portion in plain view.
Hahn however discloses that the semiconductor layer (Fig.13D, numeral 5) has an integrated shape without an edge on the mask portion (3), and comprises a hollow portion (130) that overlaps with the center of the mask portion (3) in plain view ([0055]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Ishii with Hahn to have the semiconductor layer with integrated shape without an edge on the mask portion, and comprises a hollow portion that overlaps with the center of the mask portion in plain view for the purpose of stress relieving (Hahn, [0065]).
Claim(s) 13, 14, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ishi as applied to claim 1 above, and further in view of Ishibashi (US 2007/0217460).
Regarding claim 13, Ishii does not disclose wherein in the cross section of the semiconductor layer taken along the thickness direction, an impurity concentration of the first portion is higher than an impurity concentration in the second portion.
Ishibashi however discloses wherein in the cross section of the semiconductor layer taken along the thickness direction, an impurity concentration of the first portion (Fig. 1, numeral 104) is higher than an impurity concentration in the second portion (106) ([0114]; [0135]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Ishii with Ishibashi to have in the cross section of the semiconductor layer taken along the thickness direction, an impurity concentration of the first portion is higher than an impurity concentration in the second portion for the purpose controlling vertical/lateral growth (Ishibashi, [0139]).
Regarding claim 14, Ishii does not disclose wherein the semiconductor layer comprises, in the first portion, a third portion located on the mask portion, and a fourth portion that is located closer to a surface of the semiconductor layer than the third portion is, and has a lower impurity concentration than the third portion.
Ishibashi however discloses wherein the semiconductor layer comprises, in the first portion, a third portion located on the mask portion, and a fourth portion that is located closer to a surface of the semiconductor layer than the third portion is, and has a lower impurity concentration than the third portion ([0114]; [0135]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Ishii with Ishibashi to have in the first portion, a third portion located on the mask portion, and a fourth portion that is located closer to a surface of the semiconductor layer than the third portion is, and has a lower impurity concentration than the third portion for the purpose controlling vertical/lateral growth (Ishibashi, [0139]).
Regarding claim 16, Ishi does not disclose wherein the first portion comprises, in a surface of the first portion of the semiconductor layer, a sixth portion, and a seventh portion that is located closer to the second portion than the sixth portion is, and has a lower impurity concentration than the sixth portion.
Ishibashi however discloses wherein the first portion comprises, in a surface of the first portion of the semiconductor layer, a sixth portion, and a seventh portion that is located closer to the second portion than the sixth portion is, and has a lower impurity concentration than the sixth portion ([0114]; [0135]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Ishii with Ishibashi to have the first portion comprises, in a surface of the first portion of the semiconductor layer ,a sixth portion, and a seventh portion that is located closer to the second portion than the sixth portion is, and has a lower impurity concentration than the sixth portion for the purpose controlling vertical/lateral growth (Ishibashi, [0139]).
Conclusion
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891