The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-9, 12, 18-19, 24 and 30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (2018/0188616).
Regarding claims 1 and 30, Jeong et al. teach in figure 4 and related text a display device comprising a display panel, comprising a first active area and at least one second active area (arbitrarily chosen), wherein the second active area is located on an outer side of the first active area, and the display panel further comprises:
a substrate SUB1;
a plurality of grid lines GL and a plurality of data lines DL that are located on the substrate, wherein the plurality of grid lines and the plurality of data lines are intersecting and insulated, the plurality of sub-pixels are located at a position defined by the plurality of grid lines and the plurality of data lines and are capable of displaying under driving of the plurality of grid lines and the plurality of data lines, an outermost data line of the data lines is located at a junction of the first active area and the second active area (chosen as such), and no dummy pixel is set on a side (on the left side) of the outermost data line located at the junction on the substrate away from the first active area;
a plurality of first conductive patterns (chosen as one of the GL, DL or Px lines), wherein the first conductive patterns are at least located in the second active area, and at least one first conductive pattern of the first conductive patterns are electrically connected to one grid line of the grid lines,
wherein the at least one first conductive pattern located in the second display area is set at an end of the one grid line and has a protruding structure (see figures 2, 3 and 6) toward an adjacent grid line, the protruding structure has a first part and a second part along an extension direction of the data lines, and the first part of the protruding structure is electrically connected to an output terminal of GOA circuit in a peripheral area through vias; and
a plurality of second conductive patterns (chosen as another one of the GL, DL and Px lines), located in the second active area and electrically connected to outermost data line of the data lines located at the junction; wherein orthographic projections of part of the first conductive patterns on the substrate overlap with orthographic projections of the second conductive patterns on the substrate (located at the junction), and the second part of the protruding structure overlaps with at least one second conductive pattern of the second conductive patterns.
Regarding claim 2, Jeong et al. teach in figure 4 and related text that the orthographic projection of the at least one second conductive pattern on the substrate are located within the orthographic projection of the first conductive pattern on the substrate (chosen as such).
Regarding claim 3, Jeong et al. teach in figure 4 and related text that another first conductive pattern of the first conductive patterns extends from the first active area to the second active area (chosen as such), and is electrically connected to the common electrode; and the orthographic projection of the another first conductive pattern of the pattern on the substrate overlaps with an orthographic projection of the outmost data line located at the junction on the substrate.
Regarding claim 5, Jeong et al. teach in figure 4 and related text that the second active area comprises a first dummy capacitance (located in areas DUA since said area comprises dummy pixel electrodes and dummy data lines and dummy parasitic capacitances inherently located therein, see also figure 6 area NDA), the at least one first conductive pattern is regarded as a first electrode of the first dummy capacitance, and the at least second conductive pattern is regarded as a second electrode of the first dummy capacitance.
Regarding claim 6, Jeong et al. teach in figure 4 and related text that the second active area comprises a first dummy transistor (located in area DUA), a gate of the dummy transistor is electrically connected to the one grid line, a first end of the dummy transistor is electrically connected to the outmost data line located at the junction, and a second end of the dummy transistor is arranged in isolation (the area located between the transistors).
Regarding claim 7, Jeong et al. teach in figure 4 and related text that a part region of the at least one first conductive pattern is regarded as the gate of the dummy transistor; the at least one second conductive pattern comprises a first conductive part and second conductive parts (arbitrarily chosen), the first conductive part is disconnected from the second conductive part, the first conductive part is regarded as the first end of the dummy transistor (located in DUA area), and the second conductive part is regarded as the second end of the dummy transistor.
Regarding claim 8, Jeong et al. teach in figure 4 and related text that a quantity of the dummy transistor is less than or equal to half a quantity of rows of the sub-pixels (since figure 4 depicts that the pixels in the DUA area are less than pixels on the PA area).
Regarding claim 9, Jeong et al. teach in figure 4 and related text that each of the grid lines GL divides the outmost data line DA located at the junction into a plurality of data line segments; the first active area comprises a plurality of transistors, part of the data line segments are electrically connected to the transistors, at least part of the data line DDL segments that are not connected to the transistors are electrically connected to the dummy transistors (located in area DUA).
Regarding claim 12, Jeong et al. teach in figure 4 and related text that the display panel comprises a second dummy capacitance, the another first conductive pattern is regarded as a first electrode of the second dummy capacitance, a part line segment of the outmost data line located at the junction is regarded as a second electrode of the second dummy capacitance (see above); wherein an area (arbitrarily chosen) of an orthographic projection of a part of the another first conductive pattern that is located in the second active area on the substrate is greater than an area of an orthographic projection of a part of the another first conductive pattern that is located in the first active area on the substrate.
Regarding claim 18, Jeong et al. teach in figure 4 and related text that a quantity of the second dummy capacitance is greater than or equal to half a quantity of rows of the sub-pixels.
Regarding claim 19, Jeong et al. teach in figure 4 and related text that each of the grid lines divides the outermost data line located at the junction into a plurality of data line segments; an orthographic projection of at least part of the data line segments on the substrate overlaps with the orthographic projection of the another first conductive patterns on the substrate.
Regarding claim 24, Jeong et al. teach in figure 4 and related text that the display panel further comprises a third conductive pattern (arbitrarily chosen), the third conductive pattern is electrically connected to the common electrode COM, the third conductive pattern is at least located in the second active area, and at least part region of the third conductive pattern is located between the at least one first conductive pattern and the outermost data line located at the junction (chosen as such); wherein an orthographic projection of the at least part region of the third conductive pattern on the substrate does not overlap with the orthographic projection of the data line located at the junction on the substrate.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (2018/0188616).
Regarding claim 4, Jeong et al. do not teach that an outer contour of the orthographic projection of the at least one second conductive pattern on the substrate is located within an outer contour of the orthographic projection of the at least one first conductive pattern on the substrate.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form an outer contour of the orthographic projection of the at least one second conductive pattern on the substrate is located within an outer contour of the orthographic projection of the at least one first conductive pattern on the substrate, in Jeong et al.’s device in order to simplify the processing steps of making the device.
Regarding claim 10, Jeong et al. teach in figure 4 and related text that the data line segments that are not connected to the transistors are electrically connected to the dummy transistors, and the data line segments electrically connected to the transistors and the data line segments electrically connected to the dummy transistors are arranged at intervals, but do not teach that the quantity of the dummy transistors is equal to half the quantity of rows of the sub-pixels.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the quantity of the dummy transistors equal to half the quantity of rows of the sub-pixels in Jeong et al.’s device in order to adjust the device characteristics according to the requirements of the application in hand.
Response to Arguments
1. Applicants argue that Jeong does not teach that “no dummy pixel is set on a side of the outermost data line located at the junction on the substrate away from the first active area”, as recited in claims 1 and 30.
1. The claims require that no dummy pixel is set on a side of the outermost data line. Figure 4 depicts that no dummy pixel is set on a the left side of the outermost data line. Therefore, Jeong teaches that “no dummy pixel is set on a side of the outermost data line located at the junction on the substrate away from the first active area”, as required by claims 1 and 30.
2. Applicants argue that Jeong does not teach that any “clement that can correspond to the "protruding structure" defined in the amended claim 1 of the present application, and Jeong is also silent in that the second part of the protruding structure overlaps with at least one second conductive pattern of the second conductive patterns”.
2. Figures 2, 3 and 6 depict pixel Px, pixel 1 and pixel Px being respectively “protruding structures”.
Furthermore, figure 6 of Jeon depicts that the second part of the protruding structure Px overlaps with at least one second conductive pattern of the second conductive patterns.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
O.N. /ORI NADAV/
5/22/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
Prosecution Insights