The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Election/Restrictions
Applicant’s election of the embodiment of figures 4-5 in the reply filed on 12/19/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-9, 12, 18, 24 and 30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (2018/0188616).
Regarding claims 1 and 30, Jeong et al. teach in figure 4 and related text a display device comprising a display panel, comprising a first active area and at least one second active area (arbitrarily chosen), wherein the second active area is located at one side of the first active area, and the display panel further comprises:
a substrate SUB1;
a plurality of sub-pixels Px located on the substrate and arranged in array, wherein the plurality of sub-pixels are located in the first active area, and each of the plurality of sub-pixels comprises a common electrode COM (see figure 6);
a plurality of grid lines GL and a plurality of data lines that are located on the substrate, wherein the plurality of grid lines and the plurality of data lines DL are intersecting and insulated, the plurality of sub-pixels are located at a position defined by the plurality of grid lines and the plurality of data lines, at least one of the data lines is located at a junction of the first active area and the second active area (chosen as such);
a plurality of first conductive patterns (chosen as one of the GL and DL lines), wherein the first conductive patterns are at least located in the second active area, and the first conductive patterns are electrically connected to one of the grid lines or the common electrode; and
a plurality of second conductive patterns (chosen as one of the GL and DL lines), located in the second active area and electrically connected to the at least one of the data lines located at the junction;
wherein orthographic projections of part of the first conductive patterns on the substrate overlap with orthographic projections of the second conductive patterns on the substrate (located at the junction).
Regarding claim 2, Jeong et al. teach in figure 4 and related text that the plurality of first conductive patterns comprise a first part (arbitrarily chosen); the first conductive patterns of the first part are located in the second active area and are electrically connected to the grid lines; and the orthographic projections of the second conductive patterns on the substrate are located within orthographic projections of the first conductive patterns of the first part on the substrate (chosen as such).
Regarding claim 3, Jeong et al. teach in figure 4 and related text that the plurality of first conductive patterns comprise a second part (arbitrarily chosen); the first conductive patterns of the second part extend from the first active area to the second active area (chosen as such), and are electrically connected to the common electrode; orthographic projections of the first conductive patterns of the second part on the substrate overlap with an orthographic projection of the data line located at the junction on the substrate.
Regarding claim 5, Jeong et al. teach in figure 4 and related text that the second active area comprises a plurality of first dummy capacitances (located in areas DUA since said area comprises dummy pixel electrodes and dummy data lines and dummy parasitic capacitances inherently located therein, see also figure 6 area NDA), the first conductive patterns of the first part are regarded as first electrodes of the first dummy capacitances, and the second conductive patterns are regarded as second electrodes of the first dummy capacitances.
Regarding claim 6, Jeong et al. teach in figure 4 and related text that the second active area comprises a plurality of dummy transistors (located in area DUA), gates of the dummy transistors are electrically connected to the grid lines, first ends of the dummy transistors are electrically connected to the data line located at the junction, and second ends of the dummy transistors are arranged in isolation (the area located between the transistors).
Regarding claim 7, Jeong et al. teach in figure 4 and related text that part regions of the first conductive patterns of the first part are regarded as the gates of the dummy transistors; at least part of the second conductive patterns comprises first conductive parts and second conductive parts (arbitrarily chosen), the first conductive parts are disconnected from the second conductive parts, the first conductive parts are regarded as the first ends of the dummy transistors (located in DUA area), and the second conductive parts are regarded as the second ends of the dummy transistors.
Regarding claim 8, Jeong et al. teach in figure 4 and related text that a quantity of the dummy transistors is less than or equal to half a quantity of rows of the sub-pixels (since figure 4 depicts that the pixels in the DUA area are less than pixels on the PA area).
Regarding claim 9, Jeong et al. teach in figure 4 and related text that each of the grid lines GL divides the data line DA located at the junction into a plurality of data line segments; the first active area comprises a plurality of transistors, part of the data line segments is electrically connected to the transistors, at least part of the data line DDL segments that are not connected to the transistors is electrically connected to the dummy transistors (located in area DUA).
Regarding claim 12, Jeong et al. teach in figure 4 and related text that the display panel comprises a plurality of second dummy capacitances, the first conductive patterns of the second part are regarded as first electrodes of the second dummy capacitances, part line segments of the data line located at the junction are regarded as second electrodes of the second dummy capacitances (see above); wherein an area (arbitrarily chosen) of an orthographic projection of a part of the first conductive patterns of the second part that is located in the second active area on the substrate is greater than an area of an orthographic projection of a part of the first conductive patterns of the second part that is located in the first active area on the substrate.
Regarding claim 18, Jeong et al. teach in figure 4 and related text that a quantity of the second dummy capacitance is greater than or equal to half a quantity of rows of the sub-pixels.
Regarding claim 24, Jeong et al. teach in figure 4 and related text that the display panel further comprises a third conductive pattern (arbitrarily chosen), the third conductive pattern is electrically connected to the common electrode COM, the third conductive pattern is at least located in the second active area, and at least part region of the third conductive pattern is located between the first conductive patterns of the first part and the data line located at the junction (chosen as such); wherein an orthographic projection of the at least part region of the third conductive pattern on the substrate does not overlap with the orthographic projection of the data line located at the junction on the substrate.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (2018/0188616).
Regarding claim 4, Jeong et al. do not teach that outer contours of the orthographic projections of the second conductive patterns on the substrate are located within outer contours of the orthographic projections of the first conductive patterns of the first part on the substrate.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form outer contours of the orthographic projections of the second conductive patterns on the substrate located within outer contours of the orthographic projections of the first conductive patterns of the first part on the substrate, in Jeong et al.’s device in order to simplify the processing steps of making the device.
Regarding claim 10, Jeong et al. teach in figure 4 and related text that the data line segments that are not connected to the transistors are electrically connected to the dummy transistors, and the data line segments electrically connected to the transistors and the data line segments electrically connected to the dummy transistors are arranged at intervals, but do not teach that the quantity of the dummy transistors is equal to half the quantity of rows of the sub-pixels.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the quantity of the dummy transistors equal to half the quantity of rows of the sub-pixels in Jeong et al.’s device in order to adjust the device characteristics according to the requirements of the application in hand.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
2/6/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800