Attorney’s Docket Number: 3105-23SG1P2758-US
Filing Date: 07/13/2023
Claimed Priority Date: 02/24/2021 (CN202110209347.7)
10/22/2021 (371 of PCT/CN2021/125822)
Applicants: Liu et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Amendment filed on 12/15/2025.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The Amendment filed on 12/15/2025, responding to the Office action mailed on 09/15/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this application are claims 1-20.
Response to Amendment
No amendments to the claims were presented in response to the claim rejections under 35 U.S.C. 102 and 35 U.S.C. 103, as previously formulated in the Non-Final Office action mailed on 09/15/2025. Furthermore, Applicant’s arguments have not been found persuasive. Accordingly, all grounds of rejections stand, as detailed in the Office action below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 7-15, 17, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yuan et al. (US2023/0122411).
Regarding Claim 1, Yuan (see, e.g., Figs. 1 and 4-15, and Annotated Fig. 1) shows all aspects of the instant invention, including a display panel (e.g., array substrate), comprising:
- a base substrate (e.g., base substrate 1), a light shielding layer (e.g., light-shielding layer 100) , a buffer layer (e.g., buffer layer 200), an active layer (e.g., active layer 300), a gate insulative layer (e.g., gate insulating layer 400), a gate layer (e.g., gate layer 500), a first interlayer dielectric layer (e.g., interlayer dielectric layer 600), and a first conductive layer (e.g., conductive layer 700) that are sequentially laminated; wherein
- the light shielding layer comprises a first electrode (see, e.g., Figs. 1 and 4: electrode plate 54)
- the active layer comprises a second electrode connected to the first electrode (see, e.g., Figs. 1 and 8: middle portion of 300 overlaps 54 and is connected through connecting part 65)
- the gate layer comprises a third electrode (see, e.g., Figs. 1 and 6: electrode plate 52), wherein an orthogonal projection of the third electrode on the base substrate is at least partially overlapped with an orthogonal projection of the first electrode on the base substrate to form a first storage capacitor (e.g., the projection of 52 and 54 on 1 are overlapped to form a first storage capacitor)
- the first conductive layer comprises a fourth electrode, wherein the fourth electrode is connected to the third electrode (see, e.g., Figs. 1 and 8: electrode plate 51 connected to 52 by via hole), and an orthogonal projection of the fourth electrode on the base substrate is at least partially overlapped with an orthogonal projection of the second electrode on the base substrate to form a second storage capacitor (e.g., the projection of 51 and middle portion of 300 on 1 are overlapped to form a second storage capacitor)
Regarding Claim 2, Yuan (see, e.g., Figs. 1 and 6) shows that the orthogonal projection of the second electrode (e.g., middle portion of 300) on the base substrate is at least partially overlapped with the orthogonal projection of the third electrode (e.g., 52) on the base substrate.
Regarding Claim 4, Yuan (see, e.g., Figs. 1 and 6-8) shows:
- a first transistor (e.g., left transistor/T3)
- wherein the active layer comprises a source region, a drain region, and a channel region of the first transistor, the first conductive layer comprises a source of the first transistor (e.g., connecting part 65), the source of the first transistor is connected to the source region of the first transistor and the first electrode, and the second electrode is connected to the source region of the first transistor
Regarding Claim 7, Yuan (see, e.g., Figs. 1 and 10) shows:
- a second conductive layer (e.g., conductive layer 900) and a second interlayer dielectric layer (e.g., interlayer dielectric layer 800)
- wherein the second interlayer dielectric layer is disposed on a side, distal from the base substrate, of the first interlayer dielectric layer, and the second conductive layer is disposed on a side, distal from the base substrate, of the second interlayer dielectric layer and comprises a fifth electrode (e.g., electrode plate 53), wherein the fifth electrode is connected to the second electrode (e.g., through via 92 and 65), and an orthogonal projection of the fifth electrode on the base substrate is at least partially overlapped with the orthogonal projection of the fourth electrode on the base substrate to form a third storage capacitor (e.g., the projection of 53 and 51 on 1 are overlapped to form a third storage capacitor).
Regarding Claim 8, Yuan (see, e.g., Figs. 1 and 10) shows that the orthogonal projection of the fifth electrode (e.g., 53) on the base substrate covers the orthogonal projection of the first electrode (e.g., 54) on the base substrate.
Regarding Claim 9, Yuan (see, e.g., Figs. 1 and 11) shows:
- a third interlayer dielectric layer (e.g., interlayer dielectric layer 1000), a first planarization layer (e.g., planarizing layer 1100), and a third conductive layer (e.g., conductive layer 1200)
- wherein the third interlayer dielectric layer is disposed on the side, distal from the base substrate, of the second interlayer dielectric layer, the first planarization layer is disposed on side, distal from the base substrate, of the third interlayer dielectric layer, and the third conductive layer is connected to the second conductive layer (e.g., by via holes 93).
Regarding Claim 10, Yuan (see, e.g., Figs. 1 and 15) shows an anode layer (e.g., anode layer 1700) connected to the third conductive layer (e.g., via holes 94).
Regarding Claim 11, Yuan (see, e.g., Figs. 1 and 6-8) shows:
- a second transistor (e.g., right transistor/T2)
- wherein the active layer comprises a source region, a drain region, and a channel region of the second transistor, the first conductive layer comprises a source of the second transistor (e.g., connecting part 61), and the source of the second transistor is connected to the source region of the second transistor and the fourth electrode (e.g., 51).
Regarding Claim 12, Yuan (see, e.g., Figs. 1 and 6-8) shows that the gate layer (e.g., 500) comprises a gate of the second transistor, wherein the gate of the second transistor is opposite to the channel region of the second transistor.
Regarding Claim 13, Yuan (see, e.g., Figs. 1 and 4-15) shows all aspects of the instant invention, including a method for manufacturing a display panel (e.g., array substrate), comprising:
- providing a base substrate (e.g., base substrate 1), and forming a light shielding layer (e.g., light-shielding layer 100) on the base substrate, wherein the light shielding layer comprises a first electrode (see, e.g., Figs. 1 and 4: electrode plate 54)
- forming a buffer layer (e.g., buffer layer 200) on the light shielding layer, and forming an active layer (e.g., active layer 300) on the buffer layer, wherein the active layer comprises a second electrode connected to the first electrode (see, e.g., Figs. 1 and 8: middle portion of 300 overlaps 54 and is connected through connecting part 65)
- forming a gate insulative layer (e.g., gate insulating layer 400) on the active layer, and forming a gate layer (e.g., gate layer 500) on the gate insulative layer, wherein the gate layer comprises a third electrode (see, e.g., Figs. 1 and 6: electrode plate 52), an orthogonal projection of the third electrode on the base substrate being at least partially overlapped with an orthogonal projection of the first electrode on the base substrate to form a first storage capacitor (e.g., the projection of 52 and 54 on 1 are overlapped to form a first storage capacitor)
- forming a first interlayer dielectric layer (e.g., interlayer dielectric layer 600) on the gate layer, and forming a first conductive layer (e.g., conductive layer 700) on the first interlayer dielectric layer, wherein the first conductive layer comprises a fourth electrode, wherein the fourth electrode is connected to the third electrode (see, e.g., Figs. 1 and 8: electrode plate 51 connected to 52 by via hole), and an orthogonal projection of the fourth electrode on the base substrate is at least partially overlapped with an orthogonal projection of the second electrode on the base substrate to form a second storage capacitor (e.g., the projection of 51 and middle portion of 300 on 1 are overlapped to form a second storage capacitor).
Regarding Claim 14, Yuan (see, e.g., Figs. 1 and 4-15) shows all aspects of the instant invention, including a display device (e.g., display device), comprising:
- a display panel (e.g., array substrate), wherein the display panel comprises:
- a base substrate (e.g., base substrate 1), a light shielding layer (e.g., light-shielding layer 100) , a buffer layer (e.g., buffer layer 200), an active layer (e.g., active layer 300), a gate insulative layer (e.g., gate insulating layer 400), a gate layer (e.g., gate layer 500), a first interlayer dielectric layer (e.g., interlayer dielectric layer 600), and a first conductive layer (e.g., conductive layer 700) that are sequentially laminated; wherein
- the light shielding layer comprises a first electrode (see, e.g., Figs. 1 and 4: electrode plate 54)
- the active layer comprises a second electrode connected to the first electrode (see, e.g., Figs. 1 and 8: middle portion of 300 overlaps 54 and is connected through connecting part 65)
- the gate layer comprises a third electrode (see, e.g., Figs. 1 and 6: electrode plate 52), wherein an orthogonal projection of the third electrode on the base substrate is at least partially overlapped with an orthogonal projection of the first electrode on the base substrate to form a first storage capacitor (e.g., the projection of 52 and 54 on 1 are overlapped to form a first storage capacitor)
- the first conductive layer comprises a fourth electrode, wherein the fourth electrode is connected to the third electrode (see, e.g., Figs. 1 and 8: electrode plate 51 connected to 52 by via hole), and an orthogonal projection of the fourth electrode on the base substrate is at least partially overlapped with an orthogonal projection of the second electrode on the base substrate to form a second storage capacitor (e.g., the projection of 51 and middle portion of 300 on 1 are overlapped to form a second storage capacitor)
Regarding Claim 15, Yuan (see, e.g., Figs. 1 and 6) shows that the orthogonal projection of the second electrode (e.g., middle portion of 300) on the base substrate is at least partially overlapped with the orthogonal projection of the third electrode (e.g., 52) on the base substrate.
Regarding Claim 17, Yuan (see, e.g., Figs. 1 and 6-8) shows:
- a first transistor (e.g., left transistor/T3)
- wherein the active layer comprises a source region, a drain region, and a channel region of the first transistor, the first conductive layer comprises a source of the first transistor (e.g., connecting part 65), the source of the first transistor is connected to the source region of the first transistor and the first electrode, and the second electrode is connected to the source region of the first transistor
Regarding Claim 20, Yuan (see, e.g., Figs. 1 and 10) shows:
- a second conductive layer (e.g., conductive layer 900) and a second interlayer dielectric layer (e.g., interlayer dielectric layer 800)
- wherein the second interlayer dielectric layer is disposed on a side, distal from the base substrate, of the first interlayer dielectric layer, and the second conductive layer is disposed on a side, distal from the base substrate, of the second interlayer dielectric layer and comprises a fifth electrode (e.g., electrode plate 53), wherein the fifth electrode is connected to the second electrode (e.g., through via 92 and 65), and an orthogonal projection of the fifth electrode on the base substrate is at least partially overlapped with the orthogonal projection of the fourth electrode on the base substrate to form a third storage capacitor (e.g., the projection of 53 and 51 on 1 are overlapped to form a third storage capacitor).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan et al. (US2023/0122411).
Regarding Claims 5 and 18, Yuan (see, e.g., Fig. 1) depicts active layer 300 as having a substantially constant thickness, such that a thickness of the source region of the first transistor (e.g., left transistor/T3) and a thickness of the drain region of the first transistor are similar to a thickness of the second electrode (e.g., middle portion of 300). Therefore, Yuan does not show that the thicknesses of the source and drain regions are different from a thickness of the second electrode.
However, the courts have held that differences in thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed difference in thickness between the source/drain regions and the second electrode, and since Yuan shows all aspects of the instant invention but the difference in thicknesses, it would have been obvious to one of ordinary skill in the art to have the difference in thicknesses as claimed in the device of Yuan, because it is known in the semiconductor manufacturing art that the conformality of a layer across different device regions can only be maintained within defined processes error margins, and that variations in thicknesses within said error margins are to be expected.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed difference in thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1939 (Fed. Cir. 1990).
Allowable Subject Matter
Claims 3, 6, 16, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to the claims filed on 12/15/2025 have been considered but have not been found persuasive:
Applicant argues:
“However, based on the Examiner's opinion regarding the feature "the active layer comprises a second electrode connected to the first electrode" of claim 1, only the portion of the active layer 300 that is connected to the fourth electrode plate 54 (corresponding to the first electrode) via the fifth connecting part 65 corresponds to the "second electrode." Figure 1 of Yuan shows the portion of the active layer 300 that is connected to the fourth electrode plate 54 via the fifth connecting part 65 (the portion marked in red in the figure shown, corresponding to the second electrode) and the first electrode plate 51 (the portion marked in green in the figure shown, corresponding to the fourth electrode) do not overlap in their projections on the base substrate 1, and thus cannot form a storage capacitor.” (see, e.g., Remarks, Page 2)
The examiner responds:
The examiner respectfully disagrees. Applicant has mischaracterized the examiner’s mapping of claim features to the prior art of Yuan et al. (2023/0122411). An additional annotated drawing of Fig. 1 is hereby provided to further assist with the correspondence between claimed features and the disclosure of Yuan (see, attached Annotated Fig.1).
As such, all previously presented grounds of rejection stand as detailed in the office action supra.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul whose telephone number is (571) 270-5514. The examiner can normally be reached Monday-Friday 9am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814