DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's election with traverse of Species II (claims 1-7, 10-12, 14-15, 17, 19, 21, 23, 26-27, 30, and 32) in the reply filed on 11/11/2025 is acknowledged. The traversal is on the ground(s) that Figs. 4 and 5 are in the same embodiment. This is found persuasive and thus the previous Restriction/Election mailed on 09/19/2025 has been withdrawn. Accordingly, claims 1-7, 10-12, 14-15, 17, 19, 21, 23, 26-27, 30, and 32 are pending in this application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 10-11, 14-15, 26-27, 30, and 32 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al. (U.S 2014/0320446 A1).
As to claim 1, KIM et al. disclose in Fig. 5 an array substrate, comprising: a base substrate (“display panel”/“lower substrate” 100) (Fig. 5, para. [0049]-[0055]); a plurality of pixel units (Figs. 4-5, para. [0056]-[0057], [0083], [0086]), located on a side of the base substrate (“display panel”/“lower substrate” 100) (Figs. 4-5, para. [0056]-[0057]); and a common electrode line (“touch electrode” includes “first line” 110, “second line” 120, and “common electrodes” 900), comprising a horizontal common electrode line (comprising “second line” 120 and “common electrodes” 900) and a vertical common electrode line (comprising “first line” 110 and “common electrodes” 900), the horizontal common electrode line (comprising “second line” 120 and “common electrodes” 900) is electrically connected with the vertical common electrode line (comprising “first line” 110 and “common electrodes” 900) (Fig. 5, para. [0078]-[0081], [0083]), wherein the plurality of pixel units (Figs. 4-5, para. [0056]-[0057], [0083], [0086]) are arranged in an array along a first direction (horizontal direction) and a second direction (vertical direction) to form a plurality of pixel rows and a plurality of pixel columns, each of the pixel rows extends along the first direction (horizontal direction), and each of the pixel columns extends along the second direction (vertical direction), the horizontal common electrode line (comprising “second line” 120 and “common electrodes” 900) extends along the first direction (horizontal direction) (Fig. 5), the vertical common electrode line (comprising “first line” 110 and “common electrodes” 900) extends along the second direction (vertical direction), each of the plurality of pixel units (Figs. 4-5, para. [0056]-[0057], [0083], [0086]) comprises an effective display region (“display panel” 100 include “single display interval”, Fig. 5, para. [0096]-[0101]), the horizontal common electrode line (comprising “second line” 120 and “common electrodes” 900) is overlapped with a plurality of effective display regions (“display panel” 100 include “single display interval”, Fig. 5, para. [0096]-[0101]) of a same pixel row (Fig. 5).
As to claim 2, as applied to claim 1 above, KIM et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein the effective display region (“display panel” 100 include “single display interval”, Fig. 5, para. [0096]-[0101]) comprises a first domain and a second domain arranged in the second direction (vertical direction), and the horizontal common electrode line (comprising “second line” 120 and “common electrodes” 900) is located between the first domain and the second domain (Fig. 5).
As to claim 3, as applied to claim 1 above, KIM et al. disclose in Fig. 5 all claimed limitations including the array substrate further comprising: a plurality of gate lines (GL1, GLn), arranged along the second direction (vertical direction) (Figs. 4-5, para. [0056], [0062], [0072], [0089]-[0091]); and a plurality of data lines (DL1-DLm) (Figs. 4-5, para. [0056], [0063], [0074]-[0076]), arranged along the first direction (horizontal direction), wherein each of the gate lines (GL1, GLn) extends along the first direction (horizontal direction), each of the data lines (DL1-DLm) extends along the second direction (vertical direction), the plurality of gate lines (GL1, GLn) and the plurality of data lines (DL1-DLm) are arranged in different layers, and the horizontal common electrode line (comprising “second line” 120 and “common electrodes” 900) is arranged on a same layer as the gate lines (GL1, GLn) (Figs. 4-5, para. [0056], [0062], [0072]-[0073], [0086], [0089]-[0095]).
As to claim 4, as applied to claims 1 and 3 above, KIM et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein the vertical common electrode line (comprising “first line” 110 and “common electrodes” 900) comprises a vertical conductive part (110), the vertical conductive part (100) is arranged on a same layer as the gate lines (GL1, GLn) (Figs. 4-5), the vertical conductive part (110) is located between two pixel units adjacent in the first direction (horizontal direction) (Fig. 5), the vertical conductive part (110) is located between two gate lines of the gate lines (GL1, GLn), is intersected with the horizontal common electrode line (comprising “second line” 120 and “common electrodes” 900), and form an integrated cross-shaped conductive structure at an intersection position (Figs. 4-5).
As to claim 5, as applied to claims 1, 3, and 4 above, KIM et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein the vertical conductive part (110) is located between two data lines (DL1-DLm) adjacent in the first direction (horizontal direction) (Figs. 4-5), and an orthographic projection of the vertical conductive part (110) on the base substrate (“display panel”/“lower substrate” 100) and orthographic projections of the data lines (DL1-DLm) on the base substrate (“display panel”/“lower substrate” 100) are spaced apart (Figs. 4-5).
As to claim 6, as applied to claims 1, 3, and 4 above, KIM et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein the vertical common electrode line (comprising “first line” 110 and “common electrodes” 900) comprises a vertical connection part (110), the vertical connection part (110) and the gate lines (GL1, GLn) are arranged in different layers, and the vertical connection part (110) connects two vertical conductive parts (110, 110) adjacent in the second direction (vertical direction) (Figs. 4-5).
As to claim 7, as applied to claims 1, 3, 4 and 6 above, KIM et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein two ends of the vertical connection part (110) are respectively connected with the two vertical conductive parts (110, 110) adjacent in the second direction (vertical direction) through a via hole connection structure, the plurality of pixel units comprise a first color pixel unit (“red color filter”), a second color pixel unit (“green color filter”) and a third color pixel unit (“blue color filter”) (see para. [0054]-[0056]), and an orthographic projection of the via hole connection structure on the base substrate (100) is at least partially overlapped with an orthographic projection of an effective display region of the third color pixel unit (“blue color filter”) on the base substrate (100) (Figs. 4-5, para. [0054]-[0056]).
As to claim 10, as applied to claims 1, 3, 4 and 6 above, KIM et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein each of the pixel units further comprises: a pixel electrode (para. [0057]), located on a side of a film layer where the data lines (DL1-DLm) are located away from the base substrate (100) (para. [0047], [0056]-[0057]); and a common electrode (900), located on a side of the pixel electrode away from the base substrate (100) (para. [0061], [0076], [0083], [0086], [0089]), wherein the vertical connection part (110) is arranged on a same layer as the common electrode (900) (Figs. 4-5).
As to claim 11, as applied to claims 1, 3, 4, 6 and 10 above, KIM et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein at least one of the pixel units (Figs. 4-5, para. [0056]-[0057], [0083], [0086]) further comprises: a driving transistor (para. [0098]), comprising a gate electrode (para. [0056]), a source electrode and a drain electrode (para. [0056]), wherein the gate electrode (para. [0056]) is connected with one of the gate lines (GL1, GLn), the pixel electrode (para. [0057]) is connected with the drain electrode (para. [0056]), the common electrode (900) is connected with the common electrode line, the drain electrode (para. [0056]) comprises a drain body part and a drain extension part, the drain extension part extends from the drain body part to the vertical connection part, the pixel electrode (para. [0057]) comprises a pixel electrode extension part, and the pixel electrode extension part is connected with the drain electrode extension part by overlapping (Figs. 4-5).
As to claim 14, as applied to claims 1 and 3 above, KIM et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein each of the gate lines (GL1, GLn) comprises a spacer support part (gate lines of the transistors inherently comprising spacer support parts or spacers), and a region where the spacer support part is located is configured to place a spacer, an orthographic projection of the spacer support part on the base substrate (100) is located between an orthographic projection of an extension line of the vertical conductive part (110) on the base substrate (100) and an orthographic projection of a data line (DL1-DLm) closest to the vertical conductive part (110) on the base substrate (100) (Figs. 4-5).
As to claim 15, as applied to claims 1 and 3 above, KIM et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein each of the gate lines (GL1, GLn) comprises a spacer support part (gate lines of the transistors inherently comprising spacer support parts or spacers), and a region where the spacer support part is located is configured to place a spacer, an orthographic projection of the spacer support part on the base substrate (100) is at least partially overlapped with an orthographic projection of an extension line of the vertical conductive part (110) on the base substrate (100) (Figs. 4-5).
As to claim 26, as applied to claim 1 above, KIM et al. disclose in Fig. 5 all claimed limitations including a display panel (100), comprising the array substrate (Figs. 4-5, para. [0053]-[0055]).
As to claim 27, as applied to claims 1 and 26 above, KIM et al. disclose in Fig. 5 all claimed limitations including a display panel (Figs. 4-5) further comprising: an opposite substrate (“upper substrate”, para. [0054]), arranged opposite to the array substrate (“lower substrate”, para. [0055]); a main spacer, located between the array substrate (“lower substrate”, para. [0055]) and the opposite substrate (“upper substrate”, para. [0054]); and an auxiliary spacer, located between the array substrate (“lower substrate”, para. [0055]) and the opposite substrate (“upper substrate”, para. [0054]) (Figs. 4-5, para. [0054]-[0055]).
As to claim 30, as applied to claims 1, 26 and 27 above, KIM et al. disclose in Fig. 5 all claimed limitations including the display panel (Figs. 4-5), wherein the main spacer is arranged in contact with both the array substrate (“lower substrate”, para. [0055]) and the opposite substrate (“upper substrate”, para. [0054]), and the auxiliary spacer is arranged in contact with at least one of the array substrate (“lower substrate”, para. [0055]) and the opposite substrate (“upper substrate”, para. [0054]) (Figs. 4-5).
As to claim 32, as applied to claims 1 and 26 above, KIM et al. disclose in Fig. 5 all claimed limitations including a display device (Figs. 4-5) comprising the display panel (100) (Figs. 4-5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (U.S 2014/0320446 A1).
As to claim 12, as applied to claims 1, 3, 4, 6, 10 and 11 above, KIM et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein an orthographic projection of the drain extension part on the base substrate (100) and an orthographic projection of the vertical connection part (110) on the base substrate (100) are spaced apart (Figs. 4-5).
KIM et al. do not disclose a distance between the orthographic projection of the drain extension part on the base substrate and the orthographic projection of the vertical connection part on the base substrate is in the range of 0 microns to 3 microns. However, it would have been obvious to one of ordinary skill in the art to use the teaching of KIM et al. in the range (0 microns to 3 microns for a distance between the orthographic projection of the drain extension part on the base substrate and the orthographic projection of the vertical connection part on the base substrate) in order to improve the structure or the performance as claimed, because it has been held that where the general conditions of the claims are disclosed in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955); Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. Denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); MPEP 2144.05. There is no evidence indicating the range of a distance between the orthographic projection of the drain extension part on the base substrate and the orthographic projection of the vertical connection part on the base substrate is critical. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Allowable Subject Matter
Claims 17, 19, 21, and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 March 7, 2026