The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-10 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yonekura et al. (9,310,652) in view of Lei et al. (8,653,526).
Regarding claims 1 and 22, Yonekura et al. teach in figures 1, 2A and related text a display device, comprising:
a power supply assembly VS and an array substrate AR coupled to the array substrate and is configured to supply power to the array substrate; and the array substrate comprises:
a substrate, comprising a display region (the location of the display), a wiring region (the location of the wiring), and a circuit region (the location of the circuits), wherein the wiring region and the circuit region are disposed on at least one side of the display region and successively arranged along a direction away from the display region, and wherein the wiring region (located in the middle of figure 2A) is adjacent to and in contact with the display region LPN (see figure 3), and the wiring region is adjacent to and in contact with the circuit region (for example, the region of G1);
a plurality of pixels PX, disposed in the display region;
a common electrode line CAC, extending along a first direction and disposed completely in the wiring region, wherein the common electrode line CAC comprises a plurality of cutouts spaced apart and is coupled to the plurality of pixels PX, PE;
a plurality of gate lines GI, extending along a second direction and disposed in the display region and the wiring region, wherein the first direction is intersected with the second direction;
a plurality of gate leads (the gate electrodes depicted in figure 1), extending along the second direction and disposed in the circuit region and the wiring region, wherein the plurality of gate leads are disposed on a side, distal from the substrate, of the gate line and a side, proximal to the substrate, of the common electrode line; and
a gate drive circuit GD, disposed in the circuit region and coupled to the plurality of gate leads, wherein the plurality of gate leads are connected to the plurality of gate lines by a connection portion, and the plurality of gate lines are coupled to the plurality of pixels.
Yonekura et al. do not explicitly state that the plurality of gate leads are connected to the plurality of gate lines by a connection portion disposed within the cutout.
Yonekura et al. teach in figure 2A and related text that a connection portion PB, functioning as a pixel, disposed within the cutout.
Lei et al. teach in figure 6 and related text that a plurality of gate leads (the horizontal part of element 432) are connected to a plurality of gate lines 300 by a connection portion (the vertical part of element 432 which is a pixel electrode).
Yonekura et al. and Lei et al. are analogous art because they are directed to display semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lei et al. because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to connect the plurality of gate leads to the plurality of gate lines by a connection portion disposed within the cutout, as taught by Lei et al., in prior art’s device, in order to simplify the processing steps of making the device by forming all three elements in one processing step.
Regarding claim 2, Yonekura et al. teach in figures 1, 2A and related text that an edge of each of the cutouts is spaced from an edge of the common electrode line CAC, and the edges of the cutouts are equally spaced from any edge, in the second direction, of the common electrode line CAC; and the plurality of cutouts are spaced apart along the first direction.
Regarding claim 3, Yonekura et al. teach in figures 1, 2A and related text that the plurality of pixels PX are arranged in arrays; the plurality of gate leads are connected to the plurality of gate lines GI in one-to-one correspondence by connection portions disposed within the plurality of cutouts in one-to-one correspondence, and the plurality of gate lines GI are coupled to a plurality of rows of the pixels PX in one-to-one correspondence.
Yonekura et al. do not explicitly state that the gate drive circuit GD comprises a plurality of shift register units that are successively arranged and cascaded along the first direction, and wherein the plurality of shift register units are coupled to the plurality of gate leads in one-to-one correspondence.
It is well-known in the art that a gate drive circuit comprises a plurality of shift register. Yonekura et al. teach in figure 1 and related text that plurality of units are coupled to the plurality of gate leads in one-to-one correspondence.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the gate drive circuit GD comprises a plurality of shift register units that are successively arranged and cascaded along the first direction, and wherein the plurality of shift register units are coupled to the plurality of gate leads in one-to-one correspondence in prior art’s device, in order to be able to operate the device in its intended use.
Regarding claim 4, in the combined device, each of the gate leads, each of the cutouts, and each of the gate lines GL, which are in one- to-one correspondence, are successively arranged in the second direction along a same horizontal line.
Regarding claim 5, Lei et al., and thus prior art, teach in figure 6 and related text that an a first insulator layer 214 disposed between the gate line 212/300 and the gate lead 216; a second insulator layer (another part of 214) disposed on a side, distal from the substrate, of the gate lead; a first connection portion (the middle of element 212) disposed on a side, distal from the substrate, of the second insulator layer; and a plurality of first vias (under 236) running through the second insulator layer, and a plurality of second vias (under 238) running through the second insulator layer and the first insulator layer 214; wherein an orthographic projection of the gate lead 216 on the substrate is within an orthographic projection of the gate line 212/300 on the substrate, and orthographic projections of the plurality of first vias on the substrate are not overlapped with orthographic projections of the plurality of second vias on the substrate; and the first connection portion is lapped (electrically connected ) to the gate lead through the plurality of first vias and lapped to the gate line through the plurality of second vias such that the gate line is connected to the gate lead (see figure 6).
Regarding claim 6, Lei et al., and thus prior art, teach in figure 5 and related text that there is at least one of: a number of the plurality of first vias is equal to a number of the plurality of second vias; or a number of the plurality of first vias and a number of the plurality of second vias are both greater than or equal to four and less than or equal to eight.
Regarding claim 8, Lei et al., and thus prior art, teach in figures 1 and 5 and related text that the plurality of first vias are organized into a plurality of first via groups successively arranged along the first direction (see figure 1 depicting the symmetrical arrangement of the pixel units 400 along the gate line 300, and wherein each of which comprises first and second vias), wherein each of the first via groups comprises a plurality of the first vias successively arranged along the second direction, and a number of the first vias in each of the first via groups is less than or equal to a number of the plurality of first via groups; and the plurality of second vias are organized into a plurality of second via groups successively arranged along the first direction, wherein each of the second via groups comprises a plurality of the second vias successively arranged along the second direction, and a number of the second vias in each of the second via groups is less than or equal to a number of the plurality of second via groups.
Regarding claim 9, Lei et al., and thus prior art, teach in figures 1 and 5 and related text that the plurality of first vias are organized into two of the first via groups successively arranged along the first direction, and each of the first via groups comprises two of the first vias (chosen as such) successively arranged along the second direction; and the plurality of second vias are organized into two of the second via groups successively arranged along the first direction, and each of the second via groups comprises two of the second vias successively arranged along the second direction.
Prior art does not teach that the number of the plurality of first vias and the number of the plurality of second vias are both four.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the number of the plurality of first vias and the number of the plurality of second vias are both four in prior art’s device, in order to reduce the size of the device according to the requirements of the application in hand.
Regarding claim 10, in the combined device, the first connection portion and the common electrode line are disposed in a same layer.
Response to Arguments
1. Applicants argue that Yonekura does not teach that “the wiring region is adjacent to and in contact with the display region, and the wiring region is adjacent to and in contact with the circuit region, and the common electrode line is completely disposed in the wiring region. As such, according to amended claim 1 of the present application, the common electrode line is disposed outside the display region and is not in the display region. Accordingly, the plurality of cutouts spaced apart in the common electrode line are also not in the display region”.
Applicants further argue that “the main common electrode CAC in Yonekura is disposed within the display region”.
1. The claims require that the common electrode line is completely disposed in the wiring region. Figure 2A of Yonekura depicts that the common electrode line CAC is completely disposed in the wiring region (located in the middle of figure 2A).
Furthermore, Figures 2A of Yonekura depict that the wiring region (in the middle of figure 2A) is adjacent to and in contact with the display region LPN (see figure 3), and the wiring region is adjacent to and in contact with the circuit region G1 (for example), as required by the claims.
2. Applicants argue that “the pixel gate 432 in Lei is connected to the gate line 300 via a connecting portion within the display region. However, Lei still fails to disclose, teach, or suggest the connection between the gate lead and the gate line in the wiring region outside the display region, still fails to disclose, teach, or suggest a common electrode line disposed outside the display region and within the wiring region, and still fails to disclose, teach, or suggest cutouts disposed outside the display region and within the wiring region”.
2. Lei was not cited to teach an artisan that “the connection between the gate lead and the gate line in the wiring region outside the display region, still fails to disclose, teach, or suggest a common electrode line disposed outside the display region and within the wiring region, and still fails to disclose, teach, or suggest cutouts disposed outside the display region and within the wiring region”, as argue by applicants.
Lei was cited to teach an artisan that a plurality of gate leads (the horizontal part of element 432) are connected to a plurality of gate lines 300 by a connection portion (the vertical part of element 432 which is a pixel electrode).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
O.N. /ORI NADAV/
6/6/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
Prosecution Insights