DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 14, 21 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over BYUN YOUNG TAE et al. (KR 20100025836 A, hereinafter Byun‘836).
Regarding independent claim 14, Byun‘836 teaches, “An array substrate (fig. 1-6, related description in the specification), comprising:
a substrate (4a, fig. 6) comprising a first surface (top);
an insulating layer (4b, SiO2) on the first surface of the substrate (4a);
a trench layer (4c) on a surface of the insulating layer (4b) away from the substrate, and comprising a guide trench (11, ‘groove’) ((having a width ranging from 50 nm to 250 nm)); and
a nanowire layer (12, ‘nanowire’, ABSTRACT) on the surface of the insulating layer (4b) away from the substrate (4a) and comprising a nanowire (12) therein, wherein the nanowire (12) is in the guide trench (11)”.
Regarding the limitataion, “a guide trench having a width ranging from 50 nm to 250 nm’, Byun‘836 teaches a V-shape trench 11 in fig. 1-6. The width of the trench (11) is varying from bottom to top of the trench. Referring to fig. 6, only one nanowire (12) is placed in the bottom portion of the trench (11). Thus, the width of the bottom part of the trench is approximately the diameter of a nanowire which is approximately 10-100 nm. Referring to the fig. 1 (b), the width of the top part of the trench (11, Lo) which is ~3 µm (referring to the description in page 3-4, Lo ~1.414 tSi , where tSi is the depth of the trench which is ~ 2 µm). Thus, the width of the trench ranges 10 nm -3 µm.
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While Byun‘836 does not explicitly disclose the particular claimed range, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed range during routine experimentation and optimization.
The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Regarding claim 21, Byun‘836 further teaches, “The array substrate of claim 14, further comprising: a first electrode layer (source electrode 5) on a surface of the nanowire layer (12) away from the substrate (4a), wherein the first electrode layer (5) comprises a first electrode (5) electrically coupled to a source region of the nanowires (12), and a second electrode (drain electrode 6) electrically coupled to a drain region of the nanowires (12)”.
Regarding claim 26, Byun‘836 further teaches, “An electronic device, comprising the array substrate of claim 14 (‘electronic device’, page 4)”.
Claims 15-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Byun‘836 as applied to claim 14 as above, and further in view of Ogura et al. (US 20050151061 A1, hereinafter Ogura‘061).
Regarding claim 15, Byun‘836 teaches all the limitations described in claim 14.
Byun‘836 further teaches, wherein the trench layer (11, fig. 6) comprises an activation region (channel region between source and drain) and a growth region (source/drain region), the trench layer has a plurality of guide trenches (11) comprising guide trenches in the activation region and guide trenches in the growth region.
But Byun‘836 is silent upon the provision of wherein a pitch of the guide trenches in the activation region is larger than a pitch of the guide trenches in the growth region, and the guide trenches in the activation region are connected to corresponding ones in the growth region through transition trenches.
However, Ogura‘061 teaches a similar nanowire FET (fig. 5-7), wherein a pitch of the guide trenches (20) in the activation region (channel region) is larger than a pitch of the guide trenches (22) in the growth region (16, 17), and the guide trenches in the activation region are connected to corresponding ones in the growth region through transition trenches.
Byun‘836 and Ogura‘061 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Byun‘836 with the features of Ogura‘061 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Byun‘836 and Ogura‘061 to form the trenches according to the teachings of Ogura‘061 with a motivation of raising the lifetime of the hole carriers in the activation region as described by Ogura‘061 in ¶ [0069] - ¶ [0070].
Regarding claim 16, “The array substrate of claim 15, wherein the pitch of the guide trenches in the activation region ranges from 0.2 µm to 2 µm; and the pitch of the guide trenches in the growth region ranges from 50 nm to 500 nm”, While the cited prior art Byun‘836 modified with Ogura‘061 does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization. The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Regarding claim 17, Byun‘836 modified with Ogura‘061 further teaches, “The array substrate of claim 15, wherein the activation region (fig. 7 with fig. 5) comprises a first activation region and a second activation region, the growth region comprises a first growth region and a second growth region, the guide trenches in the first growth region are communicated with the guide trenches in the first activation region, and the guide trenches in the second growth region are communicated with the guide trenches in the second activation region”.
Regarding claim 19, Byun‘836 modified with Ogura‘061 further teaches, “The array substrate of claim 17, wherein the nanowire layer (12, fig. 6, Byun‘836) comprises a plurality of nanowire groups, each nanowire group comprises a plurality of nanowires spaced apart from each other;”.
Regarding, “a pitch of the nanowires of the nanowire groups corresponding to the activation region ranges from 0.2 µm to 2 µm, and a pitch of the nanowires of the nanowire groups corresponding to the growth region ranges from 50 nm to 500 nm”, Byun‘836 modified with Ogura‘061 does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization. The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Regarding claim 20, “The array substrate of claim 19, wherein the nanowires of the nanowire groups corresponding to the first activation region and the first growth region each have a line width ranging from 60 nm to 80 nm, and the nanowires of the nanowire groups corresponding to the second activation region and the second growth region each have a line width ranging from 20 nm to 30 nm”, While the cited prior art Byun‘836 modified with Ogura‘061 does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization. The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Claims 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Byun‘836 as applied to claim 21 as above, and further in view of YOON et al. (US 20180335666 A1, hereinafter Yoon‘666).
Regarding claim 22, Byun‘836 teaches all the limitations described in claim 21.
But Byun‘836 is silent upon the provision of wherein the array substrate of claim 21, further comprising: a transition layer on a surface of the nanowire layer away from the substrate, wherein the transition layer comprises a first transition electrode between the first electrode and the source electrode region of the nanowires, and a second transition electrode between the second electrode and the drain electrode region of the nanowires.
However, Yoon‘666 a similar TFT (fig. 3-4), wherein
a transition layer (158b) on a surface of the nanowire layer (158a, active/channel layer, Byun‘836 teaches nanowire) away from the substrate (110),
wherein the transition layer (158b) comprises a first transition electrode (158b) between the first electrode (161) and the source electrode region of the nanowires (158a), and a second transition electrode (158b) between the second electrode (163) and the drain electrode region of the nanowires (158a).
Byun‘836 and Yoon‘666 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Byun‘836 with the features of Yoon‘666 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Byun‘836 and Yoon‘666 to include a a-Si layer as transition layer between the S/D region and the S/D electrode according to the teachings of Yoon‘666 as this transition layer works as an ohmic contact layer. See Yoon‘666, ¶ [0033].
Regarding claim 23, Byun‘836 modified with Yoon‘666 further teaches, “The array substrate of claim 22, further comprising: a third electrode (153, fig. 3, Yoon‘666) between the substrate (110) and the insulating layer (155)”.
Regarding claim 24, Byun‘836 modified with Yoon‘666 further teaches, “The array substrate of claim 23, further comprising a passivation layer (165) covering exposed surfaces of the trench layer (155), the nanowire layer (158a), and the first electrode layer (161)”.
Claim 25 are rejected under 35 U.S.C. 103 as being unpatentable over Byun‘836 as applied to claim 14 as above, and further in view of Chae et al. (US 20060226424 A1, hereinafter Chae‘424).
Regarding claim 25, Byun‘836 teaches all the limitations described in claim 14.
But Byun‘836 is silent upon the provision of wherein the array substrate of claim 14, further comprising a passivation layer and a third electrode, wherein the passivation layer covers the insulating layer and exposed surfaces of the nanowires; and the third electrode is on a surface of the passivation layer away from the substrate.
However, Chae‘424 a similar TFT (fig. 7F) comprising a passivation layer (214) and a third electrode (208), wherein the passivation layer (214) covers the insulating layer (SOI layer of Byun‘836) and exposed surfaces of the nanowires (202); and the third electrode (208) is on a surface of the passivation layer (214) away from the substrate (200).
Byun‘836 and Chae‘424 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Byun‘836 with the features of Chae‘424 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Byun‘836 and Chae‘424 to include a top gate TFT according to the teachings of Yoon‘666 with a motivation of exploiting the advantages of the top gate TFT e.g., reduced parasitic capacitance, lower RC delay, lower threshold voltage etc.
Allowable Subject Matter
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claim 18, the prior arts do not anticipate or make obvious, inter alia, the feature of: a width of each guide trench in the first activation region is greater than a width of each guide trench in the second activation region, a width of each guide trench in the first growth region is the same as a width of each guide trench in the first activation region, and a width of each guide trench in the second growth region is the same as the width of each guide trench in the second activation region.
Election/Restrictions
Applicant’s election with traverse of Invention I (semiconductor device), reflected in claims 14-26 in the reply filed on 11/23/2025 is acknowledged. Claims 1-3, 7-8 and 10-11 are withdrawn from further consideration pursuant to 37 CFR 1.142 (b), as being drawn to the nonelected group.
Applicant's traversal is on the ground(s) that the common technical feature between the product and process is not taught by any prior art as cited art CN 113206015 A is not a prior art. Applicant is referred to see the rejection of claims 14-26 above using prior art Byun‘836 which teaches the common technical feature very well.
The requirement is still deemed proper and is therefore made FINAL.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817