Attorney’s Docket Number: 700.680
Filing Date: 07/26/2023
Claimed Priority Date: 05/20/2022 (371 of PCT/CN2022/094188)
Applicants: Wu et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 11/17/2025.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group Invention I, drawn to a method of making a semiconductor structure, in the reply filed on 11/17/2025, is acknowledged. The traversal is on the grounds that the reference to Wu et al. (CN 113394299A) cannot be used as prior art against the application under AIA 35 U.S.C 102(a)(1) because it falls under the AIA 35 U.S.C. 102(b)(1)(A) exception, and that there is no serious burden to examine the claims of all the Groups I and II. Additionally, the Declaration from inventor Hao Wu filed on 11/17/2025 is also acknowledged.
Accordingly, and in the interest of compact prosecution, the restriction requirement between Group Inventions I and II as set forth in the Office action mailed on 09/16/2025 has been reconsidered and is hereby withdrawn. As such, pending in this application are claims 1-4, 10-16, and 18-26.
In view of the withdrawal of the restriction requirement, applicant(s) are advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Once the restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference characters not mentioned in the description: reference character 80, as illustrated in Figs. 1(b)-(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because:
- reference characters “72” and “8” have both been used to designate a same patterned catalytic layer of Indium Tin Oxide (see, e.g., Fig. 13 vs. Fig. 14 and Par. [0184]). Fig. 14 should be amendment to identify the layer above 7’ as patterned catalytic layer 72 instead.
- reference characters “41/51” and “42/52” have both been used to designate the respective source and drain transition layers 51/52 and electrode layers 41/42 (see, e.g., Fig. 21 vs. Fig. 22 and Par. [0190]-[0191]). Fig. 21 should be amendment to reverse the numbering of 41/51 and 42/52, respectively, in accordance with the sequential stacking depicted in Fig. 22 instead (i.e., electrode layers 41/42 above corresponding transition layers 51/52).
- reference characters “9” and “6” have both been used to designate a same passivation layer (see, e.g., Figs. 5-6, 24 vs. Fig. 23 and Par. [0174],[0193]). Fig. 23 should be amendment to identify the top layer above contact layer 41/42 as passivation layer 6 instead.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
- Par. [0067], L. 1 and Par. [0110], L.1: consider amending to -- The insulating layer may be made of a material comprising silicon such as silicon nitride and silicon oxide,…--, for clarity, as silicides are typically known in the semiconductor art as conductive binary compounds of silicon, rather than dielectrics as suggested by the recited exemplary materials.
- Par. [0159], L. 3: amend to -- an insulating layer 2, a nanowire 3,…--.
- Par. [0161], L. 1-2: consider amending to -- A material of the insulating layer 2 may be a material comprising silicon such as silicon nitride and silicon oxide,…--, for clarity, as discussed above.
- Par. [0166], L. 3-4: amend to -- for preparing the nanowire 3,…--.
- Par. [0176], L. 2-3: amend to -- the following description is made with reference to Fig. 7 to Fig. 24 by taking the thin film transistor of the bottom gate structure as an example.--, as illustrated by the formation of bottom gate 43 in Figs. 7-8 and 24.
- Par. [0183], L. 1-3: amend to -- At step S704, preparing a catalytic layer 72 on a surface of the sacrificial layer 7 away from the substrate 1 and in the guide trench 71, and patterning the catalytic layer 72, as shown in Figs. 13 and 14. --, in accordance with details illustrated in Fig. 13 and associated description in Par. [0184].
- Par. [0193], L. 1-2: amend to -- silicon oxide is deposited by a physical vapor deposition process as the passivation layer 6, and the passivation layer 6 covers the exposed surfaces of…--, for consistency with prior description of the same feature in, e.g., Fig. 6 and Par. [0174]: “the thin film transistor further includes a passivation layer 6 and a third electrode 43, and the passivation layer 6 covers exposed surfaces of the insulating layer 2 and the nanowire 3.
Appropriate corrections are required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 11, 18, and 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu et al. (CN 114582974 A and associated Machine Translation).
Regarding Claim 1, Yu (see, e.g., Figs. 5A-9A, 11A-B, and 17-18) shows all aspects of the instant invention including a method for manufacturing a nanowire (e.g., nanowire 20), comprising:
- preparing an insulating layer (e.g., dielectric layer 120) on a first surface of a substrate (e.g., substrate body 110) (see, e.g., Fig. 5B)
- preparing a sacrificial layer (e.g., photoresist 200) on a surface of the insulating layer away from the substrate, and patterning the sacrificial layer to form a guide trench (e.g., groove 101 has a guide function) (see, e.g., Figs. 5C-D)
- preparing an inducing particle (e.g., catalytic metal particle 30) in the guide trench (see, e.g., Figs. 6B-C)
- preparing a precipitation layer (e.g., precursor layer 40 of amorphous silicon) on a surface of the sacrificial layer away from the substrate and in the guide trench, the precipitation layer covering the inducing particle (see, e.g., Fig. 8)
- processing the precipitation layer (e.g., temperature treatment by laser irradiation) to precipitate a preset element in the precipitation layer along the guide trench under an induction of the inducing particle to form a nanowire (see, e.g., Fig. 9A: catalytic metal particle 30 absorbs the material of the amorphous precursor 40, and grows nanowire 20 along a moving direction guided by trench 101).
- removing the sacrificial layer (see, e.g., Fig. 5D: the remaining photoresist 200 is remove as to finish preparation of 101).
Regarding Claim 11, Yu (see, e.g., Figs. 17-18) shows a method for manufacturing a thin film transistor comprising an active layer (e.g., nanowire-based transistor 10), comprising: the method of claim 1, wherein the active layer comprises a nanowire.
Regarding Claim 18, Yu (see, e.g., Figs. 17-18) shows all aspects of the instant invention including a thin film transistor (e.g., nanowire-based transistor 10), comprising:
- a substrate (e.g., substrate body 110) comprising a first surface
- an insulating layer (e.g., dielectric layer 120) arranged on the first surface of the substrate
- a nanowire (e.g., nanowire 20) arranged on a surface of the insulating layer away from the substrate
- an electrode layer (e.g., layer comprising electrodes 53,54) superposed on the surface of the insulating layer away from the substrate, wherein a first electrode (e.g., source electrode 53) arranged in the electrode layer is electrically connected with a source region of the nanowire, and a second electrode (e.g., drain electrode 53) arranged in the electrode layer is electrically connected with a drain region of the nanowire
Regarding Claim 25, Yu (see, e.g., Figs. 17-18) shows:
- a passivation layer (e.g., dielectric layer 50) and a third electrode (e.g., gate 52), wherein the passivation layer covers exposed surfaces of the insulating layer and the nanowire
- the third electrode is arranged on a surface of the passivation layer away from the substrate.
Claims 18, 23-24, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xu (US2020/0150502).
Regarding Claim 18, Xu (see, e.g., Figs. 1-2 and Par. [0033]) shows all aspects of the instant invention including a thin film transistor (e.g., TFT 20), comprising:
- a substrate (e.g., substrate 1) comprising a first surface
- an insulating layer (e.g., dielectric layer 3) arranged on the first surface of the substrate
- a nanowire (e.g., silicon-based nanoline 4) arranged on a surface of the insulating layer away from the substrate
- an electrode layer (e.g., layer comprising electrodes 52,53) superposed on the surface of the insulating layer away from the substrate, wherein a first electrode (e.g., source electrode 52) arranged in the electrode layer is electrically connected with a source region of the nanowire, and a second electrode (e.g., drain electrode 53) arranged in the electrode layer is electrically connected with a drain region of the nanowire
Regarding Claim 23, Xu (see, e.g., Fig. 2) shows a third electrode (e.g., gate electrode 22) disposed between the substrate and the insulating layer.
Regarding Claim 24, Xu (see, e.g., Fig. 2) shows a passivation layer (e.g., passivation layer 6) covering exposed surfaces of the insulating layer, the electrode layer, and the nanowire.
Regarding Claim 26, Xu (see, e.g., Fig. 2 and Par. [0033]) shows a semiconductor device (e.g., TFT array substrate), comprising: the thin film transistor of claim 18.
Claims 18, 21-24, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (CN 113206015 A and associated Machine Translation).
Regarding Claim 18, Wu (see, e.g., Fig. 17) shows all aspects of the instant invention including a thin film transistor (e.g., bottom gate type TFT), comprising:
- a substrate (e.g., substrate 100) comprising a first surface
- an insulating layer (e.g., insulating layer pattern 102) arranged on the first surface of the substrate
- a nanowire (e.g., silicon nano-wire 104') arranged on a surface of the insulating layer away from the substrate
- an electrode layer (e.g., layer comprising electrodes 1061,1062) superposed on the surface of the insulating layer away from the substrate, wherein a first electrode (e.g., source electrode 1061) arranged in the electrode layer is electrically connected with a source region of the nanowire, and a second electrode (e.g., drain electrode 1062) arranged in the electrode layer is electrically connected with a drain region of the nanowire.
Regarding Claim 21, Wu (see, e.g., Fig. 17) shows a first transition electrode (e.g., first pattern 1051) is disposed between the first electrode and the source region of the nanowire, and a second transition electrode (e.g., second pattern 1052) is disposed between the second electrode and the drain region of the nanowire.
Regarding Claim 22, Wu (see, e.g., Figs. 9 and 17) show that the first transition electrode and the second transition electrode are made of a material of N+ type amorphous silicon (see, e.g., description of Fig. 9: semiconductor doped layer 105, from which patterns 1051 and 1052 are later formed, is made of N+ a-Si material).
Regarding Claim 23, Wu (see, e.g., Fig. 17) shows a third electrode (e.g., gate 101) disposed between the substrate and the insulating layer.
Regarding Claim 24, Wu (see, e.g., Fig. 17) shows a passivation layer (e.g., passivation layer pattern 107) covering exposed surfaces of the insulating layer, the electrode layer, and the nanowire.
Regarding Claim 26, Wu (see, e.g., Machine Translation) discloses “an array substrate” and “a display device”, wherein “In a third aspect, an embodiment of the present invention provides an array substrate, comprising the second aspect of the thin film transistor”, and “In a fourth aspect, an embodiment of the present invention provides a display device, comprising the third aspect of the array substrate.”. Therefore, Wu shows a semiconductor device (e.g., array substrate or display device), comprising: the thin film transistor of claim 18.
Allowable Subject Matter
Claims 2-4, 10, 12-16, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional reference cited disclose nanowire-based thin film transistors and methods of manufacturing thereof, with some features or method steps similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814