DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Foreign Priority Claim
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 07/28/2023. The certified copy of the Korean application number KR10-2021-0012899 filed on 07/28/2023 is acknowledged in this Office Action.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 04/03/2026 is in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Response to Amendment
The amendment with respect to claim(s) 1-4, 9-17, and 19-20 filed on 01/02/2026 have been fully considered for examination based on their merits. The claim(s) 5-8, and 18 are canceled.
Specification
The amendment with respect to Specification filed on 01/02/2026 are being considered and entered.
Response to Arguments
Applicant’s arguments (see Remarks, pages 8-11, filed on 01/02/2026) with respect to claim(s) 1, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding Independent Claim(s) 1 and 15. Applicant argues (see Remarks, page 11) that HSU prior art fails to teach the amended claim limitations, such as the arrangements of an upper pad, lower pad and their relations in terms of width, and thickness. Applicant further argues that none of the other prior art cures the deficiencies of the amended features to claim 1. The Examiner reviewed the amended claim limitations, but are moot as mentioned above.
The claims 2-4, 9-14, 16-17, and 19-20 depends on the independent claims 1 and 15. Therefore these dependent claims follows similar arguments and are further rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 9, 11-17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takahiro Rokugawa, (hereinafter ROKUGAWA), US 20160005685 A1, in view of Neil McLellan et al, (hereinafter MCLELLAN), US 20090032941 A1, and further in view of Yu-Ling Hsieh et al, (hereinafter HSIEH), US 20110299259 A1.
Regarding Claim 1, ROKUGAWA teaches a circuit board (Fig. 1B, wiring substrate) comprising:
an insulating layer (Fig. 1B, 24, insulation layer);
a protective layer (Fig. 1B, 41, solder resist layer, [0027]) disposed on the insulating layer (Fig. 1B, 24, insulation layer);
an electrode layer (annotated Figure 1B) disposed on the insulating layer (Fig. 1B, 24, insulation layer) and passing through upper (Fig. 1B, 41a, [0037]) and lower surfaces (annotated Figure 1B) of the protective layer (Fig. 1B, 41, solder resist layer, [0027]),
wherein the electrode layer (annotated Figure 1B) includes:
a lower pad (Fig. 1B, 26b, metal plating layer) disposed on the insulating layer (Fig. 1B, 24, insulation layer) and having a first width (annotated Figure 1B);
an upper pad (Fig. 1B, 27, metal post) disposed on the lower pad (Fig. 1B, 26b, metal plating layer) and having a second width (annotated Figure 1B) smaller than the first width (annotated Figure 1B).
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ROKUGAWA does not disclose a circuit board comprising: wherein a thickness of the lower pad is greater than a thickness of the upper pad.
MCLELLAN teaches a circuit board (Fig. 13, 290, electrical device, may be a printed circuit board, [0064]) comprising: wherein a thickness (annotated Figure 15) of the lower pad (Fig. 15, 200, bond pad) is greater (annotated Figure 15) than a thickness (annotated Figure 15) of the upper pad (Fig. 15, 230, metallization layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ROKUGAWA to incorporate the teachings of HSIEH, such that a circuit board comprising: wherein a thickness of the lower pad is greater than a thickness of the upper pad, so that to reduce and/or avoid the electrical device failure (MCLELLAN, [0008]).
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ROKUGAWA as modified by MCLELLAN does not disclose a circuit board comprising: wherein an upper surface of the upper pad and the upper surface of the protective layer are located on a same plane.
HSIEH teaches a circuit board (Fig. 2, 20) comprising: wherein an upper surface (annotated Figure 7) of the upper pad (Fig. 7, 65, conductor post) and the upper surface (annotated Figure 7) of the protective layer (Fig. 7, 125, photomask) are located on a same plan (annotated Figure 7).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ROKUGAWA as modified by MCLELLAN to incorporate the teachings of HSIEH, such that a circuit board comprising: wherein an upper surface of the upper pad and the upper surface of the protective layer are located on a same plane, so that the patterning of the pads or bumps with lateral dimensions for efficient flip-chip soldier bump design for a semiconductor package (HSIEH, [0006]).
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Regarding Claim 2, ROKUGAWA as modified by MCLELLAN and HSIEH teaches the circuit board of claim 1.
ROKUGAWA further teaches the circuit board (Fig. 1B, wiring substrate), wherein the electrode layer (annotated Figure 1B) includes a seed layer (Fig. 1B, 26a) disposed between an upper surface (annotated Figure 1B) of the insulating layer (Fig. 1B, 24, insulation layer) and the lower pad (Fig. 1B, 26b, metal plating layer).
HSIEH further teaches the circuit board (Fig. 2, 20), wherein a thickness in a vertical direction (annotated Figure 7) from a lower surface (annotated Figure 7) of the seed layer (Fig. 2, 100) to the upper surface (annotated Figure 7) of the upper pad (Fig. 7, 65, conductor post) is equal to a thickness in the vertical direction (annotated Figure 7) from the upper surface (annotated Figure 7) of the protective layer (Fig. 7, 125, photomask) to the lower surface (annotated Figure 7) of the protective layer (Fig. 7, 125, photomask).
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Regarding Claim 3, ROKUGAWA as modified by MCLELLAN and HSIEH teaches the circuit board of claim 1.
ROKUGAWA further teaches the circuit board (Fig. 1B, wiring substrate), further comprising:
a surface treatment layer (Fig. 1B, 28, surface-processed layer, [0033]) disposed on the electrode layer (annotated Figure 1B), and
wherein the thickness (annotated Figure 1B) of the lower pad (Fig. 1B, 26b, metal plating layer) is greater than a thickness (annotated Figure 1B) of the surface treatment layer (Fig. 1B, 28, surface-processed layer, [0033]).
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Regarding Claim 4, ROKUGAWA as modified by MCLELLAN and HSIEH teaches the circuit board of claim 3.
ROKUGAWA further teaches the circuit board (Fig. 1B, wiring substrate), wherein the surface treatment layer (Fig. 1B, 28, surface-processed layer, [0033]) has a third width (annotated Figure 1B) that is smaller than the first width (annotated Figure 1B) and greater than the second width (annotated Figure 1B).
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Regarding Claim 9, ROKUGAWA as modified by MCLELLAN and HSIEH teaches the circuit board of claim 3.
ROKUGAWA further teaches the circuit board (Fig. 1B, wiring substrate), wherein the surface treatment layer fourth layer (Fig. 1B, 28, surface-processed layer, [0033]) of the electrode layer (annotated Figure 1B) includes:
a first portion (annotated Figure 1B) disposed on an upper surface (annotated Figure 1B) of the upper pad third layer (Fig. 1B, 27, metal post) of the electrode layer (annotated Figure 1B); and
a second portion (annotated Figure 1B) extending from the first portion (annotated Figure 1B) and disposed on the upper surface (annotated Figure 1B) of the protective layer (Fig. 1B, 41, solder resist layer, [0027]).
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Regarding Claim 11, ROKUGAWA as modified by MCLELLAN and HSIEH teaches the circuit board of claim 2.
ROKUGAWA further teaches the circuit board (Fig. 1B, wiring substrate), wherein the insulating layer (annotated Figure 1A) includes a first insulating layer (Fig. 1A, 22) and a second insulating layer (Fig. 1A, 24) disposed on the first insulating layer (Fig. 1A, 22), and
wherein the seed layer (Fig. 1B, 26a) of the electrode layer (annotated Figure 1B) is disposed on the second insulating layer (Fig. 1A, 24).
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Regarding Claim 12, ROKUGAWA as modified by MCLELLAN and HSIEH teaches the circuit board of claim 11.
ROKUGAWA further teaches the circuit board (Fig. 1B, wiring substrate), further comprising:
an interlayer circuit pattern (Fig. 1A, 23, wiring layer) disposed between the first insulating layer (Fig. 1A, 22) and the second insulating layer (Fig. 1A, 24), and
wherein a surface roughness (Ra) of the interlayer circuit pattern (Fig. 1A, 23, wiring layer) is different ([0050]) from a surface roughness (Ra) of the upper pad (Fig. 1B, 27, metal post) of the electrode layer (annotated Figure 1B).
Regarding Claim 13, ROKUGAWA as modified by MCLELLAN and HSIEH teaches the circuit board of claim 12.
ROKUGAWA further teaches the circuit board (Fig. 1B, wiring substrate), wherein the surface roughness (Ra) of the interlayer circuit pattern (Fig. 1A, 23, wiring layer) is greater ([0050]) than the surface roughness (Ra) of the upper pad (Fig. 1B, 27, metal post) of the electrode layer (annotated Figure 1B).
Regarding Claim 14, ROKUGAWA as modified by MCLELLAN and HSIEH teaches the circuit board of claim 13.
ROKUGAWA further teaches the circuit board (Fig. 1B, wiring substrate), wherein a surface roughness (Ra) of the protective layer (Fig. 1B, 41, solder resist layer, [0027]) is smaller ([0050, [0053]) than the surface roughness (Ra) of the interlayer circuit pattern (Fig. 1A, 23, wiring layer) and greater ([0050, [0053]) than the surface roughness (Ra) of the upper pad (Fig. 1B, 27, metal post) of the electrode layer (annotated Figure 1B).
Regarding Claim 15, ROKUGAWA teaches a semiconductor package (Fig. 1A, 1, semiconductor device, [0072]) comprising:
an insulating layer (Fig. 1B, 24, insulation layer);
a protective layer (Fig. 1B, 41, solder resist layer, [0027]) disposed on the insulating layer (Fig. 1B, 24, insulation layer);
a pad part (annotated Figure 1B) disposed on the insulating layer (Fig. 1B, 24, insulation layer) and passing through upper (Fig. 1B, 41a, [0037]) and lower surfaces (annotated Figure 1B) of the protective layer (Fig. 1B, 41, solder resist layer, [0027]);
a surface treatment layer (Fig. 1B, 28, surface-processed layer, [0033]) disposed on the pad part (annotated Figure 1B);
a first adhesive member (Fig. 1B, 72, underfill resin, [0069]) disposed on the surface treatment layer (Fig. 1B, 28, surface-processed layer, [0033]);
a semiconductor chip (Fig. 1B, 60, semiconductor element) disposed on the first adhesive member (Fig. 1B, 72, underfill resin, [0069]); and
a molding layer (Fig. 1B, 71, solder) molding (Fig. 1B, [0036]) the semiconductor chip (Fig. 1B, 60, semiconductor element);
wherein the pad part (annotated Figure 1B) includes:
a lower pad (Fig. 1B, 26b, metal plating layer) disposed on the insulating layer (Fig. 1B, 24, insulation layer) and having a first width (annotated Figure 1B);
an upper pad (Fig. 1B, 27, metal post) disposed on the lower pad (Fig. 1B, 26b, metal plating layer) and having a second width (annotated Figure 1B) smaller than the first width (annotated Figure 1B).
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ROKUGAWA does not disclose a circuit board comprising: wherein a thickness of the lower pad is greater than a thickness of the upper pad.
MCLELLAN teaches a circuit board (Fig. 13, 290, electrical device, may be a printed circuit board, [0064]) comprising: wherein a thickness (annotated Figure 15) of the lower pad (Fig. 15, 200, bond pad) is greater (annotated Figure 15) than a thickness (annotated Figure 15) of the upper pad (Fig. 15, 230, metallization layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ROKUGAWA to incorporate the teachings of HSIEH, such that a circuit board comprising: wherein a thickness of the lower pad is greater than a thickness of the upper pad, so that to reduce and/or avoid the electrical device failure (MCLELLAN, [0008]).
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ROKUGAWA as modified by MCLELLAN does not disclose a circuit board comprising: wherein an upper surface of the upper pad and the upper surface of the protective layer are located on a same plane.
HSIEH teaches a circuit board (Fig. 2, 20) comprising: wherein an upper surface (annotated Figure 7) of the upper pad (Fig. 7, 65, conductor post) and the upper surface (annotated Figure 7) of the protective layer (Fig. 7, 125, photomask) are located on a same plan (annotated Figure 7).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ROKUGAWA as modified by MCLELLAN to incorporate the teachings of HSIEH, such that a circuit board comprising: wherein an upper surface of the upper pad and the upper surface of the protective layer are located on a same plane, so that the patterning of the pads or bumps with lateral dimensions for efficient flip-chip soldier bump design for a semiconductor package (HSIEH, [0006]).
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Regarding Claim 16, ROKUGAWA as modified by MCLELLAN and HSIEH teaches the circuit board of claim 15.
ROKUGAWA further teaches the circuit board (Fig. 1B, wiring substrate), wherein the pad part (annotated Figure 1B) includes a seed layer (Fig. 1B, 26a) disposed between an upper surface (annotated Figure 1B) of the insulating layer (Fig. 1B, 24, insulation layer) and the lower pad (Fig. 1B, 26b, metal plating layer).
HSIEH further teaches the circuit board (Fig. 2, 20), wherein a thickness in a vertical direction (annotated Figure 7) from a lower surface (annotated Figure 7) of the seed layer (Fig. 2, 100) to the upper surface (annotated Figure 7) of the upper pad (Fig. 7, 65, conductor post) is equal to a thickness in the vertical direction (annotated Figure 7) from the upper surface (annotated Figure 7) of the protective layer (Fig. 7, 125, photomask) to the lower surface (annotated Figure 7) of the protective layer (Fig. 7, 125, photomask).
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Regarding Claim 17, ROKUGAWA as modified by MCLELLAN and HSIEH teaches the circuit board of claim 15.
ROKUGAWA further teaches the circuit board (Fig. 1B, wiring substrate), wherein the surface treatment layer (Fig. 1B, 28, surface-processed layer, [0033]) has a third width (annotated Figure 1B) that is smaller than the first width (annotated Figure 1B) and greater than the second width (annotated Figure 1B).
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Regarding Claim 20, ROKUGAWA as modified by MCLELLAN and HSIEH teaches the circuit board of claim 15.
ROKUGAWA further teaches the circuit board (Fig. 1B, wiring substrate), wherein the surface treatment layer fourth layer (Fig. 1B, 28, surface-processed layer, [0033]) of the electrode layer (annotated Figure 1B) includes:
a first portion (annotated Figure 1B) disposed on an upper surface (annotated Figure 1B) of the upper pad third layer (Fig. 1B, 27, metal post) of the electrode layer (annotated Figure 1B); and
a second portion (annotated Figure 1B) extending from the first portion (annotated Figure 1B) and disposed on the upper surface (annotated Figure 1B) of the protective layer (Fig. 1B, 41, solder resist layer, [0027]).
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Claim(s) 10, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over ROKUGAWA, in view of MCLELLAN, further in view of HSIEH, and further in view of Yun Mi Bae et al, (hereinafter BAE), US 20180332714 A1.
Regarding Claim 10, ROKUGAWA as modified by MCLELLAN and HSIEH teaches the circuit board of claim 1.
ROKUGAWA as modified by MCLELLAN and HSIEH does not explicitly disclose the circuit board, wherein at least one of a side surface of the lower pad and a side surface of the upper pad includes a curved surface whose width increases in a horizontal direction toward an upper surface of the insulating layer.
BAE teaches in Figures 2-3, the circuit board (Fig. 2, 100, printed circuit board) of claim 1, wherein at least one of a side surface of the lower pad and a side surface of the upper pad (annotated Figure 11, 130, circuit pattern) includes a curved surface (annotated Figure 11) whose width increases (annotated Figure 11) in a horizontal direction (annotated Figure 11) toward an upper surface of the insulating layer (Fig. 11, 110).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ROKUGAWA as modified by MCLELLAN and HSIEH to incorporate the teachings of BAE, such that the circuit board, wherein at least one of a side surface of the lower pad and a side surface of the upper pad includes a curved surface whose width increases in a horizontal direction toward an upper surface of the insulating layer, so that the circuit pattern (130/230) may have a shape in which the top and bottom surfaces thereof have mutually different widths and facilitate that the mounting area of the components mounted on the circuit may be increased; accordingly the reliability of a customer may be improved (BAE, [0085], [0162], [0166]).
Regarding Claim 19, ROKUGAWA as modified by MCLELLAN and HSIEH teaches the circuit board of claim 15.
ROKUGAWA as modified by MCLELLAN and HSIEH does not explicitly disclose the circuit board, wherein at least one of a side surface of the lower pad and a side surface of the upper pad includes a curved surface whose width increases in a horizontal direction toward an upper surface of the insulating layer.
BAE teaches in Figures 2-3, the circuit board (Fig. 2, 100, printed circuit board) of claim 1, wherein at least one of a side surface of the lower pad and a side surface of the upper pad (annotated Figure 11, 130, circuit pattern) includes a curved surface (annotated Figure 11) whose width increases (annotated Figure 11) in a horizontal direction (annotated Figure 11) toward an upper surface of the insulating layer (Fig. 11, 110).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ROKUGAWA as modified by MCLELLAN and HSIEH to incorporate the teachings of BAE, such that the circuit board, wherein at least one of a side surface of the lower pad and a side surface of the upper pad includes a curved surface whose width increases in a horizontal direction toward an upper surface of the insulating layer, so that the circuit pattern (130/230) may have a shape in which the top and bottom surfaces thereof have mutually different widths and facilitate that the mounting area of the components mounted on the circuit may be increased; accordingly the reliability of a customer may be improved (BAE, [0085], [0162], [0166]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20130168132 A1 – Figures 2-12
STATEMENT OF RELEVANCE – View sequentially showing a method of manufacturing a printed circuit board.
US 20110088929 A1 – Figure 4
STATEMENT OF RELEVANCE – A metal structure of a multi-layer substrate, with a base area (404) having greater width than the main body (402).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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