Prosecution Insights
Last updated: April 19, 2026
Application No. 18/275,275

SPECTRUM CHIP AND MANUFACTURING METHOD THEREFOR, AND SPECTRUM ANALYSIS DEVICE

Non-Final OA §102§103§112
Filed
Aug 01, 2023
Examiner
YAP, DOUGLAS ANTHONY
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BEIJING SEETRUM TECHNOLOGY CO., LTD.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
3y 3m
To Grant
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
43 granted / 49 resolved
+19.8% vs TC avg
Moderate +12% lift
Without
With
+12.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
48 currently pending
Career history
97
Total Applications
across all art units

Statute-Specific Performance

§103
50.9%
+10.9% vs TC avg
§102
25.2%
-14.8% vs TC avg
§112
21.2%
-18.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 49 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: claim 77 requires a partial region of the light modulation layer and other partial regions of the light modulation layer which lacks antecedence in the specification. For purpose of compact prosecution, the examiner will find art that teaches any part of the light modulation layer having a light modulation layer and any part of the light modulation layer having a non-modulation layer. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “etching or nano-imprinting the first light modulation layer to form the first light modulation structure with at least one first modulation unit” and “etching or nano-imprinting the second light modulation layer to form the second light modulation structure with at least one second modulation unit,” emphasis added, as required by claim 61 must be shown or the feature(s) canceled from the claim(s). A similar limitation on claim 62 is also recited in the limitation of “etching or nano-imprinting the first light modulation layer to form the first light modulation structure with at least one first modulation unit.” No new matter should be entered. The preposition with carries the plain meaning of “to indicate a participation in an action, transaction, or arrangement,” as defined by Merriam-Webster dictionary. However, the specification and figures does not show the first modulation unit and/or the second modulation unit being used in a manner to carry out the etching of the first light modulation layer and/or second light modulation layer to form the first light modulation structure and/or second light modulation structure. For example, the first modulation unit was not used as a masking element in the etching process or was not used as an etchant. Instead, Figs. 6A-6C shows first modulation unit 110 and/or the second modulation unit 110 is the result of the etching actions done to first light modulation layer 114 and/or second light modulation layer 115. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections Claim 78 is objected to because of the following informalities: a spectrum chip, which is already defined in the preamble of the claim is again redefined in the limitation of “the modulation unit is held on a photosensitive path of the sensing unit to obtain a spectrum chip”. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 61-65 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 61, and by extension, dependent claims 63-65, recites the limitation of “etching or nano-imprinting the first light modulation layer to form the first light modulation structure with at least one first modulation unit” and “etching or nano-imprinting the second light modulation layer to form the second light modulation structure with at least one second modulation unit,” emphasis added. The preposition with carries the plain meaning of “to indicate a participation in an action, transaction, or arrangement,” as defined by Merriam-Webster dictionary. A similar limitation on claim 62 is also recited in the limitation of “etching or nano-imprinting the first light modulation layer to form the first light modulation structure with at least one first modulation unit.” However, the specification and figures does not show the first modulation unit and/or the second modulation unit being used in a manner to carry out the etching of the first light modulation layer and/or second light modulation layer to form the first light modulation structure and/or second light modulation structure. For example, the first modulation unit was not used as a masking element in the etching process or was not used as an etchant. Instead, Figs. 6A-6C shows first modulation unit 110 and/or the second modulation unit 110 is the result of the etching actions done to first light modulation layer 114 and/or second light modulation layer 115. For the purpose of compact prosecution, the examiner will find art that teaches what is illustrated in Figs. 6A-6C. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 61-74, 76-78 and 80 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 61 and, by extension, dependent claims 63-65, the claim requires a first light modulation structure and a second light modulation structure and parent claim 60 also requires at least two light modulation structures. It is unclear whether the first light modulation structure and a second light modulation structure is the same as the at least two light modulation structures or a different set of elements altogether. For the purpose of compact prosecution, the examiner will treat at least two light modulation structure to be comprised of a first light modulation structure and a second light modulation structure. Furthermore, claim 61 recites the limitation of "forming the at least one light modulation structure on the substrate.” There is insufficient antecedent basis for “the at least one light modulation structure” in the claim and it is unclear whether the at least one light modulation structure is the same as the modulation unit jointed panel or one of the array of light modulation structures, which are also formed on a substrate as defined in parent claim 60, or is a different element altogether. For the purpose of compact prosecution, the examiner will treat the forming of the at least one light modulation structure to be the forming one of the array of light modulation structure. Lastly, claim 61 and, by extension, dependent claims 63-65, recite the limitation of “etching or nano-imprinting the first light modulation layer to form the first light modulation structure with at least one first modulation unit” and “etching or nano-imprinting the second light modulation layer to form the second light modulation structure with at least one second modulation unit,” emphasis added. The preposition with carries the plain meaning of “to indicate a participation in an action, transaction, or arrangement,” as defined by Merriam-Webster dictionary. A similar limitation on claim 62 is also recited in the limitation of “etching or nano-imprinting the first light modulation layer to form the first light modulation structure with at least one first modulation unit.” As discussed in the 35 USC § 112 (a) rejection above, the subject matter is not disclosed in the disclosure and the examiner cannot ascertain the metes and bounds of this limitation. Hence, the examiner rejects this limitation as indefinite. Regarding claim 62, the claim recites “wherein the at least one modulation unit includes a first light modulation structure.” It is unclear whether the first light modulation structure is the same as one of the at least two light modulation structures as required in parent claim 60 or is a different structure. For the purpose of compact prosecution, the examiner will treat the first light modulation structure to be the same as in the parent claim. Claims 62, 66, 68, 70-72, 74, and 77-78 also requires forming the at least one light modulation structure which does not have antecedence basis. The examiner will treat this to be one of the array of light modulation structures defined in parent claim 60. Regarding claim 66, its dependent claims 67-68, claims 70-74, claim 69 and claim 80 as well as claim 76 and its dependent claim 77 recite the limitation of “the modulation unit”. There is insufficient antecedent basis for “the modulation unit” in these claims. For the purpose of compact prosecution, the examiner will treat the modulation unit defined in claims 66, 67-68, 69, and 70-74 to be same as the modulation unit jointed panel as defined in parent claim 60. Similarly, these claims recite the limitation of “the sensing unit.” There is insufficient antecedent basis for “the sensing unit” in these claims. The examiner will treat the sensing unit jointed panel as defined in parent claim 60 to be the same as the sensing unit of these claims. Regarding claim 71, the claim requires a proportion. The plain meaning of proportion is a ratio between two numbers. However, the claim only recites one number, which is the distance between the lower surface of the light modulation structure and the upper surface of the dielectric layer. As the examiner cannot ascertain what is the other number that consists of this proportion, for the purpose of compact prosecution, the examiner will find art that teaches a distance between the lower surface of the light modulation structure and the upper surface of the dielectric. Furthermore, claim 80 recites the limitation of "wherein the modulation unit and the sensing unit are bound to each other by a van der Waal force under the action of the encapsulation body” There is insufficient antecedent basis for “the encapsulation body.” For the purpose of compact prosecution, the examiner will treat the encapsulation body to be the same as the encapsulation body defined in claim 83. The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim 64 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 64 recites the limitation of providing a first light modulation layer on the substrate. Parent claim 61 already requires forming the first light modulation layer on the substrate. Hence, claim 64 does not further limit the claimed subject matter of parent claim 61. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim 78 is rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by Cui ‘820 (CN 111505820 A; see English translation in FOR mailed on March 24, 2025). Regarding claim 78, Cui ‘820 teaches a method for manufacturing a spectrum chip (see Abstract), characterized by comprising: forming at least one light modulation structure (5, see Fig. 2) on a substrate (4, see Fig. 15 and Example ten in Page 14 of English translation: “If the transfer process is adopted, silicon dioxide can be used as the preparation substrate of the light modulation layer 1…”) to obtain a modulation unit (1&4, see Fig. 15; Example ten in Page 14: “the prepared light modulation layer 1 and the light-transmitting layer 4 are transferred to the image sensing layer 2 as a whole”); and coupling the modulation unit to a sensing unit (2), so that the modulation unit is held on a photosensitive path (Fig. 19: light travels from lens 23 through 24, 1 and then to 2) of the sensing unit to obtain a spectrum chip (see Abstract and Summary of Invention in Pages 1-2). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 60, 66, 75-77 and 79 are rejected under 35 U.S.C. 103 as being unpatentable over Cui ‘820 (CN 111505820 A; see English translation in FOR mailed on March 24, 2025) in view of Kimura (US 2020/0103220 A1). Regarding claim 60, Cui ‘820 teaches a method for manufacturing a spectrum chip (see Abstract), characterized by comprising: forming an array of light modulation structures (5, see Fig. 2; 5 is part of layer 1 in Fig. 15) including at least two light modulation structures (Fig. 2 shows two or more 5) on a substrate (4, see Fig. 15 and Example 10 in Page 14 of English translation: “if using the transfer process scheme, the silicon dioxide can be used as the preparation substrate of the light modulation layer 1”) to obtain a modulation unit jointed panel (1&4, see Fig. 15 and Example ten in Page 14: “the prepared light modulation layer 1 and the light-transmitting layer 4 are transferred to the image sensing layer 2 as a whole”; alternatively, modulation unit jointed panel includes 1, 24, and 23 in Fig. 19); providing a sensing unit jointed panel (2&3) which includes at least two sensing units (7, see Fig. 2); coupling the modulation unit jointed panel to the sensing unit jointed panel to obtain a spectrum chip jointed panel (see the structure of Fig. 15). Cui ‘820 further teaches using forming the sensing unit on a wafer ( Detailed description, Page 6, first paragraph: “image sensing layer 2 is a CIS wafer”) but does not teach: dividing the spectrum chip jointed panel to obtain at least two spectrum chips. Kimura, in the same field of invention, teaches dividing a wafer (10) to obtain individual chips (¶ 0002). Hence, Cui ’820 in view of Kimura teaches dividing the spectrum chip jointed panel to obtain at least two spectrum chips. A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kimura into the method of Cui ‘820 to divide the spectrum chip jointed panel to obtain at least two spectrum chips. The ordinary artisan would have been motivated to modify Cui ‘820 in the manner set forth above for at least the purpose of optimizing the yield of the manufacturing process by building multiple spectrum chips on a wafer concurrently and then singulating each chip to obtain individual device chips from the wafer in order to be further packaged into stand-alone applications, such as, but not limited to, mobile phones or personal computers (Kimura ¶ 0002). Regarding claim 66, the method for manufacturing the spectrum chip according to claim 60, wherein coupling the modulation unit to the sensing unit, so that the modulation unit is held on the photosensitive path of the sensing unit to obtain the spectrum chip includes: coupling the modulation unit to the sensing unit in a flip-chip manner (Cui ‘820, Page 11: Example 5 and Fig. 11: back-illuminated structure; also Fig. 7 is flipped to obtain Fig. 11), wherein at least one light modulation structure of the modulation unit is overlaid on the sensor (Cui ‘820 Page 11: “the light modulation layer 1 is directly integrated on the light detection layer 22”). Regarding claim 75, the method for manufacturing the spectrum chip according to claim 60, wherein the light modulation structure includes a modulation portion (1&6, see Cui ‘820 Figs. 3 & 19; note: 1 has modulation holes 6) and a non-modulation portion (23&24). Regarding claim 76, the method for manufacturing the spectrum chip according to claim 75, wherein the modulation portion includes at least one light modulation unit (1 & 6 constitute the modulation panel 1 & 4 in claim 60 rejection; see also 35 USC § 112 rejection), and the non-modulation portion includes at least one filter unit (24, see Cui ‘820 Fig. 19). Regarding claim 77, the method for manufacturing the spectrum chip according to claim 76, wherein forming the at least one light modulation structure (1 & 24 & 23, see Cui ‘820 Fig. 19) on the substrate to obtain the modulation unit includes: forming a light modulation layer (1) on the substrate (4, see Fig. 15 and also 35 USC § 103 rejection of claim 60); forming the modulation portion (6, see Fig. 3) in a partial region (portions of 1 with 6) of the light modulation layer; and forming the non-modulation portion in other partial regions of the light modulation layer (Fig. 19 shows 23 & 24 not formed within 1). Regarding claim 79, teaches a spectrum chip (see Abstract of Cui ‘820) manufactured by the method for manufacturing the spectrum chip according to claim 60 (see 35 USC § rejection of claim 60 above). Claim(s) 61 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cui ‘820 (CN 111505820 A; see English translation in FOR mailed on March 24, 2025) in view of Kimura (US 2020/0103220 A1) as applied to claim 60 above, and further in view of Cui ‘060 (CN 111490060 A; see English translation in FOR mailed on August 11, 2023). Regarding claim 61, Cui ‘820 in view of Kimura teaches the method for manufacturing the spectrum chip according to claim 60 but does not teach: wherein the at least one light modulation structure includes a first light modulation structure and a second light modulation structure; forming the at least one light modulation structure on the substrate to obtain the modulation unit includes: forming a first light modulation layer on the substrate; forming a second light modulation layer on the first light modulation structure. Cui ‘820, in a different embodiment, teaches a method wherein the at least one light modulation structure includes a first light modulation structure (102 and through-holes 6, see Cui ‘820 Figs. 8-10) and a second light modulation structure (101 and through-holes 6); and forming the at least one light modulation structure on the substrate to obtain the modulation unit includes: forming a first light modulation layer (102) on the substrate (in view of Cui’ 820 Fig. 15, 102 is formed on substrate 4); forming a second light modulation layer (101) on the first light modulation structure (as shown in Figs. 8-9, 101 is formed on top of 102) A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of a different embodiment of Cui ‘820 into the method of Cui ‘820 in view of Kimura to include a first light modulation layer and a second light modulation layer in the at least one light modulation structure, with the first light modulation layer formed on the substrate and the second light modulation layer formed on the first light modulation layer. The ordinary artisan would have been motivated to modify Cui ‘820 in view of Kimura in the manner set forth above for at least the purpose of increasing the modulation capability of the light modulation structure, thus improving the precision and frequency spectrum of the spectrum chip (Cui ‘820: Page 3, Beneficial effects 2) Cui ‘820 further teaches modulation holes (6) in the first light modulation layer and the second light modulation layer (see Page 10: Example 2). However, Cui ‘820 in view of Kimura does not teach: etching or nano-imprinting the first light modulation layer to form the first light modulation structure with at least one first modulation unit; and etching or nano-imprinting the second light modulation layer to form the second light modulation structure with at least one second modulation unit. Cui ‘060, in the same field of invention, teaches a method comprising etching the light modulation layer to obtain modulation holes (Page 8: “Fourth, as shown in Fig. 12, the polarization-independent light modulation layer 110 is prepared by directly etching… The modulation hole array of the light modulation layer 110 may be [obtained by using] one or any combination of the above two solutions”). Hence, Cui ‘820 in view of Kimura and Cui ‘060 teaches: etching or nano-imprinting the first light modulation layer to form the first light modulation structure with at least one first modulation unit (see also 35 USC § 112 rejection above); and etching or nano-imprinting the second light modulation layer to form the second light modulation structure with at least one second modulation unit (see also 35 USC § 112 rejection above). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Cui ‘060 into the method of Cui ’820 in view of Kimura to etch the first light modulation layer and the second light modulation layer to form the first and second light modulation layers, respectively. The ordinary artisan would have been motivated to modify Cui ‘820 in view of Kimura in the manner set forth above for at least the purpose of using any of the multiple methods known in the art for forming through-holes in semiconductor layers. Regarding claim 62, Cui ‘820 in view of Kimura he method for manufacturing the spectrum chip according to claim 60, wherein the at least one modulation unit includes a first light modulation structure (Fig. 2 shows two or more 5; see 35 USC § 112 rejection above); and forming the at least one light modulation structure on the substrate to obtain the modulation unit including (see claim 60 rejection above): forming a first light modulation layer on the substrate (Fig. 2 shows two or more 5 formed on substrate 4; Cui’ 820 Fig. 15: layer 1 is the layer in which 5 is formed; see 35 USC § 103 of claim 60 rejection and 35 USC § 112 rejection). Cui ‘820 further teaches forming modulation holes (6) in the first light modulation layer (see Page 10: Example 2). However, Cui ‘820 in view of Kimura does not teach: etching or nano-imprinting the first light modulation layer to form the first light modulation structure with at least one first modulation unit (see also 35 USC § 112 rejection above). Cui ‘060, in the same field of invention, teaches a method comprising etching the light modulation layer to obtain modulation holes (Page 8: “Fourth, as shown in Fig. 12, the polarization-independent light modulation layer 110 is prepared by directly etching… The modulation hole array of the light modulation layer 110 may be [obtained by using] one or any combination of the above two solutions”). Hence, Cui ‘820 in view of Kimura and Cui ‘060 teaches: etching or nano-imprinting the first light modulation layer to form the first light modulation structure with at least one first modulation unit. A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Cui ‘060 into the method of Cui ’820 in view of Kimura to etch the first light modulation layer to form the first and second light modulation layers. The ordinary artisan would have been motivated to modify Cui ‘820 in view of Kimura in the manner set forth above for at least the purpose of using any of the multiple methods known in the art for forming through-holes of semiconductor layers. Regarding claim 63, the method for manufacturing the spectrum chip according to claim 61, wherein forming the first light modulation layer on the substrate includes: depositing the first light modulation layer on the substrate by a deposition process (Cui ‘820, Example 10 in Page 14 of English translation: “if a direction deposition and growth is adopted when preparing the light modulation layer 1…by chemical vapor deposition”) Regarding claim 64, the method for manufacturing the spectrum chip according to claim 61, wherein forming the first light modulation layer on the substrate includes: providing the first light modulation layer (102, see Cui ‘820 Fig. 8); and overlaying the light modulation layer on the substrate (4, see Cui ‘Fig. 15 and 35 USC § 103 rejection of claim 60 above). Regarding claim 65, the method for manufacturing the spectrum chip according to claim 61, wherein forming the second light modulation layer on the first light modulation structure includes: forming a connection layer (102, see Cui ‘820 Fig. 10) on the first light modulation layer; and forming the second light modulation layer on the connection layer (Fig. 10 shows 101 on top of 102). Claims 67 and 70- 74 are rejected under 35 U.S.C. 103 as being unpatentable over Cui ‘820 (CN 111505820 A; see English translation in FOR mailed on March 24, 2025) in view of Kimura (US 2020/0103220 A1) as applied to claim 66 above, and further in view of Tominaga (US 2015/0048239 A1). Regarding claim 67, Cui ‘820 in view of Kimura teaches the method for manufacturing the spectrum chip according to claim 66, wherein coupling the modulation unit to the sensing unit in the flip-chip manner. However, Cui ‘820 in view of Kimura do not teach the method includes: forming a dielectric layer on the sensing unit; and coupling the modulation unit to the dielectric layer. Tominaga, in the same field of invention, teaches a method for manufacturing a spectrum chip (Title, Abstract) comprising: forming a dielectric layer (103, see Fig. 3 and ¶ 0043) on the sensing unit (102, see ¶ 0042: silicon substrate 102 have photoelectric conversion regions, i.e., light sensing regions; see also ¶ 0002: an array of photodiodes); and coupling the modulation unit to the dielectric layer (Cui ‘820 in view of Kimura and Tominaga teaches coupling the modulation unit of Cui ’820 on top of Tominaga’s dielectric layer 103). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Tominaga into the method of Cui ‘820 in view of Kimura to forming a dielectric layer on the sensing unit and couple the modulation unit to the dielectric layer. The ordinary artisan would have been motivated to modify Cui ‘820 in view of Kimura in the manner set forth above for at least the purpose of using the dielectric layer as an anti-reflection layer for the further purpose of receiving a broad range of wavelengths of light to increase the detection sensitivity of the spectrum chip (Tominaga ¶ 0027). Regarding claim 70, the method for manufacturing the spectrum chip according to claim 67, wherein a distance (vertical distance) between a lower surface (bottom surface of 1 in Cui ‘820 Fig. 15) of the light modulation structure adjacent to the sensing unit in the at least one light modulation structure and an upper surface (upper surface of 2 in Cui ‘820, which in view of Tominaga, contains the dielectric layer) of the dielectric layer is less than or equal to 10 μm (Cui ‘820 Page 14, Example 10: “the thickness of the light-transmitting medium layer 4 is 50nm to 1 μm”). A person of ordinary skill, prior to the effective date of the claimed invention, will find it obvious to optimize the ranges of the thickness of the dielectric layer in order to optimize the transmittance characteristic of the device (see Chen Fig. 4). Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP § 2144.05 (II) (A). Regarding claim 71, the method for manufacturing the spectrum chip according to claim 70, wherein a proportion of the distance between the lower surface of the light modulation structure adjacent to the sensing unit in the at least one light modulation structure and the upper surface of the dielectric layer exceeding a preset threshold is less than or equal to 10% (proportion is not fully defined; see 35 USC § 112 rejection above). Regarding claim 72, the method for manufacturing the spectrum chip according to claim 71, wherein a difference in distances between respective corresponding positions on the lower surface of the light modulation structure adjacent to the sensing unit in the at least one light modulation structure and the upper surface of the dielectric layer is less than 10 μm (Cui ‘820 Fig. 15 teaches the layer 4 to have a consistent thickness; hence, a corresponding position on the lower surface of the light modulation structure and the corresponding position on the upper surface of the dielectric layer will always be less than 10 μm throughout the spectrum chip). Regarding claim 73, the method for manufacturing the spectrum chip according to claim 67, wherein the light modulation structure includes at least one light modulation unit (Cui ‘820 Fig.5 shows 5 having modulation units 11-16), wherein the distance between the lower surface of the light modulation structure adjacent to the sensing unit in the at least one light modulation structure and the upper surface of the dielectric layer is less than a length (length of the horizontal surface) of a side (horizontal surface of each module 11-16) of the light modulation unit. Regarding claim 74, the method for manufacturing the spectrum chip according to claim 67, wherein a difference in distances between any two regions (Cui ‘820 Fig. 15: leftmost and rightmost point of the bottom surface of 1) in the lower surface of the light modulation structure adjacent to the sensing unit in the at least one light modulation structure and two corresponding regions (Cui ‘820 Fig. 15: leftmost and rightmost point of the top surface of 2) in the upper surface of the dielectric layer is less than or equal to 10 μm (Cui ‘820 Fig. 15 teaches the layer 4 to have a consistent thickness; hence, the difference in distances between any two regions in the lower surface of the light modulation structure and the two corresponding regions in the upper surface of the dielectric layer will always be less than 10 μm throughout the spectrum chip). Claims 68 and 69 are rejected under 35 U.S.C. 103 as being unpatentable over Cui ‘820 (CN 111505820 A; see English translation in FOR mailed on March 24, 2025) in view of Kimura (US 2020/0103220 A1) and Tominaga (US 2015/0048239 A1) as applied to claim 67 above, and further in view of Chung (US 2020/0411472 A1) as evidenced by Aliane (US 2021/0199509 A1) Regarding claim 68, Cui ‘820 in view of Kimura and Tominaga teaches the method for manufacturing the spectrum chip according to claim 67, and further teaches the modulation unit comprising of a dielectric (substrate 4 on which the at least two light modulation structures are formed is made of silicon oxide; see 35 USC § 103 rejection of claim 60 above and Cui ‘820 Example 10 in Page 14: “the thickness of the light-transmitting medium layer 4 is 50nm to 1 μm, and the material may be silicon dioxide”). However, Cui ‘820 in view of Kimura and Tominaga does not teach the method wherein coupling the modulation unit to the dielectric layer includes: forming a binding layer on the at least one light modulation structure of the modulation unit; and coupling the modulation unit to the dielectric layer in a manner that the binding layer is bound to the dielectric layer. Chung, in the same field of invention, teaches a method wherein coupling a first dielectric layer (62, see Fig. 4 and ¶ 0035; analogous to the modulation unit) to a second dielectric layer (108; analogous to the dielectric layer) includes: forming a binding layer (the bonding surfaces between two dielectric structures constitute a binding layer) on the at least one light modulation structure of the modulation unit; and coupling the modulation unit to the dielectric layer in a manner that the binding layer is bound to the dielectric layer (¶ 0035: dielectric-to-dielectric bonding). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Wu into the method of Cui ‘820 in view of Kimura and Tominaga to form a binding layer on the at least one light modulation structure of the modulation unit in order to be coupled to the dielectric layer. The ordinary artisan would have been motivated to modify Cui ‘820 in view of Kimura and Tominaga in the manner set forth above for at least the purpose of using the hybrid bonding technique, which is known in the art as a method of joining two semiconductor structures (Chung Fig. 4 and ¶ 0035 teaches two structures: dies 50 and substrate 100, which are analogous to the modulation unit and the dielectric layer of Cui ‘820) together to form a singular device. Regarding claim 69, the method for manufacturing the spectrum chip according to claim 60, wherein coupling the modulation unit to the sensing unit, so that the modulation unit is held on the photosensitive path of the sensing unit to obtain the spectrum chip includes: attaching the modulation unit to the sensing unit by van der Waals forces (Chung ¶ 0035: hybrid bonding, which is known in the art to use van er Waal forces, as evidenced by Aliane ¶ 0102); or attaching the modulating unit to the sensing unit by an adhesive; or attaching the modulation unit to the sensing unit by a bonding process. Claims 81-84 are rejected under 35 U.S.C. 103 as being unpatentable over Cui ‘820 (CN 111505820 A; see English translation in FOR mailed on March 24, 2025) in view of Kimura (US 2020/0103220 A1) as applied to claim 60 above, and further in view of Chen (US 2019/0393362 A1). Regarding claim 81, Cui ‘820 in view of Kimura teaches a spectrum analysis device (Cui ‘820 Abstract), characterized by comprising: a spectrum chip manufactured by the method for manufacturing the spectrum chip according to claim 60 (see 35 USC § 103 rejection of claim 60 above). However, Cui ‘820 in view of Kimura does not teach the device comprising: a circuit board, wherein the spectrum chip is electrically connected to the circuit board. Chen, in the same field of invention, teaches a device (Fig. 7) comprising: a circuit board (10), wherein the spectrum chip (20; Cui ‘820 in view of Kimura and Chen teaches 20 to be the spectrum chip of Cui ‘820) is electrically connected to the circuit board. A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chen into the device of Cui ‘820 in view of Kimura to provide a circuit board, wherein the spectrum chip is connected to the circuit board. The ordinary artisan would have been motivated to modify Cui ‘820 in view of Kimura in the manner set forth above for at least the purpose of using the circuit board as means to electrically connect (through wires 25) the spectrum chip with other components (12, see Chen Fig. 7) and connectors (14) that comprises the entire device (see also Chen ¶ 0023). Regarding claim 82, the spectrum analysis device according to claim 81, further including: an optical module (50 or alternatively, 50 & 60, see Chen Figs. 9-10 and 12 and ¶ 0027) held on a photosensitive path (light enters through lens 62) of the spectrum chip (20). Regarding claim 83, the spectrum analysis device according to claim 81, further including an encapsulation body (50, see Chen Figs. 9-10 and 12) disposed on the circuit board, wherein the encapsulation body is integrally formed on the circuit board (Figs. 9-10 and 12 shows 50 disposed and formed on 10) and covers at least a part (portions of 20 directly contacting 50) of an outer surface (upper surface and sidewalls of 20) of the spectrum chip. Regarding claim 84, the spectrum analysis device according to claim 83, wherein the encapsulation body is made of an opaque material (Chen ¶ 0027). Claim 80 is rejected under 35 U.S.C. 103 as being unpatentable over Cui ‘820 (CN 111505820 A; see English translation in FOR mailed on March 24, 2025) in view of Kimura (US 2020/0103220 A1), as applied to claim 79 above, and further in view of Chen (US 2019/0393362 A1) and Chung (US 2020/0411472 A1) as evidenced by Aliane (US 2021/0199509 A1). Regarding claim 80, Cui ‘820 in view of Kimura teaches the spectrum chip according to claim 79, but does not teach the device with an encapsulation body. Chen, in the same field of invention, teaches a device with an encapsulation body (50, see Figs. 8-9 and 12) A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chen into the device of Cui ‘820 in view of Kimura to provide an encapsulating body. The ordinary artisan would have been motivated to modify Cui ‘820 in view of Kimura in the manner set forth above for at least the purpose of using the encapsulating body as part of a package body that provides mechanical protection to the spectrum device (110; see Chen ¶ 0021) and to prevent peripheral light from entering into the light-sensitive areas of the spectrum chip, so that only direct light can be captured by the sensors (Chen ¶ 0027: 50 is completely opaque). Cui ‘820 further teaches the modulation unit comprising of a dielectric (substrate 4 on which the at least two light modulation structures are formed is made of silicon oxide; see 35 USC § 103 rejection of claim 60 above and Cui ‘820 Example 10 in Page 14: “the thickness of the light-transmitting medium layer 4 is 50nm to 1 μm, and the material may be silicon dioxide”) and the sensing unit is made of a wafer (Page 3 “the CIS wafer is used as the image sensor layer”). However, Cui ‘820 in view of Kimura and Chen does not teach the device wherein the modulation unit and the sensing unit are bound with each other by a van der Waals force under the action of the encapsulation body. Chung, in the same field of invention, teaches a device wherein the dielectric layer (62, see Fig. 4; analogous to the modulation unit of Cui ‘820) and the wafer (108, see ¶ 0031: “100 may be a semiconductor wafer”; analogous to the sensing unit of Cui ‘820) are bound with each other by a van der Waals force (¶ 0035: through hybrid bonding, which is known in the art to use van der Waals forces, as evidenced by Aliane ¶ 0102) under the action of the encapsulation body (since the encapsulation body of Chen is disposed over and encloses the modulation unit and the sensing unit, then keeps the modulation unit and sensing unit in place). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chung into the device of Cui ‘820 in view of Kimura and Chen to use van der Waals forces under the action of the encapsulation body to bind the modulation unit and the sensing unit to each other. The ordinary artisan would have been motivated to modify Cui ‘820 in view of Kimura and Chen in the manner set forth above for at least the purpose of using the hybrid bonding technique, which is known in the art as a method of joining two semiconductor structures (Chung Fig. 4 and ¶ 0035 teaches two structures: dies 50 and wafer 100, which are analogous to the modulation unit and the sensing unit of Cui ‘820) together to form a singular device. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DOUGLAS YAP/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Aug 01, 2023
Application Filed
Dec 28, 2025
Non-Final Rejection — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604759
MICROELECTRONIC ASSEMBLIES INCLUDING STIFFENERS AROUND INDIVIDUAL DIES
2y 5m to grant Granted Apr 14, 2026
Patent 12598740
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Apr 07, 2026
Patent 12588519
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 24, 2026
Patent 12581993
Assembly for a Power Module, Power Module and Method for Producing an Assembly for a Power Module
2y 5m to grant Granted Mar 17, 2026
Patent 12568706
SEMICONDUCTOR DEVICE INCLUDING IMAGE SENSOR AND METHODS OF FORMING THE SAME
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+12.2%)
3y 3m
Median Time to Grant
Low
PTA Risk
Based on 49 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month