DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed on April 24, 2026, with respect to objections to specifications, drawings, and claims and the 35 USC § 112 (a), (b), and (d) rejections of claims 61-74, 76-78 and 80, and have been fully considered and are persuasive. The original objections to specification, drawings, and claims and the 35 USC § 112 (a), (b), and (d) rejections of claims 61-74, 76-78 and 80, have been withdrawn. However, due to the amendments to claims 60 and 74, new objections to the specifications and drawings are raised. Please see below.
Applicant's arguments filed with respect to 35 USC § 103 rejection of independent claim 60 have been fully considered but they are not persuasive. The amended limitation of a distance between an upper surface of the dielectric layer and a lower surface of the light modulation structure is less than a length of a side of the light modulation structure can be made obvious by the 35 USC § 103 rejection below in view of Enquist.
In summary, this application is not placed in a condition for an allowance.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a length of a side of the light modulation structure” and the “a distance between an upper surface of the dielectric layer and a lower surface of the light modulation structure adjacent to the sensing unit jointed panel,” as described in claim 60 and page 17 of the specification mailed on April 24, 2026, must be shown and labelled in the figures. Likewise, the first distance, second distance, and a difference between these two distances, as required by claim 74 and as discussed in the specification objections above, must be shown. These claimed features must be shown or the features are cancelled from the corresponding claims. No new matter should be entered.
Specifically in regards to the artifacts defined in claim 60, the specification calls out for a label “a” as the “distance between the lower surface of the light modulation structure 112 and the upper surface of the dielectric layer 120” and a label “b” as a length of a side of the light modulation structure, wherein a ≤ 2b. Please see page 17 of the specification. However, Fig. 1 does not show any labels for “a” or “b” or show the relationship that a ≤ 2b. For the purpose of compact prosecution, the examiner will treat “a” to be the thickness of the binding layer 113, which is in between the light modulation structure 112 and the dielectric layer 120 and will treat “b” to be any length of any side of the light modulation structure.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 74 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 74, the specification does not mention a difference between the first distance and the second distance is less than or equal to 10 µm. For example, page 18 of the specification mailed on April 24, 2026 writes “a difference in distances between any two regions in the lower surface of the light modulation structure 112 and the upper surface of the dielectric layer 120 is less than or equal to 10 μm.” This passage explains that the first and second distance each has a value of 10 μm and does not support difference of 10 µm between a first distance and a second distance.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 74 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As discussed above, claim 74 do not have support in the written description. The claims, as written, would not make sense to have a difference between the first distance and the second distance to be 10 µm. This is because, as described in page 18 of the specifications, each of the first distance and second distance has a value of 10 µm. See also the specifications objection above. Since the meaning of the claim is unclear, the claim does not have any metes and bounds as required by 35 USC 112 (b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 60, 66, 68-72, 74-77 and 79 are rejected under 35 U.S.C. 103 as being unpatentable over Cui ‘820 (CN 111505820 A; see English translation in FOR mailed on March 24, 2025) in view of Enquist (US 9,564,414 B2), and Kimura (US 2020/0103220 A1).
Regarding claim 60, Cui ‘820 teaches a method for manufacturing a spectrum chip (see Abstract), characterized by comprising:
forming an array of light modulation structures (5, see Fig. 2; 5 is part of layer 1 in Fig. 15) including at least two light modulation structures (Fig. 2 shows two or more 5) on a substrate (4, see Fig. 15 and Example 10 in Page 14 of English translation: “if using the transfer process scheme, the silicon dioxide can be used as the preparation substrate of the light modulation layer 1”) to obtain a modulation unit jointed panel (1&4, see Fig. 15 and Example ten in Page 14: “the prepared light modulation layer 1 and the light-transmitting layer 4 are transferred to the image sensing layer 2 as a whole”; alternatively, modulation unit jointed panel includes 1, 24, and 23 in Fig. 19);
providing a sensing unit jointed panel (2&3) which includes at least two sensing units (7, see Fig. 2);
coupling the modulation unit jointed panel to the sensing unit jointed panel to obtain a spectrum chip jointed panel (see the structure of Fig. 15).
Cui ‘820 further teaches using forming the sensing unit on a substrate ( Detailed description, Page 6, first paragraph: “image sensing layer 2 is a CIS wafer”) and forming the at least two light modulator structures on a substrate (Example 10 in Page 14 of English translation: “if using the transfer process scheme, the silicon dioxide can be used as the preparation substrate of the light modulation layer 1”), wherein a length of a side of the light modulation structure is between 60 nm to 1200 nm (see page 9 of English translation, second paragraph from the bottom of the page ). However, Cui ‘820 does not teach: forming a dielectric layer on the sensing unit jointed panel and coupling the modulation unit jointed panel to the dielectric layer, wherein for each light modulation structure of the at least two light modulation structures, a distance between an upper surface of the dielectric layer and a lower surface of the light modulation structure adjacent to the sensing unit jointed panel is less than a length of a side of the light modulation structure.
Enquist, in the same field of invention, teaches forming a dielectric layer (12; see Fig. 2 and Col. 6, Lns 44-48) between two substrates (10 and 16), wherein the thickness of the dielectric layer is between 0.5 nm -1.5 nm (Col. 6, Ln 54: 5-10 angstroms). Hence, Cui ‘520 in view of Enquist teach:
forming a dielectric layer (12) on the sensing unit jointed panel (substrate 10 is analogous to the sensing unit jointed panel) and coupling the modulation unit jointed panel to the dielectric layer (see Fig. 2 and Col. 7, Lns. 1-18),
wherein for each light modulation structure of the at least two light modulation structures, a distance (0.5 nm -1.5 nm; this is the thickness of the dielectric layer 17 formed on substrate 16; see Col. 7, Ln 5) between an upper surface (upper surface of 12) of the dielectric layer and a lower surface (lower surface of 16, which is analogous to the light modulation structure) of the light modulation structure adjacent to the sensing unit jointed panel is less than a length (Cui ‘820: 60 nm to 1200 nm) of a side (height/thickness of light modulation layer 1) of the light modulation structure.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Enquist into the device of Cui ’820 to form a dielectric layer on the sensing unit jointed panel and coupling the modulation unit jointed panel to the dielectric layer, wherein the distance between an upper surface of the dielectric layer is less than a length of a side of the light modulation structure. The ordinary artisan would have been motivated to modify Enquist in the manner set forth above for at least the purpose of using direct bonding method for bonding the substrates that contain the sensing unit jointed panel and the modulation unit jointed panel (see Enquist’s Abstract) for the further purpose of increasing the device density of integrated circuit devices (see Enquist’s Background of the Invention).
As mentioned above, Cui ‘820 further teaches using forming the sensing unit on a wafer ( Detailed description, Page 6, first paragraph: “image sensing layer 2 is a CIS wafer”) but does not teach: dividing the spectrum chip jointed panel to obtain at least two spectrum chips.
Kimura, in the same field of invention, teaches dividing a wafer (10) to obtain individual chips (¶ [0002]). Hence, Cui ’820 in view of Kimura teaches dividing the spectrum chip jointed panel to obtain at least two spectrum chips.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kimura into the method of Cui ‘820 to divide the spectrum chip jointed panel to obtain at least two spectrum chips. The ordinary artisan would have been motivated to modify Cui ‘820 in the manner set forth above for at least the purpose of optimizing the yield of the manufacturing process by building multiple spectrum chips on a wafer concurrently and then singulating each chip to obtain individual device chips from the wafer in order to be further packaged into stand-alone applications, such as, but not limited to, mobile phones or personal computers (Kimura ¶ [0002]).
Regarding claim 66, the method for manufacturing the spectrum chip according to claim 60, wherein the coupling of the modulation unit jointed panel to the sensing unit jointed panel includes:
coupling the modulation unit jointed panel to the sensing unit jointed panel in a flip-chip manner (Cui ‘820, Page 11: Example 5 and Fig. 11: back-illuminated structure; also Fig. 7 is flipped to obtain Fig. 11), wherein the two light modulation structures of the modulation unit jointed panel are overlaid on the sensing unit jointed panel (Cui ‘820 Page 11: “the light modulation layer 1 is directly integrated on the light detection layer 22”).
Regarding claim 68, the method for manufacturing the spectrum chip according to claim 66, wherein the coupling of the modulation unit jointed panel to the dielectric layer includes:
forming a binding layer (17: see Enquist Fig. 2) on the at least two light modulation structures (16 is analogous to the light modulation structures) of the modulation unit jointed panel; and
coupling the modulation unit jointed panel to the dielectric layer in a manner such that the binding layer is bound to the dielectric layer (Fig. 4; Col. 7 Lns 8-9:“[A] bond between surfaces 18 and 13 is formed”).
Regarding claim 69, the method for manufacturing the spectrum chip according to claim 60, wherein the coupling of the modulation unit jointed panel to the sensing unit jointed panel includes:
attaching the modulation unit joined panel to the sensing unit jointed panel by van der Waals forces (see Enquist Col. 7, Ln. 13) ; or
attaching the modulating unit jointed panel to the sensing unit jointed panel by an adhesive; or
attaching the modulation unit jointed panel to the sensing unit jointed panel by a bonding process.
Regarding claim 70, the method for manufacturing the spectrum chip according to claim 66, wherein for each light modulation structure of the at least two light modulation structures, the distance between the upper surface of the dielectric layer and the lower surface of the light modulation structure adjacent to the sensing unit jointed panel is less than or equal to 10 µm (Enquist Col. 6, Ln 54: 5-10 angstroms, which is 0.5 nm -1.5 nm).
Regarding claim 71, the method for manufacturing the spectrum chip according to claim 70, wherein for each light modulation structure of the at least two light modulation structures, the distance between the upper surface of the dielectric layer and the lower surface of the light modulation structure adjacent to the sensing unit jointed panel exceeds a preset threshold (Enquist Col. 6 Ln. 50-55 teaches a preset thickness of the dielectric films 11 and 17) by an amount less than or equal to 10% of the preset threshold (proportion between the distance between the upper surface of the dielectric layer and the lower surface of the light modulation structure, 1.5 nm, to the length of a side of the light modulation structure, 60 nm, is 2.5%; this is exceeds an amount that is less than 10%).
Regarding claim 72, the method for manufacturing the spectrum chip according to claim 71, wherein a difference in respective distances between the upper surface of the dielectric layer and respective corresponding positions on the lower surfaces of the at least two light modulation structures adjacent to the sensing unit jointed panel is less than 10 μm (Enquist Col. 6, Ln 52-55: 5-10 angstroms, which is 0.5 nm-1.5 nm).
Regarding claim 74, the method for manufacturing the spectrum chip according to claim 66, wherein a distance between a first region (Cui ‘820 Fig. 2: region between the leftmost and the rightmost point of the bottom surface of the leftmost 5) in the lower surface one of the light modulation structures adjacent to the sensing unit jointed panel and a first corresponding region (Cui ‘820 Fig. 2: region between the leftmost and the rightmost point of the top surface of the leftmost 7) in the upper surface of the dielectric layer is a first distance (Enquist teaches a dielectric layer in between 7 and 5, see claim 60 rejection above),
a distance between a second region (Cui ‘820 Fig. 2: region between the leftmost and the rightmost point of the bottom surface of the middle 5) in the lower surface of another of the at least two light modulation structures adjacent to the sensing unit jointed panel and a second corresponding region (Cui ‘820 Fig. 2: region between the leftmost and the rightmost point of the top surface of the middle 7) in the upper surface of the dielectric layer is a second distance, and
a difference between the first distance and the second distance is less than or equal to 10 μm (Enquist Col. 6, Ln 52-55: 5-10 angstroms, which is 0.5 nm-1.5 nm ; each of the first and second distance has this value; see also 35 USC § 112 rejection above).
Regarding claim 75, the method for manufacturing the spectrum chip according to claim 60, wherein each light modulation structure includes a modulation portion (1&6, see Cui ‘820 Figs. 3 & 19; note: 1 has modulation holes 6) and a non-modulation portion (23&24).
Regarding claim 76, the method for manufacturing the spectrum chip according to claim 75, wherein the modulation portion includes at least one light modulation unit (1 & 6 constitute the modulation panel 1 & 4 in claim 60 rejection; see also 35 USC § 112 rejection), and the non-modulation portion includes at least one filter unit (24, see Cui ‘820 Fig. 19).
Regarding claim 77, the method for manufacturing the spectrum chip according to claim 76, wherein the forming of the array of light modulation structures including the at least two light modulation structures (1 & 24 & 23, see Cui ‘820 Figs.3 & 19) on the substrate to obtain the modulation unit jointed panel includes:
forming a light modulation layer (1) on the substrate (4, see Fig. 15 and also 35 USC § 103 rejection of claim 60); and
forming the modulation portion (6, see Fig. 3) and the non-modulation portion (23&24, see Fig. 19) in the light modulation layer.
.
Regarding claim 79, teaches a spectrum chip (see Abstract of Cui ‘820) manufactured by the method for manufacturing the spectrum chip according to claim 60 (see 35 USC § rejection of claim 60 above).
Claims 61-65 are rejected under 35 U.S.C. 103 as being unpatentable over Cui ‘820 (CN 111505820 A; see English translation in FOR mailed on March 24, 2025) in view of Enquist (US 9,564,414 B2), and Kimura (US 2020/0103220 A1) as applied to claim 60 above, and further in view of Cui ‘060 (CN 111490060 A; see English translation in FOR mailed on August 11, 2023).
Regarding claim 61, Cui ‘820 et al. teach the method for manufacturing the spectrum chip according to claim 60 but do not teach: wherein the at least two light modulation structures include a first light modulation structure and a second light modulation structure,
and the forming the array of light modulation structures including the at least two light modulation structures on the substrate to obtain the modulation unit jointed panel includes:
forming a first light modulation layer on the substrate;
forming a second light modulation layer on the first light modulation structure.
Cui ‘820, in a different embodiment, teaches a method wherein the at least two light modulation structures includes a first light modulation structure (102 and through-holes 6, see Cui ‘820 Figs. 8-10) and a second light modulation structure (101 and through-holes 6);
and the forming the array of light modulation structures including the at least two light modulation structures on the substrate to obtain the modulation unit jointed panel includes:
forming a first light modulation layer (102) on the substrate (in view of Cui’ 820 Fig. 15, 102 is formed on substrate 4);
forming a second light modulation layer (101) on the first light modulation structure (as shown in Figs. 8-9, 101 is formed on top of 102).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of a different embodiment of Cui ‘820 into the method of Cui ‘820 et al. to include a first light modulation layer and a second light modulation layer in the at least one light modulation structure, with the first light modulation layer formed on the substrate and the second light modulation layer formed on the first light modulation layer. The ordinary artisan would have been motivated to modify Cui ‘820 et al. in the manner set forth above for at least the purpose of increasing the modulation capability of the light modulation structure, thus improving the precision and frequency spectrum of the spectrum chip (Cui ‘820: Page 3, Beneficial effects 2)
Cui ‘820 further teaches modulation holes (6) in the first light modulation layer and the second light modulation layer (see Page 10: Example 2). However, Cui ‘820 et al. do not teach:
etching or nano-imprinting the first light modulation layer to form the first light modulation structure; and
etching or nano-imprinting the second light modulation layer to form the second light modulation structure.
Cui ‘060, in the same field of invention, teaches a method comprising etching the light modulation layer to obtain modulation holes (Page 8 of English translation: “Fourth, as shown in Fig. 12, the polarization-independent light modulation layer 110 is prepared by directly etching… The modulation hole array of the light modulation layer 110 may be [obtained by using] one or any combination of the above two solutions”). Hence, Cui ‘820 et al. in view of Cui ‘060 teaches:
etching or nano-imprinting the first light modulation layer to form the first light modulation structure; and
etching or nano-imprinting the second light modulation layer to form the second light modulation structure.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Cui ‘060 into the method of Cui ’820 et al. to etch the first light modulation layer and the second light modulation layer to form the first and second light modulation layers, respectively. The ordinary artisan would have been motivated to modify Cui ‘820 et al. in the manner set forth above for at least the purpose of using any of the multiple methods known in the art for forming through-holes in semiconductor layers.
Regarding claim 62, Cui ‘820 et al. teach the method for manufacturing the spectrum chip according to claim 60, wherein the at least two light modulation structures include a first light modulation structure (Cui’ 820 Fig. 2 shows two or more of 5);
and the forming of the array of light modulation structures including the at least two light modulation structures on the substrate to obtain the modulation unit jointed panel includes:
forming a first light modulation layer on the substrate (Fig. 2 shows two or more 5 formed on substrate 4; Cui’ 820 Fig. 15: layer 1 is the layer in which 5 is formed; see 35 USC § 103 of claim 60 rejection and 35 USC § 112 rejection).
Cui ‘820 further teaches forming modulation holes (6) in the first light modulation layer (see Page 10: Example 2). However, Cui ‘820 et al. do not teach:
etching or nano-imprinting the first light modulation layer to form the first light modulation structure.
Cui ‘060, in the same field of invention, teaches a method comprising etching the light modulation layer to obtain modulation holes (Page 8: “Fourth, as shown in Fig. 12, the polarization-independent light modulation layer 110 is prepared by directly etching… The modulation hole array of the light modulation layer 110 may be [obtained by using] one or any combination of the above two solutions”). Hence, Cui ‘820 in view of Kimura and Cui ‘060 teaches: etching or nano-imprinting the first light modulation layer to form the first light modulation structure.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Cui ‘060 into the method of Cui ’820 et al. to etch the first light modulation layer to form the first and second light modulation layers. The ordinary artisan would have been motivated to modify Cui ‘820 et al. in the manner set forth above for at least the purpose of using any of the multiple methods known in the art for forming through-holes of semiconductor layers.
Regarding claim 63, the method for manufacturing the spectrum chip according to claim 61, wherein the forming of the first light modulation layer on the substrate includes:
depositing the first light modulation layer on the substrate by a deposition process (Cui ‘820, Example 10 in Page 14 of English translation: “if a direction deposition and growth is adopted when preparing the light modulation layer 1…by chemical vapor deposition”)
Regarding claim 64, the method for manufacturing the spectrum chip according to claim 61, wherein the forming of the first light modulation layer on the substrate includes:
providing the first light modulation layer (102, see Cui ‘820 Fig. 8); and
overlaying the first light modulation layer on the substrate (4, see Cui ‘Fig. 15 and 35 USC § 103 rejection of claim 60 above).
Regarding claim 65, the method for manufacturing the spectrum chip according to claim 61, wherein the forming of the second light modulation layer on the first light modulation structure includes:
forming a connection layer (102, see Cui ‘820 Fig. 10) on the first light modulation layer; and
forming the second light modulation layer on the connection layer (Fig. 10 shows 101 on top of 102).
Claims 80-84 are rejected under 35 U.S.C. 103 as being unpatentable over Cui ‘820 (CN 111505820 A; see English translation in FOR mailed on March 24, 2025) in view of Enquist (US 9,564,414 B2), and Kimura (US 2020/0103220 A1) as applied to claim 60 above, and further in view of Chen (US 2019/0393362 A1).
Regarding claim 80, Cui ‘820 et al. teach spectrum chip according to claim 79, and further teach: wherein the modulation unit jointed panel and the sensing unit jointed panel are bound with each other by a van der Waals force (Enquist Col.7, Ln. 13). However, Cui ‘820 et al. do not teach: under the action of an encapsulation body.
Chen, in the same field of invention, teaches a device with an encapsulation body (50, see Figs. 8-9 and 12).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chen into the device of Cui ‘820 et al. to provide an encapsulating body around the modulation unit jointed panel and the sensing unit jointed panel, hence, binding these two structures under the action of the encapsulation body. The ordinary artisan would have been motivated to modify Chen in the manner set forth above for at least the purpose of using the encapsulating body as part of a package body that provides mechanical protection to the spectrum device (110; see Chen ¶ [0021] ) and to prevent peripheral light from entering into the light-sensitive areas of the spectrum chip, so that only direct light can be captured by the sensors (Chen ¶ [0027]: 50 is completely opaque).
Regarding claim 81, Cui ‘820 et al. teach a spectrum analysis device (Cui ‘820 Abstract), comprising:
a spectrum chip manufactured by the method for manufacturing the spectrum chip according to claim 60 (see 35 USC § 103 rejection of claim 60 above).
However, Cui ‘820 in view of Kimura does not teach the device comprising:
a circuit board,
wherein the spectrum chip is electrically connected to the circuit board.
Chen, in the same field of invention, teaches a device (Fig. 7) comprising:
a circuit board (10),
wherein the spectrum chip (20; Cui ‘820 in view of Kimura and Chen teaches 20 to be the spectrum chip of Cui ‘820) is electrically connected to the circuit board.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chen into the device of Cui ‘820 et al. to provide a circuit board, wherein the spectrum chip is connected to the circuit board.
The ordinary artisan would have been motivated to modify Cui ‘820 et al. in the manner set forth above for at least the purpose of using the circuit board as means to electrically connect (through wires 25) the spectrum chip with other components (12, see Chen Fig. 7) and connectors (14) that comprises the entire device (see also Chen ¶ [0023]).
Regarding claim 82, the spectrum analysis device according to claim 81, further comprising: an optical module (50 or alternatively, 50 & 60, see Chen Figs. 9-10 and 12 and ¶ [0027]) held on a photosensitive path (light enters through lens 62) of the spectrum chip (20).
Regarding claim 83, the spectrum analysis device according to claim 81, further including an encapsulation body (50, see Chen Figs. 9-10 and 12) disposed on the circuit board, wherein the encapsulation body is integrally formed on the circuit board (Figs. 9-10 and 12 shows 50 disposed and formed on 10) and covers at least a part (portions of 20 directly contacting 50) of an outer surface (upper surface and sidewalls of 20) of the spectrum chip.
Regarding claim 84, the spectrum analysis device according to claim 83, wherein the encapsulation body is made of an opaque material (Chen ¶ [0027]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Huang (CN 212363424) teaches some aspects of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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