DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/02/2026 has been entered.
Response to Amendment
The Amendment filed on 09/02/2026 has been entered. Claims 1-13 and newly added claim 15 remain pending in the application. Applicant’s amendments have overcome the 112(b) rejection of claim 8 as previously set forth in the Final Office Action mailed on 06/03/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over by Fong et al., (United States Patent Application Publication Number, US 2018/0350785 A1), hereinafter referenced as Fong, in view of Hsu et al., (United States Patent Application Publication Number, US 2011/0031633 A1) hereinafter referenced as Hsu.
Regarding claim 1, Fong teaches a three-dimensional integrated circuit module, comprising a semiconductor structure (structure show in Fig.20) and a first passivation layer on the semiconductor structure (Fig.20, uppermost layer is a oxide layer), the semiconductor structure comprising at least two substrates arranged in sequence from bottom to top (Fig.20, bottom substrate comprises of lower device transistor and interconnect layers and bottom CVD oxide layer, top substrate comprises the entire structure on top of the bottom substrate), the substrates electrically interconnected (Fig.20, the top bond pads of the bottom substrate are electrically connected to the bottom bond pads of the top substrate), the semiconductor structure comprising at least one conductive hole located in a topmost one of the substrates and configured for connection with an internal specified metal layer (Fig.20, inter-layer metal connections), wherein in the topmost substrate in the semiconductor structure, a trench arranged to avoid the conductive hole is also formed (Fig.20, coolant flow channels), and the first passivation layer spans over and covers the trench to define a heat exchange channel (Fig.20, uppermost layer spans over and covers the trench and defines the channel)
Fong teaches wherein the three-dimensional integrated circuit module further comprises a surface cap layer, wherein the surface cap layer covers inner surfaces of the trench (Fig.20, the inner surfaces of the trench are covered by a surface cap layer, which is an oxide paragraph [0158], rows 1-4). Fong teaches the contact hole that crosses the second substrate (Fig.20, inter-layer metal connections), and the second substrate is made of silicon (paragraph [0039], rows 7-8). For Fong’s invention to function, a dielectric layer that covers the inner surfaces of the contact hole is needed in order to electrically isolate the inter-layer metal connections from the silicon substrate (in order to prevent electrical shorts), and, since the electrical connections are made through the bottom of the contact hole, the bottom surface of the contact hole needs to expose and directly contact the internal specified metal layer. Fong does not teach that the dielectric layer covering the inner surfaces of the contact hole is the same as the surface cap layer covering the inner surfaces of the trench. Hsu teaches the dielectric layer covering the inner surfaces of the contact hole is made of the same material as the surface cap layer covering the inner surfaces of the trench (Fig.11, element #303 covers the inner surfaces of contact holes, and element #301 covers the inner surfaces of the trench /channel used for cooling, and are both made of oxide, paragraph [0034], rows 2-9 and therefore cannot be distinguish from one another). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hsu and disclose a cap layer covering the inner surfaces of the trench and the contact hole. As disclosed by Hsu, the surface cap layer electrically isolates the contact hole from the substrate, while allowing electrical contact with the metal layers through the bottom of the hole. Having the same layer covering the inner surfaces of the contact hole and the trench, instead of separate layers made of different materials, simplifies the manufacturing process since it may involve a single deposition process.
Fong further teaches wherein the topmost substrate comprises a substrate layer (Fig.20, layer above the transfer device interconnect layers) and the substrate layer has a thickness of about 1um to 50um (Fig.20, topmost substrate is a transferred substrate, paragraph [0275], rows 1-3, see also Fig.2 and 2A and paragraph [0015]. In Fig.2A, the substrate layer thickness is equal to the distance between the location of the H profile and the bottom of the metal interconnect layers. This thickness is between 2um and 10um according to paragraph [0043], rows 1-5 and paragraph [0098], rows 1-3). The claimed range overlaps the range disclosed by Fong and therefore a prima facie case of obviousness exists (MPEP 2144.05). Note that the limitation “the substrate layer of the topmost substrate is thinned” is treated as a product by process limitation and as such only the structure is required to meet the limitation (MPEP 2113).
Regarding claim 3, the combination of Fong and Hsu teaches the three-dimensional integrated circuit module of claim 1 as set forth in the obviousness rejection. Fong further teaches the three-dimensional integrated circuit module of claim 1, wherein the topmost substrate further comprises an interconnect layer underlying the substrate layer (Fig.20, transfer device interconnect layers), wherein the specified metal layer is arranged within the interconnect layer (Fig.20, top metal layer of the transfer device interconnect layers). In a different embodiment, Fong teaches the conductive hole extends through the substrate layer with a bottom surface located within the interconnect layer (Fig.23, the leftmost via, element #2206, extends through the substrate and has the bottom surface within the interconnect layer). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Fong and disclose wherein the conductive hole extends through the substrate layer with a bottom surface located within the interconnect layer. As disclosed by Fong, this provides an electrical connection between the device layers and the top surface of integrated circuit, which allows the attachment of other die components (Fig.24), as well as lateral wiring connections (paragraph [0292], rows 1-5 and paragraph [0293], rows 1-8).
Regarding claim 4, the combination of Fong and Hsu teaches the three-dimensional integrated circuit module of claims 1 and 3 as set forth in the obviousness rejection. Fong further teaches the three-dimensional integrated circuit module of claim 3, wherein a bottom surface of the heat exchange channel is located within the substrate layer (Fig.20, the bottom surface of the heat exchange channel is located within the substrate layer).
Regarding claim 5, the combination of Fong and Hsu teaches the three-dimensional integrated circuit module of claim 1 as set forth in the obviousness rejection. Fong further teaches the three-dimensional integrated circuit module of claim 1, wherein the conductive hole comprises a pad metal layer, the pad metal layer extending from the inside of the contact hole over an upper surface of the first passivation layer (Fig.20, layer that forms the topmost bond pads, bottom surface of the pad is located over an upper surface of the passivation layer).
Regarding claim 13, the combination of Fong and Hsu teaches the three-dimensional integrated circuit module of claim 1 as set forth in the obviousness rejection. Fong further teaches the three-dimensional integrated circuit module of claim 1, wherein the surface cap layer does not fill up the trench (Fig.20, only inner surfaces of the trench are covered by a surface cap layer allowing the formation of a coolant flow channel in the trench).
Claims 2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Fong in view Hsu and in view of Bar et al., (United States Patent Application Publication Number, US 2016/0343638 A1) hereinafter referenced as Bar.
Regarding claim 2, the combination of Fong and Hsu teaches the three-dimensional integrated circuit module of claim 1 as set forth in the obviousness rejection. Fong further teaches a heat dissipation medium able to be introduced to the heat exchange channel (paragraph [0309], rows 1-2). The combination of Fong and Hsu does not teach the three-dimensional integrated circuit module of claim 1, wherein the heat exchange channel comprises at least one heat dissipation medium inlet and at least one heat dissipation medium outlet, a heat dissipation medium able to be introduced to the heat exchange channel through the heat dissipation medium inlet and discharged through the heat dissipation medium outlet, the heat dissipation medium inlet provided in a side face and/or an upper surface of the semiconductor structure, the heat dissipation medium outlet provided in a side face and/or the upper surface of the semiconductor structure. Bar teaches the heat exchange channel (Fig.10, element #4, paragraph [0044], rows 1-3) comprises at least one heat dissipation medium inlet and at least one heat dissipation medium outlet (Fig.10, elements #7, paragraph [0044], rows 1-3), a heat dissipation medium able to be introduced to the heat exchange channel through the heat dissipation medium inlet and discharged through the heat dissipation medium outlet (paragraph [0045], rows 1-2), the heat dissipation medium inlet provided in a side face and/or an upper surface of the semiconductor structure, the heat dissipation medium outlet provided in a side face and/or the upper surface of the semiconductor structure (Fig.10, rotated vertically by 180 degrees, the inlet and the outlet are located on the upper surface of the semiconductor structure). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Bar and disclose wherein the heat exchange channel comprises at least one heat dissipation medium inlet and at least one heat dissipation medium outlet, a heat dissipation medium able to be introduced to the heat exchange channel through the heat dissipation medium inlet and discharged through the heat dissipation medium outlet, the heat dissipation medium inlet provided in a side face and/or an upper surface of the semiconductor structure, the heat dissipation medium outlet provided in a side face and/or the upper surface of the semiconductor structure. As disclosed by Bar, the inlet, the outlet and the heat dissipation medium together result in a low cost microfluidic circuit compatible with existing CMOS processes (paragraph [0006], rows 3-4).
Regarding claim 6, the combination of Fong and Hsu teaches the three-dimensional integrated circuit module of claims 1 and 5 as set forth in the obviousness rejection. The combination of Fong and Hsu does not teach the three-dimensional integrated circuit module of claim 5, further comprising a second passivation layer on the first passivation layer, wherein a portion of the pad metal layer is defined by and exposed from the second passivation layer, the portion of the pad metal layer exposed from the second passivation layer serving as a pad. Bar teaches a second passivation layer on the first passivation layer (Fig.10, rotated vertically by 180 degrees, top two layers located on top of element #10) wherein a portion of the pad metal layer is defined by and exposed from the second passivation layer, the portion of the pad metal layer exposed from the second passivation layer serving as a pad (Fig.10, rotated vertically by 180 degrees, element #3 is exposed from layer element #5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Bar and disclose a second passivation layer on the first passivation layer, wherein a portion of the pad metal layer is defined by and exposed from the second passivation layer, the portion of the pad metal layer exposed from the second passivation layer serving as a pad. The second passivation layer provides increased protection of the substrate from environmental degradation, while exposing the pad from the passivation layer, allows the formation of electrical connections between the integrated circuit metal layer and external signal sources.
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Fong, in view of Hsu, Bar and in view of Tsutsui et al., (United States Patent Application Publication Number, US 2020/0402888 A1) hereinafter referenced as Tsutsui.
Regarding claim 7, the combination of Fong and Hsu teaches the three-dimensional integrated circuit module of claims 1 and 5 as set forth in the obviousness rejection, and the combination of Fong, Hsu and Bar teaches the three-dimensional integrated circuit module of claim 6 as set forth in the obviousness rejection. Fong further teaches the three-dimensional integrated circuit module of claim 6, wherein the upper surface of the semiconductor structure comprises a heat exchange region for accommodating the heat exchange channel and a plurality of electrical connection regions for accommodating a set of conductive holes and pads (Fig.20, the region of the upper surface located on top of the heat exchange channels is the heat exchange region, and the regions of the upper surface where the topmost pads are located are the electrical connection regions).
The combination of Fong, Hsu and Bar does not teach wherein the heat exchange region interlaces with the plurality of electrical connection regions. Tsutsui teaches wherein the heat exchange region interlaces with the plurality of electrical connection regions (Fig.7, the region of the upper surface located on top of the heat exchange channels is the heat exchange region and the regions of the upper surface located on top of the electrical connections, element #330, are the electrical connection regions, paragraph [0149], rows 13-22). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Tsutsui and disclose wherein the heat exchange region interlaces with the plurality of electrical connection regions. Having the heat exchange region interlaced with the plurality of electrical connection regions results in a large cooling area therefore resulting in an increased heat dissipation. Furthermore, this allows the placements of the cooling channels close to the connections and therefore, close to the heat generation spots, further helping with heat removal from the integrated circuit.
Regarding claim 15, the combination of Fong and Hsu teaches the three-dimensional integrated circuit module of claims 1 and 5 as set forth in the obviousness rejection, and the combination of Fong, Hsu and Bar teaches the three-dimensional integrated circuit module of claim 6 as set forth in the obviousness rejection. Fong further teaches the three-dimensional integrated circuit module of claim 6, wherein the upper surface of the semiconductor structure comprises a heat exchange region for accommodating the heat exchange channel (Fig.20, the region of the upper surface located on top of the left heat exchange channel is a heat exchange region) and a plurality of electrical connection regions for accommodating a set of conductive holes and pads (Fig.20, the regions of the upper surface where the topmost pads are located are the electrical connection regions).The combination of Fong, Hsu and Bar does not teach wherein the electrical connection regions are all disposed around the heat exchange region. Tsutsui teaches a heat exchange region for accommodating the heat exchange channel (Fig.7, the region of the upper surface located on top of the third vertical heat exchange channel from the left side of the image) and a plurality of electrical connection regions for accommodating a set of conductive holes and pads (Fig.7, first and second column of elements #330 from the left side of the image), wherein the electrical connection regions are all disposed around the heat exchange region (Fig.7, elements #330 are disposed around the heat exchange region as defined above).It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Tsutsui and disclose wherein the electrical connection regions are all disposed around the heat exchange region. Having the electrical connection regions disposed around the heat exchange region results in the placement of the electrical connections regions close to the cooling channel helping with heat removal from the integrated circuit.
Allowable Subject Matter
Claim 8 is allowed. Claims 9-10, 12 and 14 are allowed as being dependent on claim 8.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 8, the cited prior art does not teach or fairly suggests, along with other claimed features: “and the first passivation layer being formed in an upper opening region of the contact hole overlapping the upper surface of the topmost substrate”, “removing the first passivation layer above and within from the upper opening region of the contact hole” and removing at least a portion of the surface cap layer from a bottom surface of the contact hole”.
Sunohara et al., (United States Patent Application Publication Number, US 2008/0150109 A1) teaches the passivation layer is formed on the upper surface of the substrate but not in an upper opening region of the contact hole (Fig.3E, element #205 is not formed in an upper opening of element #202). Also, the surface cap layer (Fig.3E, element #203) is not formed on at least a portion of a bottom surface of the contact hole.
Response to Arguments
Applicant’s arguments filed on 09/02/2026 have been fully considered but they
are not persuasive.
In the Applicant Arguments/ Remarks document filed on 09/02/2026, Applicant argues: “Fong discloses a three-dimensional integrated circuit module utilizing a cleaving process to transfer a device layer. However, Fong does not disclose thinning the topmost substrate layer to a thickness of about 1 um to 50 um. In Fong, the "transferred substrate" (the layer remaining after cleaving) inherently retains a significant thickness to maintain mechanical integrity during subsequent processing steps. Fong's cleave plane is typically positioned 5-10 um or more from the device layer to avoid damaging active devices, resulting in a residual substrate thickness far exceeding 50 pm”.
Claim 1 is a product claim and therefore only the structure of the product is required to meet the limitation of the claim (MPEP 2113). The limitation “the substrate layer of the topmost substrate is thinned” is treated as a product by process limitation in the above rejection of claim 1. Fong's cleave plane is positioned 5-10 um inside the silicon substrate (paragraph [0098], rows 1-3 and paragraph [0043], rows 1-5). The implant used to define the cleave plane is performed through the dielectric and circuit layers of the substrate (Fig.2A the dielectric and the circuit layers are the metal interconnect layers, paragraph [0008]) and therefore the distance of 5-10um is between the metal interconnect layers and the cleave surface (Fig.2A). The transferred substrate is the part of the substrate that includes the dielectric and the circuit layers and therefore the transferred substrate has a thickness of less than 10um. The topmost substrate of Fig.20 is a transferred substrate. Furthermore, Fong’s coolant flow channels are formed in the transferred substrate (Fig.2 and 2A, the region above the H profile is the transferred substrate), which as noted above has the thickness inside the claimed range.
Applicant’s arguments with respect to Gambino are moot since Gambino is not used as in the above rejection of the claims.
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
