DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 03/17/2026 has been entered. Claims 1-10, 12 and newly added claims 13 and 14, remain pending in the application. Claim 11 has been canceled.
Specification
The specification has been amended by the applicant to correctly number the paragraphs as defined in 37 CFR 1.52(6). Therefore, the previous objection to the specification is withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, the claim recites the limitation “removing the first passivation layer above and within the contact hole causing exposure of the specified metal layer”. The method recited in claim 8 does not require the first passivation layer to be formed above and within the contact hole, therefore the method may not need the step of removing it from these areas.
For the reason of examination, claim 8 will be interpreted as: A method of fabricating a three-dimensional integrated circuit module, comprising: providing a semiconductor structure, the semiconductor structure comprising at least two substrates arranged in sequence from bottom to top, the substrates electrically interconnected; performing a downward etching process on a topmost one of the substrates to form at least one contact hole and a trench, which are both open upwardly, the trench arranged to avoid the contact hole, the contact hole configured to establish an electrical connection with a specified metal layer within the semiconductor structure, the trench configured to provide a heat exchange channel, wherein a depth of the contact hole is controlled so that the specified metal layer is exposed or not; forming a first passivation layer on the semiconductor structure, which covers an upper surface of the topmost substrate and spans over and covers the trench, the first passivation layer covering the trench to define the heat exchange channel and being formed above and within the contact hole; removing the first passivation layer above and within the contact hole and causing exposure of the specified metal layer through the contact hole; and forming a pad metal layer on the semiconductor structure, a portion of the pad metal layer in the contact hole is electrically connected to the specified metal layer, thereby forming a conductive hole; after the contact hole and the trench are formed and before the first passivation layer is formed, the method further comprising: conformally forming a surface cap layer over the semiconductor structure, which covers inner surfaces of the contact hole and the trench, wherein after the first passivation layer is etched and before the pad metal layer is formed, the surface cap layer on a bottom surface of the contact hole is at least partially removed, thereby causing the exposure of the specified metal layer through the contact hole.
Claims 9-12 and 14 are being rejected as being dependent on claim 8.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over by Fong et al., (United States Patent Application Publication Number, US 2018/0350785 A1), hereinafter referenced as Fong, in view of Gambino et al., (United States Patent Application Publication Number, US 2018/0219038 A1) hereinafter referenced as Gambino.
Regarding claim 1, Fong teaches a three-dimensional integrated circuit module, comprising a semiconductor structure (structure show in Fig.20) and a first passivation layer on the semiconductor structure (Fig.20, uppermost layer is a oxide layer), the semiconductor structure comprising at least two substrates arranged in sequence from bottom to top (Fig.20, bottom substrate comprises of lower device transistor and interconnect layers and bottom CVD oxide layer, top substrate comprises the entire structure on top of the bottom substrate), the substrates electrically interconnected (Fig.20, the top bond pads of the bottom substrate are electrically connected to the bottom bond pads of the top substrate), the semiconductor structure comprising at least one conductive hole located in a topmost one of the substrates and configured for connection with an internal specified metal layer (Fig.20, inter-layer metal connections), wherein in the topmost substrate in the semiconductor structure, a trench arranged to avoid the conductive hole is also formed (Fig.20, coolant flow channels), and the first passivation layer spans over and covers the trench to define a heat exchange channel (Fig.20, uppermost layer spans over and covers the trench and defines the channel)
Fong teaches wherein the three-dimensional integrated circuit module further comprises a surface cap layer, wherein the surface cap layer covers inner surfaces of the trench (Fig.20, the inner surfaces of the trench are covered by a surface cap layer). Fong does not directly teach wherein the surface cap layer covers inner surfaces of the contact hole, wherein a bottom surface of the contact hole exposes the specified metal layer through the contact hole. However, Fong teaches the contact hole (Fig.20, inter-layer metal connections), crosses the second substrate, and the second substrate is made of silicon [paragraph [0039], rows 7-8). For Fong’s invention to function, a dielectric layer (similar to the one that covers the inner surfaces of the trench) that covers the inner surfaces of the contact hole is needed in order to isolate the metal connections from the silicon substrate (prevent shorts), and, since the metal connection is made through the bottom of the contact hole, the bottom surface of the contact hole needs to expose the specified metal layer through the contact hole. Nevertheless, Gambino teaches wherein the three-dimensional integrated circuit module (Fig.1, whole structure) further comprises a surface cap layer over the semiconductor structure (Fig.1, layer formed elements #24 and #22 are made of same material, therefore, are indistinguishable from a single layer, paragraph [0038], rows 20-25), wherein the surface cap layer covers inner surfaces of the contact hole and the trench, (Fig.1, element #24 and #22 cover the inner surfaces of both the trench, element #18 and the contact hole, which is the opening located to the left side of the trench), wherein a bottom surface of the contact hole exposes the specified metal layer through the contact hole (Fig.1, element #24 and #22 are missing on the bottom of the contact hole and expose the metal layer below the hole). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Gambino and disclose wherein the three-dimensional integrated circuit module further comprises a surface cap layer over the semiconductor structure, wherein the surface cap layer covers inner surfaces of the contact hole and the trench, wherein a bottom surface of the contact hole exposes the specified metal layer through the contact hole. The surface cap layer is a dielectric layer (paragraph [0038], rows 20-25) that electrically isolates the contact hole from the substrate, while allowing electrical contact with the metal layers through the bottom of the hole.
Regarding claim 3, the combination of Fong and Gambino teaches the three-dimensional integrated circuit module of claim 1 as set forth in the obviousness rejection. Fong further teaches the three-dimensional integrated circuit module of claim 1, wherein the topmost substrate comprises a substrate layer and an interconnect layer underlying the substrate layer (Fig.20, layer between the top passivation layer and the transfer device transistor layers), wherein the specified metal layer is arranged within the interconnect layer (Fig.20, bottom metal layer of the transfer device transistor layers). In a different embodiment, Fong teaches the conductive hole extends through the substrate layer with a bottom surface located within the interconnect layer (Fig.23, the leftmost via, element #2206, extends through the substrate and has the bottom surface within the interconnect layer). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Fong and disclose wherein the conductive hole extends through the substrate layer with a bottom surface located within the interconnect layer. As disclosed by Fong, this provides an electrical connection between the device layers and the top surface of integrated circuit, which allows the attachment of other die components (Fig.24), as well as lateral wiring connections (paragraph [0292], rows 1-5 and paragraph [0293], rows 1-8).
Regarding claim 4, the combination of Fong and Gambino teaches the three-dimensional integrated circuit module of claims 1 and 3 as set forth in the obviousness rejection. Fong further teaches the three-dimensional integrated circuit module of claim 3, wherein a bottom surface of the heat exchange channel is located within the substrate layer (Fig.20, the bottom surface of the heat exchange channel is within the substrate layer).
Regarding claim 5, the combination of Fong and Gambino teaches the three-dimensional integrated circuit module of claim 1 as set forth in the obviousness rejection. Fong further teaches the three-dimensional integrated circuit module of claim 1, wherein the conductive hole comprises a pad metal layer, the pad metal layer extending from the inside of the contact hole over an upper surface of the first passivation layer (Fig.20, layer that forms the topmost bond pads, bottom surface of the pad is located over an upper surface of the passivation layer).
Regarding claim 13, the combination of Fong and Gambino teaches the three-dimensional integrated circuit module of claim 1 as set forth in the obviousness rejection. Fong further teaches the three-dimensional integrated circuit module of claim 1, wherein the surface cap layer does not fill up the trench (Fig.20, only inner surfaces of the trench are covered by a surface cap layer allowing the formation of a coolant flow channel in the trench).
Claims 2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Fong in view Gambino and in view of Bar et al., (United States Patent Application Publication Number, US 2016/0343638 A1) hereinafter referenced as Bar.
Regarding claim 2, the combination of Fong and Gambino teaches the three-dimensional integrated circuit module of claim 1 as set forth in the obviousness rejection. Fong further teaches a heat dissipation medium able to be introduced to the heat exchange channel (paragraph [0309], rows 1-2). The combination of Fong and Gambino does not teach the three-dimensional integrated circuit module of claim 1, wherein the heat exchange channel comprises at least one heat dissipation medium inlet and at least one heat dissipation medium outlet, a heat dissipation medium able to be introduced to the heat exchange channel through the heat dissipation medium inlet and discharged through the heat dissipation medium outlet, the heat dissipation medium inlet provided in a side face and/or an upper surface of the semiconductor structure, the heat dissipation medium outlet provided in a side face and/or the upper surface of the semiconductor structure. Bar teaches the heat exchange channel (Fig.10, element #4, paragraph [0044], rows 1-3) comprises at least one heat dissipation medium inlet and at least one heat dissipation medium outlet (Fig.10, elements #7, paragraph [0044], rows 1-3), a heat dissipation medium able to be introduced to the heat exchange channel through the heat dissipation medium inlet and discharged through the heat dissipation medium outlet (paragraph [0045], rows 1-2), the heat dissipation medium inlet provided in a side face and/or an upper surface of the semiconductor structure, the heat dissipation medium outlet provided in a side face and/or the upper surface of the semiconductor structure (Fig.10, rotated vertically by 180 degrees, the inlet and the outlet are located on the upper surface of the semiconductor structure). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Bar and disclose wherein the heat exchange channel comprises at least one heat dissipation medium inlet and at least one heat dissipation medium outlet, a heat dissipation medium able to be introduced to the heat exchange channel through the heat dissipation medium inlet and discharged through the heat dissipation medium outlet, the heat dissipation medium inlet provided in a side face and/or an upper surface of the semiconductor structure, the heat dissipation medium outlet provided in a side face and/or the upper surface of the semiconductor structure. As disclosed by Bar, the inlet, the outlet and the heat dissipation medium together result in a low cost microfluidic circuit compatible with existing CMOS processes (paragraph [0006], rows 3-4).
Regarding claim 6, the combination of Fong and Gambino teaches the three-dimensional integrated circuit module of claims 1 and 5 as set forth in the obviousness rejection. The combination of Fong and Gambino does not teach the three-dimensional integrated circuit module of claim 5, further comprising a second passivation layer on the first passivation layer, wherein a portion of the pad metal layer is defined by and exposed from the second passivation layer, the portion of the pad metal layer exposed from the second passivation layer serving as a pad. Bar teaches a second passivation layer on the first passivation layer (Fig.10, rotated vertically by 180 degrees, top two layers located on top of element #10) wherein a portion of the pad metal layer is defined by and exposed from the second passivation layer, the portion of the pad metal layer exposed from the second passivation layer serving as a pad (Fig.10, rotated vertically by 180 degrees, element #3 is exposed from layer element #5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Bar and disclose a second passivation layer on the first passivation layer, wherein a portion of the pad metal layer is defined by and exposed from the second passivation layer, the portion of the pad metal layer exposed from the second passivation layer serving as a pad. The second passivation layer provides increased protection of the substrate from environmental degradation, while exposing the pad from the passivation layer, allows the formation of electrical connections between the integrated circuit metal layer and external signal sources.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Fong, in view of Gambino, Bar and in view of Tsutsui et al., (United States Patent Application Publication Number, US 2020/0402888 A1) hereinafter referenced as Tsutsui.
Regarding claim 7, the combination of Fong and Gambino teaches the three-dimensional integrated circuit module of claims 1 and 5 as set forth in the obviousness rejection, and the combination of Fong, Gambino and Bar teaches the three-dimensional integrated circuit module of claim 6 as set forth in the obviousness rejection. Fong further teaches the three-dimensional integrated circuit module of claim 6, wherein the upper surface of the semiconductor structure comprises a heat exchange region for accommodating the heat exchange channel and a plurality of electrical connection regions for accommodating a set of conductive holes and pads (Fig.20, the region of the upper surface located on top of the heat exchange channels is the heat exchange region and the regions of the upper surface where the topmost pads are located are the electrical connection regions).
The combination of Fong, Gambino and Bar does not teach wherein the heat exchange region interlaces with the plurality of electrical connection regions, or the electrical connection regions are all disposed around the heat exchange region. Tsutsui teaches wherein the heat exchange region interlaces with the plurality of electrical connection regions (Fig.7, the region of the upper surface located on top of the heat exchange channels is the heat exchange region and the regions of the upper surface located on top of the electrical connections, element #330 are located are the electrical connection regions, paragraph [0149], rows 13-22). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Tsutsui and disclose wherein the heat exchange region interlaces with the plurality of electrical connection regions. Having the heat exchange region interlaced with the plurality of electrical connection regions results in a large cooling area therefore resulting in an increased heat dissipation. Furthermore, this allows the placements of the cooling channels close to the connections and therefore, close to the heat generation spots, further helping with heat removal from the integrated circuit.
Allowable Subject Matter
Claim 8 is allowed if the 112b rejection is overcome through amendments, such as the one proposed in this office action. Claims 9-12 and 14 will be allowed as being dependent on claim 8, if the 112b rejection of claim 8 is overcome.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 8, the cited prior art does not teach or fairly suggests, along with other claimed features: “after the first passivation layer is etched and before the pad metal layer is formed, the surface cap layer on a bottom surface of the contact hole is at least partially removed thereby causing the exposure of the specified metal layer through the contact hole”.
Sunohara et al., (United States Patent Application Publication Number, US 2008/0150109 A1) teaches after the contact hole and the trench are formed and before the first passivation layer is formed, the method further comprising: conformally forming a surface cap layer over the semiconductor structure, which covers inner surfaces of the contact hole and the trench but does not fill up the trench (Fig.3E, element #203 is formed after the contact hole, element #201 and the trench, element #204 are formed). However, Sunohara does not teach, “wherein after the first passivation layer is etched and before the pad metal layer is formed, the surface cap layer on a bottom surface of the contact hole is at least partially removed, thereby causing the exposure of the specified metal layer through the contact hole”.
Response to Arguments
Applicant’s arguments filed on 03/17/2026 have been fully considered but they
are not persuasive.
The 112b rejection of claim 8 is maintained since the amended claim 8 still specifies the removal of the non-existent first passivation layer from above and within the contact hole.
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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