Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election, without traverse, of Group I (Figs. 1-5), claims 1-2, 4-8 and 10-16 in the reply filed on November 05th, 2025 is acknowledged. Non-elected invention and species, claims 3 and 9 have been cancelled. Claims 1, 4, 7 and 10 have been amended. Claims 1-2, 4-8 and 10-16 are pending.
Action on merits of Group I, claims 1-2, 4-8 and 10-16 as follows.
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on August 03rd, 2023; August 30th, 2023; and December 20th, 2023, have been considered by the examiner.
Drawings
The drawings filed on 08/03/2023 are acceptable.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-2, 4, 7-8, 10 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Katsui (JP 2020/183971, hereinafter as Kats ‘971) in view of Mazhari (US 2015/0262531, hereinafter as Mazh ‘531).
Regarding Claim 1, Kats ‘971 teaches a manufacturing method of a display comprising a vertical organic light-emitting transistor, the method comprising:
forming a gate electrode layer (Fig. 5, (20g); [0044]) of the vertical organic light-emitting transistor (20; [0044]) and one of current-carrying electrode layers (21d; [0046]) of a thin-film transistor (21; [0046]) connected to the gate electrode layer of the vertical organic light-emitting transistor, wherein the source electrode layer (20s; [0044]) of the vertical organic light-emitting transistor is formed after a surface layer (31; [0044]) serving as a base is formed, by forming a thin film or a percolating network of a conductive material on a main surface of the surface layer (31) (see para. [0044]).
Thus, Kats ‘971 is shown to teach all the features of the claim with the exception of explicitly the limitations: “forming integrally on a same layer of a gate electrode layer and the current-carrying electrode layer”.
Mazh ‘531 teaches forming integrally on a same layer of a cathode electrode layer (Fig. 2, (112); [0018]) of the OLED (110) and the current-carrying electrode layer of a thin-film transistor (120; [0018]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kats ‘971 by forming integrally on a same layer of a gate electrode layer and the current-carrying electrode layer for the purpose of reducing the process steps (see para. [0017]) as suggested by Mazh ‘531.
Regarding Claim 7, Kats ‘971 teaches a display comprising:
a vertical organic light-emitting transistor Fig. 5, (20); [0044]); and
a thin-film transistor (Fig. 5, (21); [0046]) in which one of current-carrying electrode layers (21d; [0046]) is connected to a gate electrode layer (20g; [0044]) of the vertical organic light-emitting transistor, wherein the gate electrode layer of the vertical organic light-emitting transistor and the one of the current-carrying electrode layer of the thin-film transistor connected to the gate electrode layer of the vertical organic light-emitting transistor and the source electrode layer (20s; [0044]) of the vertical organic light-emitting transistor (20) is made of a conductive material and formed on a main surface of a surface layer (31; [0044) serving as a base.
Thus, Kats ‘971 is shown to teach all the features of the claim with the exception of explicitly the limitations: “the gate electrode layer and the current-carrying electrode layers are formed integrally on a same layer”.
Mazh ‘531 teaches a cathode electrode layer (Fig. 2, (112); [0018]) of the OLED (110) and the current-carrying electrode layer of a thin-film transistor (120; [0018]) are formed integrally on a same layer.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kats ‘971 by forming integrally on a same layer of a gate electrode layer and the current-carrying electrode layer for the purpose of reducing the process steps (see para. [0017]) as suggested by Mazh ‘531.
Product by process limitation:
The expression “are formed integrally on a same layer” is/are taken to be a product by process limitation and is given no patentable weight. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
PNG
media_image1.png
273
444
media_image1.png
Greyscale
Regarding Claims 2 and 8, Kats ‘971 teaches the vertical organic light-emitting transistors have at least two or more source electrode layers (20s and 31) formed integrally on the same layer (see para. [0044]).
Regarding Claim 4, Kats ‘971 teaches a current supply line (11; [0061]) configured to supply current to the source electrode layer of the vertical organic light-emitting transistor, and after the current supply line is formed, the source electrode layer (20s) of the vertical organic light-emitting transistor is formed of the conductive material so as to straddle the surface layer and the current supply line.
Thus, Kats ‘971 and Mazh ‘531 are shown to teach all the features of the claim with the exception of explicitly the limitations: “after the surface layer is formed, a part of the main surface of the surface layer is formed with a current supply line”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the surface layer that can be arranged in any order, thus after the surface layer is formed, a part of the main surface of the surface layer is formed with a current supply line involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to have part of the main surface of the surface layer is formed with a current supply line when this allows a good flow with the other steps in the fabrication process.
Amended claim 4 contains functional limitation “configured to supply current to the source electrode layer of the vertical organic light-emitting transistor” (emphasis added). According to MPEP 2173(05) g. " the use of functional language in a claim may fail “to provide a clear-cut indication of the scope of the subject matter embraced by the claim” and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). For example, when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255 (Fed. Cir. 2008)”. In the instant case, “configured to supply current to the source electrode layer of the vertical organic light-emitting transistor” is nothing else than the result achieved by the invention.
Regarding Claim 10, Kats ‘971 teaches a current supply line (11; [0061]) configured to supply current to the source electrode layer of the vertical organic light-emitting transistor, and the source electrode layer (20s) of the vertical organic light-emitting transistor is formed of the conductive material so as to straddle the surface layer and the current supply line.
Thus, Kats ‘971 and Mazh ‘531 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a part of the main surface of the surface layer is formed with a current supply line”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the surface layer that can be arranged in any order, thus a part of the main surface of the surface layer is formed with a current supply line involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to have a part of the main surface of the surface layer is formed with a current supply line when this allows a good flow with the other steps in the fabrication process.
Amended claim 4 contains functional limitation “configured to supply current to the source electrode layer of the vertical organic light-emitting transistor” (emphasis added). According to MPEP 2173(05) g. " the use of functional language in a claim may fail “to provide a clear-cut indication of the scope of the subject matter embraced by the claim” and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). For example, when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255 (Fed. Cir. 2008)”. In the instant case, “configured to supply current to the source electrode layer of the vertical organic light-emitting transistor” is nothing else than the result achieved by the invention.
Regarding Claim 13, Kats ‘971 teaches a layer (bank layer (24); [0059]) between the source electrode layer (20s) and an organic semiconductor layer (20c) of the vertical organic light-emitting transistor (20), wherein the resin layer is formed with, in an active area of the display, an opening in an area where the source electrode layer and the gate electrode layer of the vertical organic light-emitting transistor overlap with each other when viewed from the direction of laminating each layer.
Thus, Kats ‘971 and Mazh ‘531 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a resin layer”.
However, it has been held to be within the general skill of a worker in the art to select a known material (e.g. resin material) on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have a resin layer in order to improve the performance of the semiconductor device.
Regarding Claim 14, Kats ‘971 teaches an auxiliary line (Fig. 4, (12); [0041]) that is directly or indirectly connected with one or more current supply lines (11) to help supply and distribute current.
Examiner notes that claim 4 contains functional limitation “to help supply and distribute current” (emphasis added). According to MPEP 2173(05) g. " the use of functional language in a claim may fail “to provide a clear-cut indication of the scope of the subject matter embraced by the claim” and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). For example, when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255 (Fed. Cir. 2008)”. In the instant case, “to help supply and distribute current” is nothing else than the result achieved by the invention.
Regarding Claim 15, Kats ‘971 teaches the auxiliary line (12) is formed on a same layer in the same process with one of the current-carrying electrode layer (11) of the thin-film transistor.
Further, it has been held to be within the general skill of a worker in the art to have the auxiliary line is formed on a same layer in the same process with one of the current-carrying electrode layer on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have the auxiliary line is formed on a same layer in the same process with one of the current-carrying electrode layer in order to reduce the process steps.
Regarding Claim 16, Kats ‘971 teaches the auxiliary line (gate line (13); [0041]) is formed on a same layer in the same process with the gate electrode layer (21g).
Further, it has been held to be within the general skill of a worker in the art to have the auxiliary line is formed on a same layer in the same process with the gate electrode layer of the thin-film transistor on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have the auxiliary line is formed on a same layer in the same process with the gate electrode layer of the thin-film transistor in order to reduce the process steps.
Claims 5-6 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable Kats ‘971 and Mazh ‘531 as applied to claim 1 above, and further in view of Rinzler (US 2013/0240842, hereinafter as Rinz ‘842).
Regarding Claims 5 and 11, Kats ‘971 and Mazh ‘531 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the gate electrode layer of the vertical organic light-emitting transistor is formed of a material made of metal oxide that exhibits conductivity and transparency to light”.
Rinz ‘842 teaches the gate electrode layer (Fig. 1B; (201a); [0047]) of the vertical organic light-emitting transistor is formed of a material made of metal oxide (ITO; [0032], [0040]) and [0047]) that exhibits conductivity and transparency to light.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kats ‘971 and Mazh ‘531 by having the gate electrode layer of the vertical organic light-emitting transistor is formed of a material made of metal oxide that exhibits conductivity and transparency to light for the purpose of transparency to visible light (see para. [0030]) as suggested by Rinz ‘842.
Regarding Claims 6 and 12, Rinz ‘842 teaches on an outer side of the thin-film transistor when viewed from a direction of laminating each layer, a color filter layer (not shown; [0081]) that transmits light in a part of a wavelength band of light emitted from the vertical organic light-emitting transistor.
Examiner notes that claims 6 and 12 contain functional limitation “transmits light in a part of a wavelength band of light emitted from the vertical organic light-emitting transistor” (emphasis added). According to MPEP 2173(05) g. " the use of functional language in a claim may fail “to provide a clear-cut indication of the scope of the subject matter embraced by the claim” and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). For example, when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255 (Fed. Cir. 2008)”. In the instant case, “transmits light in a part of a wavelength band of light emitted from the vertical organic light-emitting transistor” is nothing else than the result achieved by the invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Muccini et al. (US 2017/0250238 A1)
Kim et al. (US 2014/0054555 A1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DZUNG TRAN/
Primary Examiner, Art Unit 2893