Prosecution Insights
Last updated: April 19, 2026
Application No. 18/275,930

SEMICONDUCTOR PACKAGE

Non-Final OA §102§112
Filed
Aug 04, 2023
Examiner
LIU, BENJAMIN T
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Innotek Co., Ltd.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
3y 1m
To Grant
87%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
511 granted / 687 resolved
+6.4% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
48 currently pending
Career history
735
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.9%
+16.9% vs TC avg
§102
32.8%
-7.2% vs TC avg
§112
9.2%
-30.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 687 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 25 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 25 recites the limitation "the second-second through electrode" in ll. 1. There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 11, 13-14, 19-22, and 27-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagai et al. (US 7,683,393) (“Nagai”). With regard to claim 11, figs. 1-2 of Nagai discloses a circuit board comprising: a first insulating layer (“substrate body 2 was integrally laminated of ceramic (or insulating) layers s1 to s7”, col. 4 ll. 27-28); a first pad 17 disposed on an upper surface 4 of the first insulating layer 2; a second pad 16 disposed on a lower surface 3 of the first insulating layer 2 opposite to the upper surface 4; and a first through part 15 passing through the first insulating layer 2, wherein the first through part (18, 15) comprises a first-first through electrode 18 and a first-second through electrode 15 spaced apart from each other in a horizontal direction (left to right in fig. 2), wherein the first-second through electrode 15 is provided closer to an outer side surface (outer edge of 2) of the first insulating layer 2 than the first-first through electrode 18, wherein an outer side surface of the first-second through electrode 15 is positioned on the same plane as the outer side surface (edge of 2) of the first insulating layer 2, and wherein the first pad 17 extends from the upper surface 4 of the first insulating layer 2 toward the outer side surface (edge of 2) of the first insulating layer 2 to connect between the first-first through electrode 18 and the first-second through electrode 15. With regard to claims 13 and 27, figs. 1-2 of Nagai discloses one first pad 17 connects between an upper surface 4 of the first-first through electrode 18 and an upper surface of the first-second through electrode 15, and wherein the second pad (16, 12) comprises: a second-first pad 12 connected to the first-first through electrode 18; and a second-second pad 16 connected to the first-second through electrode 15 and spaced apart from the second-first pad 12. With regard to claims 14 and 28, figs. 1-2 of Nagai discloses an outer side surface of the first pad 17, an outer side surface of the second-second pad 16, the outer side surface of the first-second through electrode 15, and the outer side surface of the first insulating layer 2 are positioned on the same plane. With regard to claim 19, figs. 1-2 of Nagai discloses at least one of the first-first through electrode 18 and the first-second through electrode 15 has a bar shape extending in a longitudinal direction (top to bottom in fig. 2). With regard to claim 20, figs. 1-2 of Nagai discloses that the first-second through electrode 15 includes a plurality of sub through electrodes (top and bottom end portions of left middle 15 in fig. 1) including an outer side surface respectively positioned on the same plane as the outer side surface of the first insulating layer 2 and spaced apart from each other (ends of top and bottom portion of left middle 15 spaced apart from each other in fig. 1). With regard to claim 21, figs. 1-2 of Nagai discloses that the first-second through electrode 15 includes a connection through electrode (middle portion of left middle 15 in fig. 1) connecting the plurality of sub through electrodes (top and bottom end portions of left middle 15 in fig. 1). With regard to claim 22, figs. 1-2 of Nagai discloses an overall planar shape of the plurality of sub through electrodes (top and bottom end portions of left middle 15 in fig. 1) and the connection through electrode (middle portion of left middle 15 in fig. 1) has a U-shape (left middle 15 has u-shape in fig. 1). With regard to claim 25, figs. 1-2 of Nagai discloses that the second-second through electrode 7 is connected to the first-first through electrode 18 and the first-second through electrode 15 through the first pad 17. With regard to claim 26, figs. 1-2 of Nagai discloses a semiconductor package comprising: a substrate 2; an adhesive member 8 disposed on the substrate 2; and a chip 9 disposed on the adhesive member 8; wherein the substrate 2 comprises: a first insulating layer 2; a first pad 17 disposed on an upper surface 4 of the first insulating layer 2; a second pad 16 disposed on a lower surface 3 of the first insulating layer 2 opposite to the upper surface 4; and a first through part (15, 18) passing through the first insulating layer 2, wherein the first through part (15, 18) comprises a first-first through electrode 18 and a first-second through electrode 15 spaced apart from each other in a horizontal direction (left to right in fig. 2), wherein the first-second through electrode 15 is provided closer to an outer side surface (edge of 2) of the first insulating layer 2 than the first-first through electrode 18, wherein an outer side surface of the first-second through electrode 15 is positioned on the same plane (edge of 15 aligned with edge of 2 in fig. 1) as the outer side surface of the first insulating layer 2, and wherein the first pad 17 extends from the upper surface 4 of the first insulating layer 2 toward the outer side surface (edge of 2) of the first insulating layer 2 to connect between the first-first through electrode 18 and the first-second through electrode 15. With regard to claim 30, figs. 1-2 of Nagai discloses that the first-second through electrode 15 includes a plurality of sub through electrodes (top and bottom ends of left middle 15 in fig. 1) spaced apart from each other and a connection through electrode (middle portion of left middle 15 in fig. 1) connecting the plurality of sub through electrodes (top and bottom ends of left middle 15 in fig. 1), wherein an outer surface of each of the plurality of sub through electrodes (top and bottom ends of left middle 15 in fig. 1) is positioned on the same plane as the outer surface of the first insulating layer 2, and wherein the connection through electrode (middle portion of left middle 15 in fig. 1) is spaced apart from the outer surface of the first insulating layer 2. Allowable Subject Matter Claims 12, 15-18, 23-24, and 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at 571 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Aug 04, 2023
Application Filed
Dec 04, 2025
Non-Final Rejection — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604522
UNIVERSAL ELECTRICALLY INACTIVE DEVICES FOR INTEGRATED CIRCUIT PACKAGES
2y 5m to grant Granted Apr 14, 2026
Patent 12588116
MICROWAVE COOKING APPARATUS, CONTROL METHOD AND STORAGE MEDIUM
2y 5m to grant Granted Mar 24, 2026
Patent 12557677
BACKSIDE POWER DISTRIBUTION NETWORK SEMICONDUCTOR ARCHITECTURE USING DIRECT EPITAXIAL LAYER CONNECTION AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Feb 17, 2026
Patent 12550797
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Feb 10, 2026
Patent 12538581
INTEGRATED CIRCUIT INCLUDING CONNECTION LINE
2y 5m to grant Granted Jan 27, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
87%
With Interview (+12.6%)
3y 1m
Median Time to Grant
Low
PTA Risk
Based on 687 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month