Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Application filed on 8/04/2023 and IDS filed on 8/4/2023. Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1-4, 9-11, 13-17, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Banna et al. (U.S. Pub. No. 2020/0110852 A1).
As per claim 1, Banna discloses:
A method for determining a spatially varying process offset for a lithographic process, the spatially varying process offset varying over a substrate subject to the lithographic process to form one or more structures thereon, the method comprising:
obtaining a trained model having been trained to predict first metrology data (See Para [0040]-[0062], i.e. building an empirical spatial model using machine-learning techniques to predict the variability of one or more dimensions of interest across a full wafer or a portion of a wafer, See [Para [0073], i.e. final spatial model 838 obtained from the machine-learning engine 818 trained with actual and digital DoE based metrology data) based on second metrology data (See Para [0073], i.e. VM (block 828) and OBM (block 830) raw data from a current wafer (W.sub.n−1) is fed to a data filtering and feature extraction module 836. Every lot, a few wafers are sampled to go to the in-line metrology tool, and based on the data collected from in-line metrology (block 832)), wherein the first metrology data is spatially varying metrology data which relates to a first type of measurement on the one or more structures being a measure of yield and the second metrology data is spatially varying metrology data which relates to a second type of measurement on the one or more structures and correlates with the first metrology data (See Para [0035], i.e. measurements performed on the devices themselves within a die or on test structures having features similar to the device, See Para [0038], i.e. such as TEM, previously performed on a similar set of devices. These on-tool and off-tool metrology is performed on a finite number of wafers dedicated for DoE…relationships between metrology of dimensions of interest and various knobs that control the process, Para [0076], i.e. VM and OBM are used to qualitatively provide a spatial map of the dimension of interest, which is then compared to a golden reference to identify potential points of failure. Selected wafers are then taken to the in-line metrology tool (such as e-beam for customized metrology and the areas of interest where the potential failure sites are identified are scanned in detail to identify the root cause of failure – [prior art correlate different data (Figure 8, i.e., VM raw data, OBM raw data, in-line metrology data), considered as the first type of measurement and second type of measurement as cited above]); and
using the model to obtain the spatially varying process offset (See Para [0053], i.e. immediately suggests virtual recipes that would give predictable performance within the desired process window, See Para [0073], i.e. The output of the inverse spatial model is to recommend an adjusted recipe (block 846) for the next wafer (W.sub.n) within the same lot –[prior art adjust manufacturing process based on the model, considered as obtaining of the offset as cited above]).
As per claim 2, Banna discloses all of the features of claim 1 as discloses above wherein Banna also discloses training the model using the first metrology data and second metrology data (See Para [0040]-[0062], i.e. building an empirical spatial model using machine-learning techniques to predict the variability of one or more dimensions of interest across a full wafer or a portion of a wafer, See [Para [0073], i.e. final spatial model 838 obtained from the machine-learning engine 818 trained with actual and digital DoE based metrology data).
As per claim 3, Banna discloses all of the features of claim 1 as discloses above wherein Banna also discloses wherein the first metrology data comprises electrical characteristic data describing an electrical characteristic of the one or more structures (See Para [0035], i.e. measurements performed on the devices themselves within a die or on test structures having features similar to the device, See Para [0038], i.e. such as TEM, previously performed on a similar set of devices. These on-tool and off-tool metrology is performed on a finite number of wafers dedicated for DoE…relationships between metrology of dimensions of interest and various knobs that control the process, Para [0076], i.e. VM and OBM are used to qualitatively provide a spatial map of the dimension of interest, which is then compared to a golden reference to identify potential points of failure. Selected wafers are then taken to the in-line metrology tool (such as e-beam for customized metrology and the areas of interest where the potential failure sites are identified are scanned in detail to identify the root cause of failure).
As per claim 4, Banna discloses all of the features of claim 3 as discloses above wherein Banna also discloses wherein the first type of measurement comprises one or more selected from: electrostatic discharge measurement, electrical probe measurement, or scan fault isolation measurement (See Para [0082], i.e. such as TEM, electrical test tool etc. The electrical test data may include device parametric and yield data).
As per claim 9, Banna discloses all of the features of claim 1 as discloses above wherein Banna also discloses wherein the model has a variable spatial resolution such that the spatial scale of the spatially varying process offset can be varied (See Para [0040]-[0062], i.e. building an empirical spatial model using machine-learning techniques to predict the variability of one or more dimensions of interest across a full wafer or a portion of a wafer, See [Para [0073], i.e. final spatial model 838 obtained from the machine-learning engine 818 trained with actual and digital DoE based metrology data).
As per claim 10, Banna discloses all of the features of claim 9 as discloses above wherein Banna also discloses wherein the model aggregates the second metrology data in accordance with a desired spatial scale for the spatially varying process offset (See Para [0040]-[0062], i.e. building an empirical spatial model using machine-learning techniques to predict the variability of one or more dimensions of interest across a full wafer or a portion of a wafer, See [Para [0073], i.e. final spatial model 838 obtained from the machine-learning engine 818 trained with actual and digital DoE based metrology data).
As per claim 11, Banna discloses all of the features of claim 9 as discloses above wherein Banna also discloses wherein the spatial scale is variable between at least one selected from: measurement location level, die level, field level, or multiple-field region level (See Para [0040]-[0062], i.e. building an empirical spatial model using machine-learning techniques to predict the variability of one or more dimensions of interest across a full wafer or a portion of a wafer, See Para [0073], i.e. final spatial model 838 obtained from the machine-learning engine 818 trained with actual and digital DoE based metrology data)
As per claim 13, Banna discloses all of the features of claim 1 as discloses above wherein Banna also discloses wherein the spatially varying process offset comprises an offset between a nominal optimal parameter value as measured by a metrology device and an actual optimal parameter value which optimizes yield (See Para [0053], i.e. immediately suggests virtual recipes that would give predictable performance within the desired process window, See Para [0073], i.e. The output of the inverse spatial model is to recommend an adjusted recipe (block 846) for the next wafer (W.sub.n) within the same lot).
As per claim 14, Banna discloses all of the features of claim 1 as discloses above wherein Banna also discloses wherein a smoothness constraint is imposed on the model so as to impose smoothness in the variation of the spatially varying relationship between values corresponding to the first metrology data and second metrology data, and/or to impose smoothness in the variation of the spatially varying process offset (See Para [0035], i.e. measurements performed on the devices themselves within a die or on test structures having features similar to the device, See Para [0038], i.e. such as TEM, previously performed on a similar set of devices. These on-tool and off-tool metrology is performed on a finite number of wafers dedicated for DoE…relationships between metrology of dimensions of interest and various knobs that control the process, Para [0076], i.e. VM and OBM are used to qualitatively provide a spatial map of the dimension of interest, which is then compared to a golden reference to identify potential points of failure. Selected wafers are then taken to the in-line metrology tool (such as e-beam for customized metrology and the areas of interest where the potential failure sites are identified are scanned in detail to identify the root cause of failure).
As per claim 15, Banna discloses:
A non-transitory computer program product comprising instructions therein, the instructions, when executed by a processor system, configured to cause the processor system to at (See Figure 13) least:
obtain a trained model having been trained to predict first metrology data (See Para [0040]-[0062], i.e. building an empirical spatial model using machine-learning techniques to predict the variability of one or more dimensions of interest across a full wafer or a portion of a wafer, See [Para [0073], i.e. final spatial model 838 obtained from the machine-learning engine 818 trained with actual and digital DoE based metrology data) based on second metrology data (See Para [0073], i.e. VM (block 828) and OBM (block 830) raw data from a current wafer (W.sub.n−1) is fed to a data filtering and feature extraction module 836. Every lot, a few wafers are sampled to go to the in-line metrology tool, and based on the data collected from in-line metrology (block 832)), wherein the first metrology data is spatially varying metrology data which relates to a first type of measurement on structures being a measure of yield and the second metrology data is spatially varying metrology data which relates to a second type of measurement on the structures and correlates with the first metrology data (See Para [0035], i.e. measurements performed on the devices themselves within a die or on test structures having features similar to the device, See Para [0038], i.e. such as TEM, previously performed on a similar set of devices. These on-tool and off-tool metrology is performed on a finite number of wafers dedicated for DoE…relationships between metrology of dimensions of interest and various knobs that control the process, Para [0076], i.e. VM and OBM are used to qualitatively provide a spatial map of the dimension of interest, which is then compared to a golden reference to identify potential points of failure. Selected wafers are then taken to the in-line metrology tool (such as e-beam for customized metrology and the areas of interest where the potential failure sites are identified are scanned in detail to identify the root cause of failure – [prior art correlate different data (Figure 8, i.e., VM raw data, OBM raw data, in-line metrology data), considered as the first type of measurement and second type of measurement as cited above]); and
use the model to obtain a spatially varying process offset for a lithographic process, the spatially varying process offset varying over a substrate subject to the lithographic process to form one or more structures thereon (See Para [0053], i.e. immediately suggests virtual recipes that would give predictable performance within the desired process window, See Para [0073], i.e. The output of the inverse spatial model is to recommend an adjusted recipe (block 846) for the next wafer (W.sub.n) within the same lot –[prior art adjust manufacturing process based on the model, considered as obtaining of the offset as cited above])
As per claim 16, Banna discloses all of the features of claim 15 as discloses above wherein Banna also discloses wherein the instructions are further configured to cause the computer system to train the model using the first metrology data and second metrology data (See Para [0040]-[0062], i.e. building an empirical spatial model using machine-learning techniques to predict the variability of one or more dimensions of interest across a full wafer or a portion of a wafer, See [Para [0073], i.e. final spatial model 838 obtained from the machine-learning engine 818 trained with actual and digital DoE based metrology data).
As per claim 17, Banna discloses all of the features of claim 15 as discloses above wherein Banna also discloses wherein the first metrology data comprises electrical characteristic data describing an electrical characteristic of the one or more structures (See Para [0035], i.e. measurements performed on the devices themselves within a die or on test structures having features similar to the device, See Para [0038], i.e. such as TEM, previously performed on a similar set of devices. These on-tool and off-tool metrology is performed on a finite number of wafers dedicated for DoE…relationships between metrology of dimensions of interest and various knobs that control the process, Para [0076], i.e. VM and OBM are used to qualitatively provide a spatial map of the dimension of interest, which is then compared to a golden reference to identify potential points of failure. Selected wafers are then taken to the in-line metrology tool (such as e-beam for customized metrology and the areas of interest where the potential failure sites are identified are scanned in detail to identify the root cause of failure).
As per claim 19, Banna discloses all of the features of claim 15 as discloses above wherein Banna also discloses wherein the model has a variable spatial resolution such that the spatial scale of the spatially varying process offset can be varied (See Para [0053], i.e. immediately suggests virtual recipes that would give predictable performance within the desired process window, See Para [0073], i.e. The output of the inverse spatial model is to recommend an adjusted recipe (block 846) for the next wafer (W.sub.n) within the same lot).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim(s) 5-8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Banna et al. (U.S. Pub. No. 2020/0110852 A1) in view of YPMA et al. (WO 2018/202361 from IDS filed 8/4/2023).
As per claim 5, Banna discloses all of the features of claim 1 as discloses above.
Banna does not teach: wherein the second metrology data comprises overlay data.
However, YPMA teach: wherein the second metrology data comprises overlay data (See Para [0055]-[0056], i.e. overlay, See Para [0079], i.e. overlay metrology (e.g., after develop inspection (ADI) metrology).).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of YPMA into
the teaching of Banna because it would allow designer to determine yield related
information for a circuit which is available well before the end product is available for
electrical testing (See Para [0014]).
As per claim 6, Banna and YPMA discloses all of the features of claim 5 as discloses above wherein YPMA also discloses wherein the overlay data comprises one or more selected from: of after-develop overlay data measured prior to a processing step or after-etch overlay data measured after the processing step (See Para [0055]-[0056], i.e. overlay, See Para [0079], i.e. overlay metrology (e.g., after develop inspection (ADI) metrology).).
As per claim 7, Banna and YPMA discloses all of the features of claim 5 as discloses above wherein YPMA also discloses wherein the spatially varying process offset is an overlay offset to be used as a desired overlay value during the lithographic process (See Para [0081], See Para [0077]).
As per claim 8, Banna and YPMA discloses all of the features of claim 5 as discloses above wherein YPMA also discloses wherein the second metrology data further comprises additional process data relating to a parameter other than overlay or dose (See Para [0057]).
As per claim 18, Banna discloses all of the features of claim 15 as discloses above.
Banna does not teach: wherein the second metrology data comprises overlay data.
However, YPMA teach: wherein the second metrology data comprises overlay data. (See Para [0055]-[0056], i.e. overlay, See Para [0079], i.e. overlay metrology (e.g., after develop inspection (ADI) metrology).).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of YPMA into
the teaching of Banna because it would allow designer to determine yield related
information for a circuit which is available well before the end product is available for
electrical testing (See Para [0014]).
Allowable Subject Matter
7. Claims 12 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
8. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach the limitations of claims 12 and/or 20.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NHA T NGUYEN/Primary Examiner, Art Unit 2851
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