Prosecution Insights
Last updated: May 29, 2026
Application No. 18/276,453

DISPLAY DEVICE

Final Rejection §103
Filed
Aug 09, 2023
Priority
Feb 15, 2021 — nonprovisional of PCTJP2021005426
Examiner
BLACKWELL, ASHLEY NICOLE
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sharp Kabushiki Kaisha
OA Round
2 (Final)
98%
Grant Probability
Favorable
3-4
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 98% — above average
98%
Career Allowance Rate
55 granted / 56 resolved
+30.2% vs TC avg
Minimal +3% lift
Without
With
+2.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
26 currently pending
Career history
90
Total Applications
across all art units

Statute-Specific Performance

§103
92.1%
+52.1% vs TC avg
§102
4.5%
-35.5% vs TC avg
§112
3.4%
-36.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 56 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, see pages 5-9, filed 01/26/2026, with respect to the rejection(s) of claims 1-3, 5 and 9-12 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lee et al. (US 20180144705 A1). Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1, 2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20140339508 A1) in view of Lee et al. (US 20180144705 A1). Regarding claim 1, Hong discloses a display device comprising: a display region (DA) comprising a plurality of pixels (PX) provided in a matrix; ([0037]-[0038], Fig. 1) a plurality of thin-film transistors (T inside PDC) that is provided for the plurality of respective pixels (PX), ([0052], Fig. 1 and 3) wherein: each of the plurality of capacitors (C1 and C2) includes a lower electrode (SS) provided in a lower layer, an upper electrode (CB1) provided in an upper layer above the lower electrode (SS), and an insulating portion (60 inside C1) provided between the lower electrode (SS) and the upper electrode (CB1), (Fig. 6) the lower electrode (SS) contains a material (due to being an extension of the source electrode) identical to a material of a source electrode (SS) of each of the plurality of thin-film transistors (T), (Fig. 6) each of the plurality of pixels (PX) includes a first electrode (CA), a second electrode (AN), and a light-emitting layer (80) provided between the first electrode (CA) and the second electrode (AN), the upper electrode (CB1) contains a material identical to a material of the first electrode (CA). ([0040], Fig. 6) Hong does not disclose: a plurality of capacitors provided in a frame region located around the display region, and electrically floating; and in a plan view, the display region has a rectangular shape with four sides, the frame region includes a terminal section facing one of the four sides, and in the plan view, the plurality of capacitors is arranged in such a manner to face only an opposite face of another side of the four sides, the other side being opposite to the one of the four sides facing the terminal section. However, Lee discloses: a plurality of capacitors (Cref2) provided in a frame region (N/A) located around the display region (AA), and electrically floating (per [[0107]); (Fig. 17) in a plan view (Fig. 17), the display region (150) has a rectangular shape with four sides, the frame region includes a terminal section (130) facing one of the four sides, and in the plan view (Fig. 17), the plurality of capacitors (Cref2 in each 130A) is arranged in such a manner to face only an opposite face of another side of the four sides, the other side being opposite to the one of the four sides facing the terminal section (130). (Fig. 17) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hong and Lee to have a plurality of capacitors provided in a frame region located around the display region, and electrically floating and in a plan view, the display region has a rectangular shape with four sides, the frame region includes a terminal section facing one of the four sides, and in the plan view, the plurality of capacitors is arranged in such a manner to face only an opposite face of another side of the four sides, the other side being opposite to the one of the four sides facing the terminal section in order to “compensate for a variation in a threshold voltage (and mobility) of the driving transistor” (Lee, [0035]) Regarding claim 2, Lee discloses the display device according to claim 1, wherein each of the plurality of capacitors (Cref2 in each 130A) is not connected to and is separated from, a routed wire (VREF1) routed from the display region (150) to the frame region (outside of 150). (Fig. 17) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hong and Lee for similar reasons mentioned beforehand. Regarding claim 9, Hong discloses the display device according to claim 1, further comprising an interlayer insulating layer (60) covering the plurality of thin-film transistors (T) and having a surface (annotated below) where the first electrode (CA) is provided, wherein the insulating portion contains a material identical to a material of the interlayer insulating layer. (Fig. 6) PNG media_image1.png 447 623 media_image1.png Greyscale Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20140339508 A1) in view of Lee et al. (US 20180144705 A1) as applied to claim 1 above, and further in view of Seo et al. (US 20160379578 A1). Regarding claim 3, Hong in view of Lee disclose the display device according to claim 1. Hong in view of Lee do not disclose wherein the plurality of capacitors is arranged along a shorter side of the rectangular shape at an end of the display region. However, Seo discloses: the plurality of capacitors (Cd) is arranged along a shorter side (bottom) of the rectangular shape at an end of the display region (DA). (Fig. 5) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hong, Lee and Seo for wherein the plurality of capacitors is arranged along a shorter side of the rectangular shape at an end of the display region in order to “collect external static electricity coming through the signal wires before the external static electricity flows into the lighting circuits.” (Seo, Abstract) Claims 5, 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20140339508 A1) in view of Lee et al. (US 20180144705 A1) as applied to claim 1 above, and further in view of Wang (CN 1111129101 A). Regarding claim 5, Hong in view of Lee disclose the display device according to claim 1. Hong in view of Lee do not disclose wherein each of the plurality of capacitors is arranged along the end of the display region in such a manner that in the plan view, the plurality of capacitors is partly adjacent to each other in a direction of approach from the frame region to the display region, or in a direction from the frame region outward. However, Wang discloses: each of the plurality of capacitors (410+420) is arranged along the end of the display region (AA) in such a manner that in the plan view, the plurality of capacitors (410+420) is partly adjacent to each other in a direction of approach from the frame region (outside AA) to the display region (AA), or in a direction from the frame region outward (outside AA). (Fig. 11C) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hong, Lee and Wang for each of the plurality of capacitors is arranged along the end of the display region in such a manner that in the plan view, the plurality of capacitors is partly adjacent to each other in a direction of approach from the frame region to the display region, or in a direction from the frame region outward in order to “improve the static leading effect on the plate capacitor structure.” (Wang, page 10 of the translation) Regarding claim 10, Hong in view of Lee disclose the display device according to claim 1. Hong in view of Lee do not disclose further comprising a sealing layer covering the display region, wherein the plurality of capacitors is provided in a region where the sealing layer is provided. However, Wang discloses: a sealing layer (200) covering the display region (AA), (Fig. 1) wherein the plurality of capacitors (410+420) is provided in a region (NA) where the sealing layer (200) is provided. (Fig. 1 and 2) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hong, Lee and Wang for similar reasons as mentioned beforehand. Regarding claim 11, Hong in view of Lee disclose the display device according to claim 1. Hong in view of Lee do not disclose wherein each of the plurality of capacitors is configured such that the lower electrodes are coupled to each other and the upper electrodes are separated from each other, or such that the lower electrodes are separated from each other and the upper electrodes are coupled to each other. However, Wang discloses: Each of the plurality of capacitors (410+420) is configured such that the lower electrodes (420) are coupled to each other (see page 10 of the translation, Fig. 6g and 11a) and the upper electrodes (410) are separated from each other (see Fig. 6g and 11a), (the examiner has met the first limitation and therefore the limitation after “or” is treated as optional) or such that the lower electrodes are separated from each other, and that the upper electrodes are coupled to each other. It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hong, Lee and Wang for similar reasons as mentioned beforehand. Claim 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20140339508 A1) in view of Lee et al. (US 20180144705 A1) as applied to 1 above, and further in view of Seo (US 20200135120 A1). Regarding claim 12, Hong in view of Lee disclose the display device according to claim 1. Hong in view of Lee do not disclose further comprising a plurality of electrode pads connected to the plurality of capacitors. However, Seo discloses: a plurality of electrode pads (PI1-PI7) connected to the plurality of capacitors (C1-C5). ([0093], Fig. 2) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hong, Lee and Seo for a plurality of electrode pads connected to the plurality of capacitors so that “mechanical strength is ensured with a reduced thickness of the display device.” (Seo, [0010]) Regarding claim 13, Hong in view of Lee disclose the display device according to claim 1. Hong in view of Lee do not disclose further comprising a connection wire electrically connected to the upper electrode, wherein: a line width of the connection wire is smaller than a line width of the upper electrode, and in the plan view, a part of the upper electrode and a part of the connection wire overlap with the lower electrode. However, Seo discloses: a connection wire (LI2) electrically connected to the upper electrode (CE2), wherein: a line width of the connection wire (LI2) is smaller than a line width of the upper electrode (CE2), and in the plan view (Fig. 2) , a part of the upper electrode (CE2) and a part of the connection wire (LI2) overlap with the lower electrode. ([0093], Fig. 2) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hong, Lee and Seo for a connection wire electrically connected to the upper electrode, wherein: a line width of the connection wire is smaller than a line width of the upper electrode, and in the plan view, a part of the upper electrode and a part of the connection wire overlap with the lower electrode so that “mechanical strength is ensured with a reduced thickness of the display device.” (Seo, [0010]) Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897 /JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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Prosecution Timeline

Aug 09, 2023
Application Filed
Oct 27, 2025
Non-Final Rejection mailed — §103
Jan 26, 2026
Response Filed
Apr 08, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
98%
Grant Probability
99%
With Interview (+2.9%)
3y 5m (~7m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 56 resolved cases by this examiner. Grant probability derived from career allowance rate.

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