DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The abstract of the disclosure is objected to because The abstract of the disclosure does not commence on a separate sheet in accordance with 37 CFR 1.52(b)(4) and 1.72(b). A new abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 3, 5, 6, 10, and 14 – 16 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US Patent No. 5,130,779 to Agarwala et al.
Regarding claim 1, Agarwala et al. teach a solder bump structure comprising:
an under bump metallurgy (UBM) layer (14);
a first solder portion (16) over the UBM layer, the first solder portion having a first composition;
a barrier layer (18) encapsulating the first solder portion; and
a second solder portion (26) over the barrier layer, the second solder portion having a second composition different from the first composition (Col. 10, lines 37-43).
Regarding claim 2, Agarwala et al. teach a solder bump structure, wherein the first solder portion has an upper surface, at least one side surface, and a lower surface positioned over the UBM layer, the barrier layer encapsulating at least part of the upper surface and the at least one side surface of the first solder portion. See Figs. 3 and 4.
Regarding claim 3, Agarwala et al. teach a solder bump structure, wherein the barrier layer is configured to limit diffusion of material between the first solder portion and the second solder portion during multiple reflowing of the bump structure (Col. 5, lines 56 – 62).
Regarding claim 5, Agarwala et al. teach a solder bump structure, wherein the second solder portion exhibits a substantially hemispherical shape after a first reflowing of the bump structure (Col. 11, lines 64 – 68).
Regarding claim 6, Agarwala et al. teach a solder bump structure, wherein the barrier layer restrains the first solder portion to a substantially cylindrical shape during multiple reflowing of the bump structure (Col. 10, lines 22 – 27).
Regarding claim 10, Agarwala et al. teach a solder bump, wherein the barrier layer comprise a layer of nickel (Ni) (Col. 13, lines 62 – 65).
Regarding claim 14, Agarwala et al. teach a solder bump, wherein the UBM layer is configured to be deposited over an integrated circuit (IC) chip (Col. 9, lines 25 – 33) and the second solder portion is configured to form a solder joint with a substrate for interconnecting the IC chip and the substrate and forming a flip-chip assembly (Col. 16, lines 21 – 25).
Regarding claim 15, Agarwala et al. teach a method for manufacturing a solder bump structure, the method comprising:
depositing an under bump metallurgy (UBM) layer (14) over an integrated circuit (IC) chip (Col. 9, lines 25 – 33);
depositing a first solder layer (16) over the UBM layer, the first solder layer having a first composition;
depositing a barrier layer (18) that encapsulates the first solder portion; and
depositing at least one second solder layer over the barrier layer, the at least one second solder layer having a second composition different from the first composition (Col. 10, lines 37-43).
Regarding claim 16, Agarwala et al. teach a method, wherein the barrier layer is deposited to encapsulate at least part of an upper surface and at least one side surface of the first solder layer. See Figs. 3 and 4.
Allowable Subject Matter
Claims 4, 7 – 9, 11, 12, 17, 19, 20, 22, and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent No. 6,501,185 to Chow et al. teach a solder structure including a conductive structure with a barrier layer encapsulation and a solder portion over the barrier layer. Chow et al. do not teach the first solder portion.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS W OWENS whose telephone number is (571)272-1662. The examiner can normally be reached M-F 5:30-1:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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DOUGLAS W. OWENS, Esq.
Primary Patent Examiner
Art Unit 2897
/DOUGLAS W OWENS/Primary Patent Examiner, Art Unit 2897