DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 9-12, 14-15, and 21-27 are rejected under 35 U.S.C. 102(a)(1) as being ancitipated by Massicotte1
Regarding claim 1, Massicotte teaches a method for laterally confining neutral excitons in a semiconductor layer structure of a solid-state device, the semiconductor layer structure comprising at least one semiconductor layer and defining a device plane (Fig. 1b), the method comprising: creating an inhomogeneous electric field in the semiconductor layer structure, the electric field having an in-plane field having a magnitude that varies along at least at least one confinement direction in the device plane, the magnitude of the in-plane field component having a maximum along said confinement direction (Fig. 1d electric field distribution varying along the x direction, compare with Fig. 3 of the instant application); whereby the in-plane field component causes a lateral confining potential for neutral excitons around the maximum; and irradiating the solid-state device with light to create neutral excitons in the semiconductor layer structure, the neutral excitons being laterally confined along the confinement direction by the lateral confining potential (p. 3-4, Fig. 1e, compare upper solid line with Fig. 2 of the instant application; application Spec at p. 15, l. 10-31 teaches the exciton confinement arises from the in-plane electric field and charge density gradient; Fig. 1a depicts charge density under [AltContent: textbox (Application Figures)]
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the electric field (F>0), compare with upper dashed line of application Fig. 3).
Regarding claim 2, Massicotte teaches wherein creating the inhomogeneous electric field in the semiconductor layer structure comprises modifying a charge carrier density in the semiconductor layer structure to create a p-doped region and/or an n-doped region (p. 3, “Applying gate voltages of opposite polarity … leads to the formation of a sharp p-n junction … with an in-plane electric field (Fig. 1d)”).
Regarding claim 3, Massicotte teaches wherein both a p-doped region and an n-doped region are created, the p-doped region and the n-doped region being laterally separated in the device plane by an i-type region, the maximum of the magnitude of the in-plane field component being located in the i-type region between the p-doped region and the n-doped region, whereby the neutral excitons are laterally confined in the i-type region (Fig. 1b-1c, undoped (i-type) region between gates; see application, p. 14, l. 25-34).
Regarding claim 5, Massicotte teaches wherein modifying the charge carrier density in the semiconductor layer structure comprises applying at least one gate voltage between at least one gate electrode and the semiconductor layer structure (p. 3, “Applying gate voltages of opposite polarity … leads to the formation of a sharp p-n junction … with an in-plane electric field (Fig. 1d)”, V(G1), V(G2)).
Regarding claim 6, Massicotte teaches wherein the solid-state device comprises an insulating first spacer layer disposed on a first surface of the semiconductor layer structure and a first gate electrode arranged on the first spacer layer, and wherein creating the inhomogeneous electric field comprises applying a first gate voltage between the first gate electrode and the semiconductor layer structure (Fig. 1b, bottom hBN layer between semiconductor layer WSe2 and gate electrodes Pd; p. 3, “Applying gate voltages of opposite polarity … leads to the formation of a sharp p-n junction … with an in-plane electric field”)
Regarding claim 7, Massicotte teaches wherein the solid-state device further comprises a second gate electrode arranged on the first spacer layer, wherein creating the inhomogeneous electric field in the semiconductor layer structure comprises applying a second gate voltage between the second gate electrode and the semiconductor layer structure, the first and second gate voltages having opposite signs (Fig. 1b, 1e).
Regarding claim 9, Massicotte teaches wherein the maximum of the magnitude of the in-plane field component is at least 10 V/μm (Fig. 1d).
Regarding claim 10, Massicotte teaches wherein the at least one semiconductor layer in the semiconductor layer structure has a thickness that causes electric polarizability of excitons perpendicular to the device plane to be not more than 10% of electric polarizability of excitons in the device plane (Fig. 1b, monolayer WSe2 is less than 1nm thickness; see Spec, p. 8, l. 29-35, “the thickness should be sufficiently small that the electric polarizability of direct excitons in the semiconductor layer perpendicular to the device plane is not more than 10% … the thickness of the semiconductor is preferably not more than 5 nm, more preferably not more than 2 nm, and it may be less than 1 nm”).
Regarding claim 11, Massicotte teaches wherein excitons in the semiconductor layer structure have a binding energy of at least 10 meV (p. 3, Eb = 170 meV).
Regarding claim 12, Massicotte teaches wherein the semiconductor layer structure comprises a semiconductor material selected from the group consisting of transition metal dichalcogenides, inorganic and organic hybrid perovskites, black phosphorous, bilayer graphene, silicene, antimonene, and semiconducting polymers (Fig. 1, p. 2, WSe2 is a transition metal dichalcogenide).
Regarding claims 14 and 27, Massicotte does not explicitly teach wherein the lateral confining potential causes the excitons to have at least two bound motional eigenstates in the lateral confining potential, wherein the at least two bound motional eigenstates are separated by an energy splitting at least 0.5 meV. However, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. See MPEP 2112.01. The lateral confining potential is identical or substantially identical in structure (see rejection of claim 1). Therefore, the result of that lateral confining potential is anticipated by Massicotte.
Regarding claim 15, Massicotte teaches a device for laterally confining neutral excitons, the device comprising: a semiconductor layer structure defining a device plane; an insulating first spacer layer disposed on a first surface of the semiconductor layer structure; a first gate electrode arranged on the first spacer layer; a second gate electrode arranged on the first spacer layer or on an insulating second spacer layer disposed between the semiconductor layer structure and the second gate electrode on a second surface of the semiconductor layer structure opposite to the first spacer layer; a first voltage source configured to apply a first gate voltage between the first gate electrode and the semiconductor layer structure; and a second voltage source configured to apply a second gate voltage between the second gate electrode and the semiconductor layer structure (Fig. 1b, WSe2 semiconductor layer, bottom hBN spacer layer, first/second gate electrodes Pd, first/second voltage sources VG1/G2);
wherein application of the first and second gate voltages causes an inhomogeneous electric field in the semiconductor layer structure, the electric field having an in-plane field component having a magnitude that varies along at least one confinement direction in the device plane, the magnitude of the in-plane field component having a maximum along said confinement direction (Fig. 1d electric field distribution varying along the x direction, compare with Fig. 3 of the instant application) whereby the in-plane field component causes a lateral confining potential for neutral excitons around the maximum (p. 3-4, Fig. 1e, compare upper solid line with Fig. 2 of the instant application; application Spec at p. 15, l. 10-31 teaches the exciton confinement arises from the in-plane electric field and charge density gradient; Fig. 1a depicts charge density under the electric field (F>0), compare with upper dashed line of application Fig. 3).
Regarding claim 21, Massicotte teaches wherein the semiconductor layer structure comprises a transition metal dichalcogenide layer (Fig. 1, p. 2, WSe2 is a transition metal dichalcogenide).
Regarding claim 22, Massicotte teaches an optical system configured to irradiate the semiconductor layer structure with incident light to excite neutral excitons in the semiconductor layer structure (p. 6, photocurrent measurements, laser beam, microscope objective, stage, etc.).
Regarding claim 23, Massicotte teaches wherein the in-plane field component as a function of position along the confinement direction describes a curve having a full width at half maximum of not more than 100 nm (see attached annotated Fig. 1d).
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Regarding claim 24, Massicotte teaches wherein the semiconductor layer has a thickness of not more than 5 nm (Fig. 1b, monolayer WSe2 is less than 1nm thickness).
Regarding claim 25, Massicotte teaches wherein excitons in the semiconductor layer structure have a binding energy of at least 50 meV (p. 3, Eb = 170 meV). Regarding claim 26, Massicotte teaches wherein the semiconductor layer structure comprises a transition metal dichalcogenide monolayer (Fig. 1, p. 2, monolayer WSe2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Massicotte in view of Peimyoo2
Regarding claim 4, Massicotte does not explicitly teach wherein modifying the charge carrier density in the semiconductor layer structure comprises chemical doping of at least a portion of the semiconductor layer structure.
Peimyoo teaches wherein chemical doping of TMD materials allows modifying the charge carrier density (p. 11325, col. 1, “physical adsorption of dopants can tune the carrier concentration in 1L WS2 and strongly modulate its optical and electrical properties, which are expected to be a generic effect for other layered TMD materials as well”).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Peimyoo with Massicotte such that modifying the charge carrier density in the semiconductor layer structure comprises chemical doping of at least a portion of the semiconductor layer structure for the purpose of modifying the carrier concentration and electrical properties (Peimyoo, p. 11325).
Claims 8 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Massicotte in view of Lee (KR 102198343 B1).
Regarding claim 8, Massicotte does not explicitly teach wherein the second gate electrode is arranged on the second spacer layer and partially overlaps with the first gate electrode when viewed along an out-of-plane direction that is perpendicular to the device plane.
Lee teaches an additional gate electrode arranged on a second spacer layer and partially overlapping with the first gate electrode when viewed along an out-of-plane direction that is perpendicular to the device plane (Figs. 1a-c, 32, 102/202, Fig. 4).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Lee with Massicotte such that the second gate electrode is arranged on the second spacer layer and partially overlaps with the first gate electrode when viewed along an out-of-plane direction that is perpendicular to the device plane for the purpose of adjusting the Fermi level and electric field position (Lee, Figs. 4-5 and corresponding text).
Regarding claim 16, Massicotte does not explicitly teach wherein the second gate electrode is arranged on the second spacer layer and partially overlaps with the first gate electrode when viewed along an out-of-plane direction that is perpendicular to the device plane.
Lee teaches an additional gate electrode arranged on a second spacer layer and partially overlapping with the first gate electrode when viewed along an out-of-plane direction that is perpendicular to the device plane (Figs. 1a-c, 32, 102/202, Fig. 4).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Lee with Massicotte such that the second gate electrode is arranged on the second spacer layer and partially overlaps with the first gate electrode when viewed along an out-of-plane direction that is perpendicular to the device plane for the purpose of adjusting the Fermi level and electric field position (Lee, Figs. 4-5 and corresponding text).
Regarding claim 17, Massicotte teaches wherein upon application of the first and second gate voltages, an n- or p-doped region is created in the semiconductor layer structure in a region of the first gate electrode where no overlap with the second gate electrode exists, and an oppositely doped region is created in a region of overlap, such that an i-type region forms at an edge of the region of overlap along the perimeter of the second gate electrode (p. 3, “Applying gate voltages of opposite polarity … leads to the formation of a sharp p-n junction … with an in-plane electric field (Fig. 1d)”; Fig. 1b-1c, undoped (i-type) region between gates; see application, p. 14, l. 25-34).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Massicotte in view of Ross3
Regarding claim 13, Massicotte does not explicitly teach wherein the solid state device is operated at a temperature at which the excitons have a ratio between binding energy and linewidth in the lateral confining potential of at least 10. Massicotte teaches wherein the neutral exciton binding energy is 170 meV when operated at room temperature (p. 3, Eb).
Ross teaches wherein the solid state device is operated at a temperature at which the excitons have linewidth in the lateral confining potential of 5 meV (Fig. 1, monolayer Wse2 device; p. 270, room temperature; p. 271, neutral exciton linewidth).
Therefore it would have been obvious to a person having ordinary skill in the art that operating the device of Ross at room temperature as taught would result in the excitons having a ratio between binding energy and linewidth in the lateral confining potential of at least 10.
Allowable Subject Matter
Claims 18-20 and 28-30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art does not teach or suggest the claimed electrode shapes and corresponding lateral confining potential. Art teaching shapes similar to those claimed (Shanks4, Fig. 1; Hu5, Fig. 3) is not available as prior art.
Conclusion
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/ALIA SABUR/ Primary Examiner, Art Unit 2812
1 Massicotte, Mathieu & Vialla, Fabien & Schmidt, Peter & Lundeberg, Mark & Latini, Simone & Haastrup, Sten & Danovich, Mark & Davydovskaya, Diana & Watanabe, Kenji & Taniguchi, Takashi & Falko, Vladimir & Thygesen, Kristian & Pedersen, Thomas & Koppens, Frank. (2018). Dissociation of two-dimensional excitons in monolayer WSe2. Nature Communications. 9. 10.1038/s41467-018-03864-y.
2 Peimyoo, Namphung & Weihuang, Yang & Shang, Jingzhi & Shen, Xiaonan & Wang, Yanlong & Yu, Ting. (2014). Chemically Driven Tunable Light Emission of Charged and Neutral Excitons in Monolayer WS 2. ACS nano. 8. 10.1021/nn504196n.
3 Ross, Jason & Klement, Philip & Jones, Aaron & Ghimire, Nirmal & Yan, J.-Q & Mandrus, D & Taniguchi, Takashi & Watanabe, Kenji & Kitamura, Kenji & Yao, Wang & Cobden, David & Xu, Xiaodong. (2014). Electrically tunable excitonic light-emitting diodes based on monolayer WSe2 p-n junctions. Nature nanotechnology. 9. 10.1038/nnano.2014.26.
4 Shanks, Daniel & Mahdikhanysarvejahany, Fateme & Muccianti, Christine & Alfrey, Adam & Koehler, Michael & Mandrus, David & Taniguchi, Takashi & Watanabe, Kenji & Yu, Hongyi & LeRoy, Brian & Schaibley, John. (2021). Nanoscale trapping of interlayer excitons in a 2D semiconductor heterostructure. 10.48550/arXiv.2103.08838.
5 Hu, Jenny & Lorchat, Etienne & Chen, Xueqi & Watanabe, Kenji & Taniguchi, Takashi & Heinz, Tony & Murthy, Puneet & Chervy, Thibault. (2024). Quantum control of exciton wave functions in 2D semiconductors. Science advances. 10. eadk6369. 10.1126/sciadv.adk6369.