DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-7 and 9-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuo et al. (US 2020/0052048 A1; hereinafter, “Kuo”, of record).
PNG
media_image1.png
510
782
media_image1.png
Greyscale
PNG
media_image2.png
510
782
media_image2.png
Greyscale
Regarding claims 1, 3-7 and 9-20:
re claim 1, Kuo discloses a display substrate, comprising:
a base substrate SB (Fig. 1F, 1G and [0050]), comprising a first display region DR1 (Fig. 1D and [0022]) and a second display region DR2 (Fig. 1D and [0022]) located on least one side of the first display region;
a plurality of first pixel circuits (e.g., A1/A2 of SP1R in Figs. 1D-1F and [0050-0051], wherein [0051] discloses electrode layers A1 and A2 are electrically connected; accordingly, A1/A2 is a pixel circuit) and a plurality of first light emitting elements P1 (Figs. 1D-1E and [0026]) , located in the first display region DR1; wherein at least one first pixel circuit (e.g., A1/A2 of SP1R of Fig. 1D-1F) among the plurality of first pixel circuits is electrically connected with at least one first light emitting element (e.g., P1(P) in Fig. 1E) among the plurality of first light emitting elements, and is configured to drive the at least one first light emitting element to emit light (e.g., SP1R of P1(P) emits red light, [0050]); and
at least one first signal line (a combination of “first sub-signal line” and “second sub-signal line” in Exhibit A) configured to provide a first signal to the plurality of first pixel circuits in a first direction D2 (in Fig. 1D and [0039]); wherein the at least one first signal line comprises a first sub-signal line (see “first sub-signal line” in Exhibit A) and a second sub-signal line (see “second sub-signal line” in Exhibit A) connected in parallel and electrically (e.g., see Exhibit A, two points of connections “T1(T)” are shown for “first sub-signal line” and “second sub-signal line”, wherein the first and second sub-signal lines are electrically connected at least at these two points and the two sub-signal lines are shown parallel to each other), the first sub-signal line is located in the first display region DR1 (Fig. 1D), and the second sub-signal line is located in the second display region DR2 (Fig. 1D);
re claim 3, the display substrate according to claim 1, wherein the second sub-signal line is located on a side of the first sub-signal line away from the base substrate (i.e., in Figs. 1F and 1G, “A1” or “A2” could be the sub-signal lines because Kuo discloses A1 and A2 are electrically connected [0051]; accordingly, with respect to the current claim, the second sub-signal line would be “A1” and the first sub-signal line would be “A2”);
re claim 4, the display substrate according to claim l, wherein the at least one first signal line further (a combination of “first sub-signal line” and “second sub-signal line” in Exhibit A) comprises: a third sub-signal line (see “third sub-signal line” in Exhibit A) and a fourth sub-signal line (see “fourth sub-signal line” in Exhibit A) located in the second display region DR2, wherein the third sub-signal line and the fourth sub-signal line are located in the second display region DR2 (Fig. 1D) on opposite sides of the first display region DR1 along the first direction D2; and
both ends of the first sub-signal line (see “ends of first sub-signal line” in Exhibit A) are electrically connected with the third sub-signal line and the fourth sub-signal line, respectively, and both ends of the second sub-signal line (see “ends of second sub-signal line” in Exhibit A) are electrically connected with the third sub-signal line and the fourth sub-signal line, respectively;
re claim 5, the display substrate according to claim 4, wherein at least one end of the first sub-signal line is electrically connected with the third sub-signal line or the fourth sub-signal line through a gate of a transistor of at least one first pixel circuit (e.g., in Fig. 1D and Exhibit A, active element T (or T1) is electrically connected to the first sub-signal line and the third/fourth sub-signal lines, wherein the active element comprises a TFT [0057]; accordingly, at least one end of the first sub-signal line is electrically connected through a TFT, which comprises a gate for operation; therefore, the electrical connection is achieved through a gate of the TFT);
re claim 6, the display substrate according to claim l, wherein the display substrate comprises a plurality of first signal lines SSL (e.g., SSL2 in Fig. 1C and [0024]) which are divided into two groups; a second sub-signal line of a first group of first signal lines is located within the second display region on one side of the first display region along a second direction, and a second sub-signal line of a second group of first signal lines is located within the second display region on the other side of the first display region along the second direction, and the second direction intersects with the first direction (i.e., in Fig. 1D, the second display region DR2 surround the first display region DR1; accordingly, a first group of first signal lines SSL2 would be in a region above DR1, and a second group of first signal lines SSL2 would be in a region below DR1; therefore, the first and second groups are located on opposing sides of the first display region DR1 in a second direction D1, which intersects the first direction D2, see Fig. 1D);
re claim 7, the display substrate according to claim 1, further comprising: a plurality of second pixel circuits (e.g., ST2 in Fig. 1G and [0058]) and a plurality of second light emitting elements P2(P) (Fig. 1D and [0026]) located in the second display region DR2 (Fig. 1D), wherein at least one second pixel circuit among the plurality of second pixel circuits is electrically connected with at least one second light emitting element among the plurality of second light emitting elements, and is configured to drive the at least one second light emitting element to emit light (Fig. 1G, e.g., ST21(ST2) is a driving transistor for R1); and
an orthographic projection of the second sub-signal line (see “second sub-signal line” in Exhibit A) of the at least one first signal line on the base substrate is not overlapped with an orthographic projection of an anode A2 (Fig. 1G and [0051]) of the second light emitting element P2(P) (Fig. 1D) on the base substrate;
re claim 9, the display substrate according to claim 7, wherein the second sub-signal line (see “second sub-signal line” in Exhibit A) comprises: a first connection segment (see “1” in Exhibit A), a second connection segment (see “2” in Exhibit A), a third connection segment (see “3” in Exhibit A), and a fourth connection segment (see “4” in Exhibit A);
the second connection segment “2” (Exhibit A) is a straight line segment extending along the first direction D2 (Fig. 1D), the second connection segment is electrically connected with the first connection segment “1” (Exhibit A), and the first connection segment is configured to at least partially surround an anode of one second light emitting element (e.g., in Exhibit A, segment “1” partially surrounds P2(P) above region DR1); the third connection segment is a fold line extending along a second direction D1 (Exhibit A), the fourth connection segment is connected with the third connection segment, and the fourth connection segment is a straight line segment extending along the first direction D2; and the second direction D1 intersects with the first direction D2;
re claim 10, the display substrate according to claim 8, wherein the second display region DR2 (Figs. 1D and 1E) is further provided with a plurality of auxiliary traces (e.g., in the cross-section B-B’ in Fig. 1E, traces including “SSL(SSL2)” and portions between “SSL(SSL2)” and “P2(P)”) disposed in a same layer as the second sub-signal line (e.g., SSL1 in Exhibit A), wherein an orthographic projection of the plurality of auxiliary traces on the base substrate is not overlapped with the orthographic projection of the anode of the second light emitting element or the orthographic projection of the connection position of the gate of the drive transistor, the first electrode of the threshold compensation transistor, and the first electrode plate of the storage capacitor of the second pixel circuit on the base substrate (i.e., the traces comprise SSL(SSL2) and portions between SSL(SSL2) and P2(P), therefore, orthographic projections of the traces don’t overlap P2(P), which contains the anode, connection position, the first electrode and the first electrode plate that are part of the pixel circuit within P2(P));
re claim 11, the display substrate according to claim 10, wherein the auxiliary traces are configured to be electrically connected with a first power supply line (i.e., the auxiliary traces are electrically connected to the second driving circuit 130, Fig. 1C; and 130 will be electrically connected to a power supply line in order for the display to function properly);
re claim 12, the display substrate according to claim 11, wherein at least one of the plurality of auxiliary traces comprises: a first auxiliary segment SSL(SSL2) (Fig. 1E) and a second auxiliary segment (portions between SSL(SSL2) and P2(P) in Fig. 1E) which are connected with each other; and the first auxiliary segment SSL(SSL2) is a straight line segment extending along the first direction D2 (Figs. 1C and 1E), and the second auxiliary segment is a fold line extending along a second direction D1 (Figs. 1C and 1E), and the second direction D1 intersects with the first direction D2;
re claim 13, the display substrate according to claim l, wherein the at least first signal line comprises at least one of following: a scan line (Fig. 1C and [0027], wherein the second driving circuit 130 is a gate/scan driving circuit and the first driving circuit 120 is a data driving circuit), a first reset control line, and a light emitting control line;
re claim 14, the display substrate according to claim 1, further comprising: at least one second signal line configured to provide a second signal to the plurality of first pixel circuits in a second direction D1 (Fig. 1D and Exhibit B); the at least one second signal line comprises a fifth sub-signal line (see “fifth sub-signal line” in Exhibit B) and a sixth sub-signal line (see “sixth sub-signal line” in Exhibit B) connected in parallel and electrically, wherein the fifth sub-signal line is located in the first display region DR1 and the sixth sub-signal line is located in the second display region DR2; and the first direction D2 intersects with the second direction D1;
re claim 15, the display substrate according to claim 14, wherein the first direction D2 is perpendicular to the second direction D1 (Fig. 1D and Exhibit B);
re claim 16, the display substrate according to claim 14, wherein the at least one second signal line further comprises: a seventh sub-signal line (see “seventh sub-signal line” in Exhibit B) and an eighth sub-signal line (see “eight sub-signal line” in Exhibit B) located in the second display region DR2, wherein the seventh sub-signal line and the eighth sub-signal line are located within the second display region DR2 on opposite sides of the first display region DR1 along the second direction D1; and both ends of the fifth sub-signal line are electrically connected with the seventh sub-signal line and the eighth sub-signal line (see “ends of fifth sub-signal line” and “ends of sixth sub-signal line” in Exhibit B), respectively, and both ends of the sixth sub-signal line are electrically connected with the seventh sub-signal line and the eighth sub-signal line, respectively;
re claim 17, the display according to claim 14, wherein the fifth sub-signal line is disposed in a same layer as the first sub-signal line (i.e., all layers shown in Figs. 1F-1G will be in an encapsulation layer in order to acquire a complete display), and the sixth sub-signal line (located in a film layer for signal lines SSL1, Fig. 1D) and the second sub-signal (located in a film layer for signal lines FSL1, Fig. 1D) are located in different film layers;
re claim 18, the display substrate according to claim l, wherein a pixel density of the first display region DR1 is less than or equal to a pixel density of the second display region DR2 (Fig. 1D);
re claim 19, the display substrate according to claim 1, wherein a light transmittance rate of the first display region DR1 is greater than a light transmittance rate of the second display region DR2 [0044]; and
re claim 20, A display apparatus, comprising a display substrate according to claim 1 (Fig. 1A).
Therefore, claims 1, 3-7 and 9-20 are anticipated by Kuo.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo in view of Fu (US 2020/0251539 A1, of record).
Regarding claim 2:
Kuo anticipates claim 1 but does not specify materials for the first and second sub-signal lines; accordingly, Kuo does not disclose a combination of transparent conductive material and metal material.
Fu teaches, in a similar display, signal lines 211 (Fig. 13 and [0104]) located outside of a light transmittance area AA2 [0049] are made of metal (e.g., are made of the same material as a gate electrode or source/drain electrodes, and in [0057], Fu specifies no TFT or metal trace in region AA2, which comprises a transparent region) and signal lines 213/180 (Fig. 13, [0077] and [0098]) located in the light transmittance area AA1 are made of transparent conductive material (e.g., ITO).
It would have been obvious to one of ordinary skill in the art to specifically incorporate metal signal lines and transparent conductive signal lines, as taught by Fu, because the incorporation would ensure Kuo’s first display region DR1 has a higher transmittance than the second display region DR2 (i.e., Kuo discloses the importance of higher transmittance [0048, 0054]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo in view of Lee et al. (US 2020/0044006 A1; hereinafter, “Lee”, of record).
Regarding claim 8:
Kuo anticipates claim 7 and discloses an orthographic projection of the second sub-signal line (see “second sub-signal line” in Exhibit A) of the at least one first signal line on base substrate is not overlapped with an orthographic projection of the pixel circuit (e.g., ST2 in Fig. 1G and [0058]). However, Kuo does not disclose all details of the second pixel circuit; accordingly, Kuo does not disclose the limitations in the current claim.
Lee teaches a complete pixel circuit that is suitable for a display similar to that in Kuo, wherein Lee discloses the pixel circuit (Fig. 5) comprises: a drive transistor T1 [0087], a threshold compensation transistor T3 [0087], and a storage capacitor Cst [0085]; a gate of the drive transistor T1 is electrically connected with a first electrode plate Cst1 of the storage capacitor Cst and a first electrode D3 [0091] of the threshold compensation transistor T3.
Since Kuo does not disclose details for an entire pixel circuit, it would have been obvious to one of ordinary skill in the art to incorporate a pixel circuit, as taught by Lee, because such a pixel circuit is well suited for a display and would provide a complete pixel circuit necessary for a functional display. Furthermore, it is noted that the pixel circuit (in both Kuo and Lee) is contained within a pixel; accordingly, in Fig. 1D of Kuo (e.g., Exhibit A), an orthographic projection of the second sub-signal line of the at least one first signal line on base substrate is not overlapped with an orthographic projection of the entire pixel circuit contained within P2(P), wherein the entire pixel circuit comprises a connection position of the gate of the drive transistor, the first electrode of the threshold compensation transistor, and the first electrode plate of the storage capacitor of the second pixel circuit on the base substrate.
Remarks
The objections to the title and claims are withdrawn in view of the amendments.
Applicant’s remarks/arguments have been carefully reviewed and considered; however, they are not persuasive because it appears applicant requires narrow interpretations of the current claim language. Applicant submits Kuo discloses active elements T1 and T2 are not in the first display region DR1; accordingly, it appears applicant asserts that Kuo does not disclose a plurality of pixel circuits located in the first display region. Applicant further submits there are pixel circuits in the first display region (of current claim 1), and thus the drive transistors of the pixel circuits are also located in the first display region. The examiner respectfully notes that current claim 1 does not require/recite drive transistors in the pixel circuits; accordingly, the current claim language does not require such a narrow interpretation for “pixel circuit”. In other words, a pixel circuit could be a combination of an electrode layer A1 (Kuo, [0051]), electrode layer A2 and/or an OLED in the region DR1. Therefore, the examiner respectfully disagrees with what appears to be applicant’s required narrow interpretation of “pixel circuit”.
Applicant further submits that the “first sub-signal line” as understood by the examiner is actually the wiring between the transistors and the sub-pixels, and is not a decomposition of the first signal line or the second signal line (into sub-signal lines). The examiner respectfully disagrees because each pixel connected to “SSL1” requires a “sub-signal line” branching from “SSL1” in order for a plurality of pixels to be connected to “SSL1”; therefore, the current claim language does not require what seems to be applicant’s required narrow interpretation of a first “sub-signal line” and a second “sub-signal line”.
In sum, the prior grounds of rejections are maintained because the current claim language does not require what appears to be applicant’s narrow interpretation of “pixel circuit” and “sub-signal lines”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
Prosecution Insights