Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 2/5/2026 has been entered. Claims 1, 3 are amended. Claims 4, 7, 18, 23, 25 – 32 are canceled. Claims 1 – 3, 5 – 6, 8 – 17, 19 – 22, 24 remain pending in the application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 24 rejected under 35 U.S.C. 102 (a) (2) as being unpatentable over Adiga.
Regarding Independent Claim 24 (Original) Adiga teaches a conductive substrate for an electronic device provided with a removable protective coating ( Adiga, [0037], a 10 nm to 20 nm thick layer of PMMA is deposited on the graphene. The PMMA may increase the structural integrity; [0038], In some embodiments, the PMMA is then removed (e.g., using an acetone solution or forming gas) ), the substrate consisting of:
an insulative layer (Adiga, FIG. 2A, FIG. 2B, 204, 206, 214, 216) having a thickness of from 1 nm to 1 μm (Adiga, [0023], the first and the second oxide layers are each about 50 nm to 300 nm thick, or about 200 nm thick; [0024], the first and the second nitride layers are each about 20 nm to 60 nm thick, or about 40 nm thick), and having first and second opposing planar surfaces;
a graphene monolayer or multi-layer structure ( Adiga, FIG. 2I, 252; [0040], graphene sheet 252; The graphene sheet 252 is disposed on the second nitride layer 216 ) on the first planar surface of the substrate;
a dissolvable polymer coating ( Adiga, [0037], a 10 nm to 20 nm thick layer of PMMA is deposited on the graphene. The PMMA may increase the structural integrity; [0038], In some embodiments, the PMMA is then removed (e.g., using an acetone solution or forming gas) ) over the graphene monolayer or multi-layer structure (Adiga, FIG. 2I, 252; [0040], graphene sheet 252); and
optionally, a silicon layer on the second planar surface, the silicon layer having a thickness of less than 100 nm ( Adiga, [0004], a thin spacer sandwiched between two chips with thin (less than about 100 nanometer (nm)) silicon nitride membranes; [0023], first and the second oxide layers are each about 50 nm to 300 nm thick, or about 200 nm thick ).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, 8, 12 are rejected under 35 U.S.C. 103 as being unpatentable over Adiga ( Pub. No. US 20160042912 A1 ), hereinafter Adiga, in view of Vijayaraghavan ( Pub. No. US 20200048082 A1 ), hereinafter Vijayaraghavan.
Regarding Independent Claim 1 (Currently Amended) Adiga teaches a method for the manufacture of an electronic device precursor, the method comprising, in order:
(i) providing a silicon wafer ( Adiga, FIG. 1, 105; FIG. 2A, 202; [0023], In some embodiments, the substrate comprises silicon; [0025], substrate 202 ) having a growth surface ( Adiga, [0023], When the substrate comprises silicon, the oxide layer may be silicon oxide and the silicon oxide may be thermally grown on the silicon substrate );
(ii) forming an insulative layer ( Adiga, FIG. 2A, FIG. 2B, 204, 206, 214, 216; FIG. 2E, 232; [0025], first oxide layer 204, second oxide layer 206, first nitride layer 214, and second nitride layer 216; [0031], third nitride layer 232 disposed on the second oxide layer 206 ) on the growth surface having a thickness of from 1 nm to 10 μm ( Adiga, [0023], In some embodiments, the first and the second oxide layers are each about 50 nm to 300 nm thick, or about 200 nm thick; [0024], In some embodiments, the first and the second nitride layers are each about 20 nm to 60 nm thick, or about 40 nm thick; [0030], In some embodiments, the third nitride layer is about 20 nm to 60 nm thick, or about 40 nm thick );
(iii) forming a graphene monolayer or multi-layer structure ( Adiga, FIG. 2I, 252; [0040], graphene sheet 252; The graphene sheet 252 is disposed on the second nitride layer 216 ) on the insulative layer ( Adiga, FIG. 2A, FIG. 2B, 204, 206, 214, 216; FIG. 2E, 232 );
(iv) optionally forming one or more further layers ( Adiga, FIG. 4F, FIG. 4G, 432, 416; FIG. 5, 505; [0059], polymer material 432, second nitride layer 416; [0062], silicon nitride layer 505 ) and/or electrical contacts ( Adiga, FIG. 5, 510, 520; [0062], a first electrode 510 and a second electrode 520 ) on the graphene monolayer or multi-layer structure ( Adiga, FIG. 4G, 252; [0059], graphene sheet 252; [0040], In some embodiments, the graphene sheet 252 comprises a monolayer of graphene. In some embodiments, the graphene sheet 252 comprises a few layers of graphene );
(v) forming a polymer coating ( Adiga, [0037], A thin poly(methyl methacrylate) (PMMA) solution may be deposited (e.g., spin coated) on the graphene. In some embodiments, a 10 nm to 20 nm thick layer of PMMA is deposited on the graphene; FIG. 4F, FIG. 4G, 432; [0059], polymer material 432 ) over the graphene monolayer or multi-layer structure ( Adiga, FIG. 4G, 252; [0059], graphene sheet 252 ) and any further layers ( Adiga, FIG. 4F, FIG. 4G, 416 ) and/or electrical contacts ( Adiga, [0037], For example, in some embodiments, the graphene is grown on copper using a CVD process. A thin poly(methyl methacrylate) (PMMA) solution may be deposited (e.g., spin coated) on the graphene );
(vi) thinning the silicon wafer ( Adiga, FIG. 2D, 202; [0025], substrate 202 ), or removing the silicon wafer( Adiga, FIG. 2D, 202; [0025], substrate 202 ) to provide an exposed surface ( Adiga, [0029], a cavity 224 in the substrate 202 exposing the second oxide layer 206 ) of the insulative layer ( Adiga, FIG. 2D, 206; [0025], second oxide layer 206 ), by etching with an etchant ( [0028], In some embodiments, etching the substrate is performed with a wet etching process (e.g., a potassium hydroxide (KOH) etch or a tetramethylammonium hydroxide (TMAH) etch when the substrate comprises silicon). A KOH etch will etch the second oxide layer, so the etch duration may be timed when using a KOH etch so as to not etch the second oxide layer too much. A TMAH etch will not etch the second oxide layer ), wherein the silicon wafer is optionally subjected to a grinding ( Adiga, [0023], In some embodiments, the substrate comprises a double side polished semiconductor wafer ) step before etching; and
(vii) optionally dissolving away the polymer coating ( Adiga, [0038], the PMMA is then removed (e.g., using an acetone solution or forming gas) );
wherein the insulative layer ( Adiga, FIG. 2D, second oxide layer 206 ) resistant to etching by the etchant ( Adiga, [0028], … potassium hydroxide (KOH) … tetramethylammonium hydroxide (TMAH) ); and
wherein the silicon wafer has a post-etching thickness after step (vi) of less than 100 microns ( Adiga, FIG. 2D, 202; [0029], FIG. 2D … a cavity 224 in the substrate 202 exposing the second oxide layer 206 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create wherein the silicon wafer has a post-etching thickness after step (vi) of less than 100 microns, by combining the teaching of Adifa [0023] ( i.e. 150 microns to 450 microns ) and FIG. 2D ( i.e. cavity 224 ), since this is within the skill level of one in the art. Furthermore, “ [W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. ” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Adiga fails to teach:
wherein the polymer coating is resistant to etching by the etchant.
However, Vijayaraghavan teaches:
wherein the polymer coating is resistant to etching by the etchant ( Vijayaraghavan, [0124], a new PMMA layer (PMMA 950 3 wt % in anisole) is spin-coated (3000 rpm for 60 s) and baked (130° C. for 5 mins) onto the graphene; [0125], The graphene-PMMA membrane with tape support window is then submerged in an aqueous potassium hydroxide solution (30 wt %) for up to 5 hours until the tape support window and graphene-PMMA membrane lifts off the Si/SiO2 substrate and floats on the surface of the solution ).
Adiga and Vijayaraghavan are both considered to be analogous to the claimed invention because they are forming the graphene substrate. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Adiga ( forming the graphene substrate on the insulative layer SiO2 ), to incorporate the teachings of Vijayaraghavan ( PMMA in graphene-PMMA membrane resistant to potassium hydroxide solution (30 wt %) for up to 5 hours until it lifts off the silicon substrate ), to implement that wherein the polymer coating is resistant to etching by the etchant. Doing so would provide a specific process which can etch the silicon substrate and meanwhile protect the graphene substrate by covering the polymer PMMA, and therefore a thin graphene substrate can be fabricated.
Regarding Claim 3 (Currently Amended) Adiga and Vijayaraghavan teach the method as claimed in claim 1, on which this claim is dependent, Adiga further teaches:
wherein the silicon wafer ( Adiga, FIG. 1, 105 ) has a pre-etching thickness in step (i) of at least 200 microns ( Adiga, [0023], In some embodiments, the substrate is about 150 microns to 450 microns thick, or about 300 microns thick ) and/or wherein the silicon wafer has a post-etching thickness after step (vi) of less than 10 microns ( Adiga, FIG. 2D, 202; [0029], FIG. 2D … a cavity 224 in the substrate 202 exposing the second oxide layer 206 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create wherein the silicon wafer has a post-etching thickness after step (vi) of less than 10 microns, by combining the teaching of Adifa [0023] ( i.e. 150 microns to 450 microns ) and FIG. 2D ( i.e. cavity 224 ), since this is within the skill level of one in the art. Furthermore, “ [W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. ” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding Claim 5 (Previously Presented) Adiga and Vijayaraghavan teach the method as claimed in claim 1, on which this claim is dependent, Adiga further teaches:
wherein the insulative layer ( Adiga, FIG. 2A, FIG. 2B, 204, 206, 214, 216 ) comprises a material selected from the group consisting of Al2O3, AlN, h-BN, c-BN, ZnO, HfO2, SiO2 ( [0025], first oxide layer 204, second oxide layer 206 ) and SiNx ( [0031], third nitride layer 232 disposed on the second oxide layer 206 ).
Regarding Claim 8 (Previously Presented) Adiga and Vijayaraghavan teach the method as claimed in claim 1, on which this claim is dependent, Adiga further teaches:
wherein the insulative layer ( Adiga, FIG. 2A, FIG. 2B, 204, 206, 214, 216; [0025], first oxide layer 204, second oxide layer 206, first nitride layer 214, and second nitride layer 216 ) and the polymer coating ( Adiga, [0037], A thin poly(methyl methacrylate) (PMMA) ) are resistant to etching by the etchant ( Adiga, [0028], … potassium hydroxide (KOH) … tetramethylammonium hydroxide (TMAH) ) such that under the etching conditions the silicon is etched at least 10 times faster ( Adiga, [0028], TMAH etch will not etch the second oxide layer ) by weight.
Regarding Claim 12 (Previously Presented) Adiga and Vijayaraghavan teach the method as claimed in claim 1, on which this claim is dependent, Adiga further teaches:
wherein step (ii) is performed in a CVD or MOCVD reaction chamber ( Adiga, [0023], In some embodiments, the oxide may be deposited on the substrate using a chemical vapor deposition (CVD) technique or a physical vapor deposition (PVD) technique. ).
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Adiga, in view of Vijayaraghavan, in view of He ( U: He, H., Kim, K.H., Danilov, A. et al. Uniform doping of graphene close to the Dirac point by polymer-assisted assembly of molecular dopants. Nat Commun 9, 3956 (2018) ), hereinafter He.
Regarding Claim 2 (Original) Adiga and Vijayaraghavan teach the method as claimed in claim 1, on which this claim is dependent, Adiga and Vijayaraghavan further teach:
wherein the polymer coating ( Adiga, [0037], A thin poly(methyl methacrylate) (PMMA) solution may be deposited (e.g., spin coated) on the graphene. In some embodiments, a 10 nm to 20 nm thick layer of PMMA is deposited on the graphene; FIG. 4F, FIG. 4G, 432; [0059], polymer material 432 ) is formed directly on the graphene monolayer or multi-layer structure ( Adiga, FIG. 4G, 252; [0059], graphene sheet 252 ) and wherein the polymer coating ( Adiga, [0037] ) comprises a polymer and a dopant, wherein the polymer has a first doping effect on graphene and the dopant has an opposite and substantially equal second doping effect on graphene.
Adiga and Vijayaraghavan fail to teach:
wherein the polymer coating comprises a polymer and a dopant, wherein the polymer has a first doping effect on graphene and the dopant has an opposite and substantially equal second doping effect on graphene.
However, He teaches:
wherein the polymer coating comprises a polymer ( He, page 2, column on the right, line 13, PMMA ) and a dopant ( He, page 2, column on the right, line 13, F4TCNQ ), wherein the polymer has a first doping effect ( He, page 2, column on the right, line 15, hole-doping ) on graphene and the dopant has an opposite and substantially equal ( He, page 2, column on the right, line 13, charge-neutral graphene ) second doping effect ( He, page 2, column on the right, line 15, electron-doping ) on graphene ( He, page 2, column on the right, line 11, The resulting carrier density could be fine-tuned by the total annealing time. For a concentration of 7% of F4TCNQ in PMMA by weight, charge-neutral graphene is achieved after annealing at T = 160 °C for 5 min. Shorter annealing times yield hole-doping and longer times yield electron-doping (Supplementary Fig. 1) ).
Adiga, Vijayaraghavan and He are all considered to be analogous to the claimed invention because they are forming the graphene substrate. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Adiga and Vijayaraghavan ( forming the graphene substrate on the insulative layer SiO2, and PMMA in graphene-PMMA membrane resistant to etchant ), to incorporate the teachings of He ( carrier density could be fine-tuned by the total annealing time by using F4TCNQ in PMMA ), to implement that wherein the polymer has a first doping effect on graphene and the dopant has an opposite and substantially equal second doping effect on graphene. Doing so would provide specific materials and processes which can make n-type and p-type graphene, and therefore expand the functionality of graphene substrate.
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Adiga, in view of Vijayaraghavan, in view of Kil ( Pub. No. US 20050110069 A1 ), hereinafter Kil.
Regarding Claim 6 (Previously Presented) Adiga and Vijayaraghavan teach the method as claimed in claim 1, on which this claim is dependent,
Adiga and Vijayaraghavan do not explicitly teach:
wherein the insulative layer is formed by ALD and/or in a water-free process.
However, Kil teaches:
wherein the insulative layer is formed by ALD ( Kil, [0026], FIG. 5 is a timing diagram showing gas supply to a chamber when the HfO2 and Al2O3 alloyed dielectric layer is formed by employing an atomic layer deposition (ALD) technique in accordance with the first preferred embodiment of the present invention ) and/or in a water-free process ( Kil, [0029], FIG. 7B is a diagram showing an alloyed state of (HfO2)1-x(Al2O3 )x formed by a reaction between a single molecular source gas of Hf-Al and a reaction gas of ozone (O3) ).
Adiga, Vijayaraghavan and Kil are all considered to be analogous to the claimed invention because they are forming the insulative dielectric layer. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Adiga and Vijayaraghavan ( first oxide layer 204, second oxide layer 206, first nitride layer 214, and second nitride layer 216 ), to incorporate the teachings of Kil ( dielectric layer is formed by atomic layer deposition (ALD) and/or by a reaction gas of ozone (O3) ), to implement that wherein the insulative layer is formed by ALD and/or in a water-free process. Doing so would provide specific processes to make insulative dielectric layers which can be used to make the electronic device precursor having graphene substrate.
Claims 9 – 11 are rejected under 35 U.S.C. 103 as being unpatentable over Adiga, in view of Vijayaraghavan, in view of Ishiwata ( Pub. No. US 5300172 A ), hereinafter Ishiwata.
Regarding Claim 9 (Previously Presented) Adiga and Vijayaraghavan teach the method as claimed in claim 1, on which this claim is dependent,
Adiga and Vijayaraghavan do not explicitly teach:
wherein the polymer coating comprises HDPE.
However, Ishiwata teaches:
wherein the polymer coating comprises HDPE ( Ishiwata, Abstract, a surface-protection method during chemical etching of a plate material, which comprises sticking a radiation-curable adhesive tape onto the area of plate material where etching should not be effected; column 7, line 6, The radiation-curable adhesive was coated onto the surface of a 100 µm-thick film support made of a high-density polyethylene resin; column 7, line 24, This radiation-curable adhesive tape was stuck onto a silicon wafer; column 7, line 30, Then the wafer was dipped for 5 min in an etching liquid of a mixture of nitric acid (concentration: 61%) and hydrofluoric acid (concentration: 46%) (mixing volume ratio: 10:1), to etch the wafer ).
Adiga, Vijayaraghavan and Ishiwata are all considered to be analogous to the claimed invention because they are forming the polymer coating which is resistant to etching by the etchant. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Adiga and Vijayaraghavan ( PMMA in graphene-PMMA membrane resistant to etchant ), to incorporate the teachings of Ishiwata ( adhesive … where etching should not be effected … made of a high-density polyethylene resin ), to implement that polymer coating comprises HDPE. Doing so would provide specific polymer coating HDPE which is resistant to etching by the etchant HF, and therefore it can be used to protect the desired part of graphene substrate during the etching process.
Regarding Claim 10 (Previously Presented) Adiga and Vijayaraghavan teach the method as claimed in claim 1, on which this claim is dependent,
Adiga and Vijayaraghavan do not explicitly teach:
wherein the etchant is HF in gaseous or aqueous form.
However, Ishiwata teaches:
wherein the etchant is HF ( Ishiwata, Abstract, a surface-protection method during chemical etching of a plate material; column 7, line 24, This radiation-curable adhesive tape was stuck onto a silicon wafer; column 7, line 30, Then the wafer was dipped for 5 min in an etching liquid of a mixture of nitric acid (concentration: 61%) and hydrofluoric acid (concentration: 46%) (mixing volume ratio: 10:1), to etch the wafer ) in gaseous or aqueous form.
Adiga, Vijayaraghavan and Ishiwata are all considered to be analogous to the claimed invention because they are forming the polymer coating which is resistant to etching by the etchant. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Adiga and Vijayaraghavan ( PMMA in graphene-PMMA membrane resistant to etchant ), to incorporate the teachings of Ishiwata ( hydrofluoric acid (concentration: 46%) ), to implement that wherein the etchant is HF. Doing so would provide specific polymer coating HDPE which is resistant to etching by the etchant HF, and therefore it can be used to protect the desired part of graphene substrate during the etching process.
Regarding Claim 11 (Previously Presented) Adiga and Vijayaraghavan teach the method as claimed in claim 1, on which this claim is dependent, Adiga further teaches:
wherein in step (vi) the silicon wafer ( Adiga, FIG. 2D, 202 ) is reduced from a pre-etch thickness ( Adiga, FIG. 2B, 202 ) to a post-etch thickness ( Adiga, FIG. 2D, 202 ) and wherein step (vi) comprises a grinding step to remove from 70 to 99% of the difference between the pre-etch and the post-etch thicknesses.
Adiga and Vijayaraghavan do not explicitly teach:
wherein step (vi) comprises a grinding step to remove from 70 to 99% of the difference between the pre-etch and the post-etch thicknesses.
However, Ishiwata teaches:
wherein step (vi) comprises a grinding step to remove from 70 to 99% of the difference between the pre-etch and the post-etch thicknesses ( Ishiwata, column 1, line 30, The step of grinding the back surface of a semiconductor wafer is carried out in such a way that the circuit-pattern formed wafer surface is secured by suction and the back surface is ground so that the thickness is reduced, for example from 500 µm to 300-200 µm, and is made uniform ).
Adiga, Vijayaraghavan and Ishiwata are all considered to be analogous to the claimed invention because they are forming a thin silicon wafer. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Adiga and Vijayaraghavan ( thinning the silicon wafer ), to incorporate the teachings of Ishiwata ( grinding the back surface of a semiconductor wafer ), to implement that wherein the etchant is HF. Doing so would provide a grinding process to remove the major thickness of the silicon wafer, and therefore a thin graphene substrate can be fabricated efficiently.
Claims 13 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Adiga, in view of Vijayaraghavan, in view of Chen ( Pub. No. US 20140084252 A1 ), hereinafter Chen.
Regarding Claim 13 (Previously Presented) Adiga and Vijayaraghavan teach the method as claimed in claim 1, on which this claim is dependent, Adiga further teaches:
wherein the insulative layer (Adiga, FIG. 2A, FIG. 2B, 204, 206, 214, 216) has a thickness of less than 10 nm ( Adiga, [0024], In some embodiments, the first and the second nitride layers are each about 20 nm to 60 nm thick ), wherein the silicon wafer is removed ( Adiga, FIG. 2B, FIG. 2D, 202 ) or thinned to less than 10 nm in step (vi),
Adiga and Vijayaraghavan fail to teach:
wherein the method comprises forming a light sensitive or light emitting structure on a first portion of the graphene monolayer or multi-layer structure in step (iv), and forming a first contact on the light sensitive or light emitting structure in step (iv), and forming a second contact:
(a) on the exposed surface of the insulative layer after step (vi); or
(b) on a second portion of the graphene monolayer or multi-layer structure in step (iv); or
(c) on a second portion of the graphene monolayer or multi-layer structure after step (vii).
However, Chen teaches:
wherein the method comprises forming a light sensitive or light emitting structure ( Chen, FIG. 5B, 16; [0055], electroluminescent material 16 ) on a first portion of the graphene monolayer or multi-layer structure ( Adiga, FIG. 2I, 252 ) in step (iv), and forming a first contact ( Chen, FIG. 5B, 18; [0058], cathode material 18 ) on the light sensitive or light emitting structure ( Chen, FIG. 5B, 16 ) in step (iv), and forming a second contact (Chen, FIG. 5B, 12):
(a) on the exposed surface of the insulative layer after step (vi); or
(b) on a second portion of the graphene monolayer or multi-layer structure ( Chen, FIG. 5B, 12; [0026], the layer of doped graphene 12 serves as a bottom transparent conductive electrode of an OLED device. In other embodiments, the layer of doped graphene 12 can serve as a top transparent conductive electrode of an OLED device ) in step (iv); or
(c) on a second portion of the graphene monolayer or multi-layer structure after step (vii).
Adiga, Vijayaraghavan and Chen are all considered to be analogous to the claimed invention because they are forming graphene substrate used for electronic devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Adiga and Vijayaraghavan (thin graphene substrate), to incorporate the teachings of Chen ( graphene substrate is used as electrode ), to implement OLED in which the electrode is made by graphene substrate. Doing so would use graphene to replace the transparent conductive electrode in OLED, and therefore to reduce the manufacturing cost of OLED and make OLED device extremely flexible.
Regarding Claim 14 (Original) Adiga, Vijayaraghavan and Chen teach the method as claimed in claim 13, on which this claim is dependent, Adiga and Chen further teach:
wherein the second contact ( Adiga, [0062], a first electrode 510 and a second electrode 520 disposed on a silicon nitride layer 505) is formed on the exposed surface of the insulative layer ( Adiga, FIG. 2A, FIG. 2D, 206 ) after removing the silicon wafer ( Adiga, FIG. 2B, FIG. 2D, 202 ) in step (vi), and a third contact is formed on a second portion of the graphene monolayer or multi-layer structure ( Chen, FIG. 5B, 12; [0026], the layer of doped graphene 12 serves as a bottom transparent conductive electrode of an OLED device. In other embodiments, the layer of doped graphene 12 can serve as a top transparent conductive electrode of an OLED device ), either in step (iv) after step (vii).
Regarding Claim 15 (Previously Presented) Adiga, Vijayaraghavan and Chen teach the method as claimed in claim 13, on which this claim is dependent, Chen further teaches:
wherein the second contact is transparent ( Chen, FIG. 5B, 12; [0026], the layer of doped graphene 12 serves as a bottom transparent conductive electrode of an OLED device. In other embodiments, the layer of doped graphene 12 can serve as a top transparent conductive electrode of an OLED device )) or is arranged adjacent a light-emitting or light-receiving region of the exposed surface of the insulative layer.
Regarding Claim 16 (Previously Presented) Adiga, Vijayaraghavan and Chen teach the method as claimed in claim 13, on which this claim is dependent, Adiga and Chen further teach:
wherein the electronic device precursor is an OLED ( Chen, FIG. 5B, 16; [0055], electroluminescent material 16; FIG. 5B, 12; [0026], the layer of doped graphene 12 serves as a bottom transparent conductive electrode of an OLED device ) and wherein step (vii) is not performed (Adiga, [0056], Returning to FIG. 3, at block 330, a portion of the polymer material, the second nitride layer, and the second oxide layer are removed to form a through hole).
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Adiga, in view of Vijayaraghavan, in view of He, in view of Cheng ( Pub. No. US 20150038378 A1 ), hereinafter Cheng.
Regarding Claim 17 (Previously Presented) Adiga, Vijayaraghavan and He teach the method as claimed in claim 2, on which this claim is dependent, Adiga further teaches:
and, optionally, the silicon wafer is removed ( Adiga, FIG. 2B, FIG. 2D, 202 ) or thinned to less than 10 nm in step (vi) and a third electrical contact is formed, on the exposed surface ( Adiga, [0029], a cavity 224 in the substrate 202 exposing the second oxide layer 206 ) of the insulative layer ( Adiga, FIG. 2D, 206 ) or on the thinned silicon wafer ( Adiga, FIG. 2D, 202; [0025], substrate 202 ).
Adiga, Vijayaraghavan and He fail to teach:
wherein the electronic device precursor is a biosensor device precursor, wherein no further layers are formed in step (iv), wherein first and second electrical contacts are formed on the graphene monolayer or multi-layer structure in step (iv), wherein the method comprises depositing a biologically sensitive material between the first and second electrical
contacts on an exposed surface of the graphene monolayer or multi-layer structure after step (vii),
and, optionally, the silicon wafer is removed or thinned to less than 10 nm in step (vi) and a third electrical contact is formed, opposite the biologically sensitive material, on the exposed surface of the insulative layer or on the thinned silicon wafer.
However, Cheng teaches:
wherein the electronic device precursor is a biosensor device precursor ( Cheng, [0043] FIG. 2 shows a sensor 100 utilizing the graphene sheet 10 disposed in a cavity 108 … the sensor 100 is structured as an ion-sensitive field effect transistor (ISFET) … ), wherein no further layers are formed in step (iv), wherein first and second electrical contacts ( Cheng, [0043], electrodes 102, 104 ) are formed on the graphene monolayer or multi-layer structure ( Cheng, [0043], sensor 100 ) in step (iv), wherein the method comprises depositing a biologically sensitive material between the first and second electrical contacts ( Cheng, [0043], electrodes 102, 104 ) on an exposed surface of the graphene monolayer or multi-layer structure after step (vii),
and, optionally, the silicon wafer is removed or thinned to less than 10 nm in step (vi) and a third electrical contact is formed, opposite the biologically sensitive material ( Cheng, [0043], sensor 100 ), on the exposed surface of the insulative layer or on the thinned silicon wafer.
Adiga, Vijayaraghavan, He and Cheng are all considered to be analogous to the claimed invention because they are forming graphene substrate used for electronic devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Adiga, Vijayaraghavan, He ( thin graphene substrate ), to incorporate the teachings of Cheng ( graphene substrate is used as biosensor sheet), to implement a biosensor in which graphene is used for catching specific molecules . Doing so would use graphene as biologically sensitive material in a biosensor, and therefore to reduce the manufacturing cost of biosensor and be able to attach specific molecules.
Claims 19 is rejected under 35 U.S.C. 103 as being unpatentable over Adiga, in view of Vijayaraghavan; in view of Adkisson ( Pub. No. US 20130146846 A1 ), hereinafter Adkisson.
Regarding Claim 19 (Previously Presented) Adiga and Vijayaraghavan teach the method as claimed in claim 1, on which this claim is dependent, Adiga further teaches:
wherein the insulative layer ( Adiga, FIG. 2A, FIG. 2B, 204, 206, 214, 216 ) has a thickness of less than 10 nm (Adiga, [0024], In some embodiments, the first and the second nitride layers are each about 20 nm to 60 nm thick),
(d) either:
forming a third contact on the exposed surface( Adiga, [0029], a cavity 224 in the substrate 202 exposing the second oxide layer 206 ) of the insulative layer ( Adiga, FIG. 2D, 206 ) after step (vi); or
forming a third contact on an exposed surface of the thinned silicon wafer ( Adiga, FIG. 2D, 202; [0025], substrate 202 ) after step (vi).
Adiga and Vijayaraghavan fail to teach:
wherein the electronic device precursor is a transistor device precursor,
wherein the method comprises in step (iv):
(a) forming a dielectric layer on a first portion of the graphene monolayer or multi-layer structure,
(b) forming a first contact on a second portion of the graphene monolayer or multi-layer structure,
(c) forming a second contact on the dielectric layer, and
(d) either:
a third contact,
However, Adkisson teaches:
wherein the electronic device precursor is a transistor ( Adkisson, [0001], graphene field effect transistor (FET) ) device precursor,
wherein the method comprises in step (iv):
(a) forming a dielectric layer ( Adkisson, FIG. 8, 50; [0026], gate dielectric 50 ) on a first portion of the graphene monolayer or multi-layer structure ( Adkisson, FIG. 8, 30; [0021], graphene 30 ),
(b) forming a first contact ( Adkisson, FIG. 8, 45; [0025], source/drain electrodes 45) on a second portion of the graphene monolayer or multi-layer structure ( Adkisson, FIG. 8, 30; [0021], graphene 30 ),
(c) forming a second contact ( Adkisson, FIG. 8, 50; [0026], gate electrodes 55 ) on the dielectric layer ( Adkisson, FIG. 8, 50; [0026], gate dielectric 50 ), and
(d) either:
a third contact ( Adkisson, FIG. 7, 45; [0025], source/drain electrodes 45; FIG. 16, 100, 105; [0037], Wires/interconnects 100 may comprise any suitable conductive material, such as Cu, Al, etc., formed by CVD on the liner 105 in the trenches ),
Adiga, Vijayaraghavan and Adkisson are all considered to be analogous to the claimed invention because they are forming graphene substrate used for electronic devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Adiga, Vijayaraghavan ( thin graphene substrate ), to incorporate the teachings of Cheng ( graphene that functions as a channel in a FET ), to implement a transistor in which graphene is used as channel. Doing so would use graphene due to its high mobility and low noise, and therefore to use graphene as the channel in transistor.
Claims 20 is rejected under 35 U.S.C. 103 as being unpatentable over Adiga, in view of Vijayaraghavan, in view of He, in view of Kawa ( Pub. No. US 20170373134 A1 ), hereinafter Kawa.
Regarding Claim 20 (Previously Presented) Adiga, Vijayaraghavan and He teach the method as claimed in claim 1, on which this claim is dependent, Adiga and He further teach:
wherein the insulative layer ( Adiga, FIG. 2A, FIG. 2B, 204, 206, 214, 216 ) has a thickness of less than 10 nm ( Adiga, [0030], In some embodiments, the third nitride layer is about 20 nm to 60 nm thick ),
and, wherein in step (v) the polymer coating ( Adiga, [0037] ) is formed directly on the second graphene monolayer or multi-layer structure ( Adiga, FIG. 4G, 252; [0059], graphene sheet 252 ) and wherein the polymer coating comprises a polymer ( He, page 2, column on the right, line 13, PMMA ) and a dopant ( He, page 2, column on the right, line 13, F4TCNQ ), wherein the polymer has a first doping effect ( He, page 2, column on the right, line 15, hole-doping ) on graphene and the dopant has an opposite and substantially equal ( He, page 2, column on the right, line 13, charge-neutral graphene ) second doping effect ( He, page 2, column on the right, line 15, electron-doping ) on graphene ( He, page 2, column on the right, line 11, The resulting carrier density could be fine-tuned by the total annealing time. For a concentration of 7% of F4TCNQ in PMMA by weight, charge-neutral graphene is achieved after annealing at T = 160 °C for 5 min. Shorter annealing times yield hole-doping and longer times yield electron-doping (Supplementary Fig. 1) ).
Adiga, Vijayaraghavan and He fails to teach:
wherein the electronic device precursor is a capacitor device precursor,
wherein the method comprises in step (iv):
(a) forming a dielectric layer on a first portion of the graphene monolayer or multi-layer structure,
(b) forming a first contact on a second portion of the graphene monolayer or multi-layer structure,
(c) forming a second graphene monolayer or multi-layer structure on the dielectric layer,
(d) forming a second contact on the second graphene monolayer or multi-layer structure,
However, Kawa teaches:
wherein the electronic device precursor is a capacitor ( Kawa, Abstract, a capacitor device includes 10,000 layers of interleaved graphene separated by 9,999 layers of HfO ) device precursor,
wherein the method comprises in step (iv):
(a) forming a dielectric layer ( Kawa, FIG. 5I, 522; [0049], dielectric material layer 522 ) on a first portion of the graphene ( Kawa, FIG. 5I, 520, 524; [0049], odd conductive layer 520; even conductive layer 524 ) monolayer or multi-layer structure,
(b) forming a first contact ( Kawa, FIG. 5I, 516, 518; [0049], first and second contact pads 516, 518 ) on a second portion of the graphene monolayer or multi-layer structure,
(c) forming a second graphene ( Kawa, FIG. 5I, 520, 524; [0049], odd conductive layer 520; even conductive layer 524 ) monolayer or multi-layer structure on the dielectric layer,
(d) forming a second contact ( Kawa, FIG. 5I, 516, 518; [0049], first and second contact pads 516, 518 ) on the second graphene ( Kawa, FIG. 5I, 520, 524; [0049], odd conductive layer 520; even conductive layer 524 ) monolayer or multi-layer structure,
Adiga, Vijayaraghavan, He and Kawa are all considered to be analogous to the claimed invention because they are forming the graphene substrate used for electronic devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Adiga, Vijayaraghavan, He ( thin graphene substrate ), to incorporate the teachings of Kawa ( 2D material super capacitors ), to implement graphene super capacitors. Doing so would provide a specific process to make graphene capacitor, and therefore an energy storage device that is small in size and has a high energy stored to volume ratio can be fabricated.
Claims 21 – 22 are rejected under 35 U.S.C. 103 as being unpatentable over Adiga, in view of Vijayaraghavan, in view of Polley ( Pub. No. US 20170373134 A1 ), hereinafter Polley.
Regarding Claim 21 (Previously Presented) Adiga and Vijayaraghavan teach the method as claimed in claim 1, on which this claim is dependent, Adiga further teaches:
wherein the insulative layer ( Adiga, FIG. 2A, FIG. 2B, 204, 206, 214, 216 ) has a thickness of less than 50 nm ( Adiga, [0023], third nitride layer is about 20 nm to 60 nm thick ),
Adiga, Vijayaraghavan and He fails to teach:
wherein the electronic device precursor is a Hall-sensor device precursor, wherein the method comprises:
(a) forming a further insulative layer on the graphene monolayer or multi-layer structure in step (iv),
(b) a further step, between steps (iii) and (iv) or between steps (iv) and (v), of shaping the graphene monolayer or multi-layer structure into a Hall-sensor configuration, and
(c) forming a plurality of electrical contacts in direct contact with the graphene monolayer or multilayer structure.
However, Polley teaches:
wherein the electronic device precursor is a Hall-sensor device ( Polley, Abstract, Graphene Hall sensor (GHS) ) precursor, wherein the method comprises:
(a) forming a further insulative layer ( Polley, [0027], another layer of dielectric 108 is formed over the graphene layer ) on the graphene ( Polley, [0027], A layer of graphene 102 ) monolayer or multi-layer structure in step (iv),
(b) a further step, between steps (iii) and (iv) or between steps (iv) and (v), of shaping the graphene monolayer or multi-layer structure into a Hall-sensor configuration ( Polley, [0008], FIG. 1 is an illustration of an exemplary a Graphene Hall sensor (GHS) device ), and
(c) forming a plurality of electrical contacts ( Polley, [0027], Contact regions 106 are formed in contact with the graphene layer ) in direct contact with the graphene monolayer or multilayer structure.
Adiga, Vijayaraghavan and Polley are all considered to be analogous to the claimed invention because they are forming the graphene substrate used for electronic devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Adiga and Vijayaraghavan ( thin graphene substrate ), to incorporate the teachings of Polly ( low-offset graphene Hall sensor ), to implement graphene Hall sensor. Doing so would provide a much higher magnetic sensitivity graphene Hall sensor, because the magnetic sensitivity of Hall sensor is directly related to, and limited by, the electron mobility; silicon typically has an electron mobility of approximately 1500 cm2/(Vs); graphene, by contrast, may have an electron mobility in the range of 4500-40000 cm2/(Vs).
Regarding Claim 22 (Previously Presented) Adiga, Vijayaraghavan and Polley teach the method as claimed in claim 21, on which this claim is dependent, Adiga further teaches:
wherein the insulative layer ( Adiga, FIG. 2A, FIG. 2B, 204, 206, 214, 216 ) has a thickness of less than 10 nm ( Adiga, [0024], irst and the second nitride layers are each about 20 nm to 60 nm thick ), and wherein the method further comprises:
forming one or more wires ( Adiga, [0064], For example, in some embodiments, electrodes could be deposited and patterned after block 125 or after block 140 ) for carrying a current to be sensed on the exposed surface ( Adiga, FIG. 2D, [0029], cavity 224 in the substrate 202 may expose the first side of the second oxide layer 206 ) of the insulative layer ( Adiga, FIG. 2D, 206; [0029], second oxide layer 206 ) after step (vi).
Response to Arguments
Applicant's remarks filed 2/5/2026 have been fully considered but they are not persuasive.
Applicant’s remarks regarding ( Currently Amended ) Claims 1: on page 10, line 15, cited “ Nothing in Adiga directs a skilled person to the method as claimed in which a graphene layer structure is encapsulated between an insulative layer and a polymer coating which is resistant to etching by an etchant that is then used to thin (or completely remove) the underlying silicon wafer. ”; on page 10, line 32, cited “ There is nothing in Vijayaraghavan that teaches any of the essential differences between the method of claim 1 and Adiga as discussed above. ”.
Examiner’s response: please refer to claim 1 in Claim Rejections - 35 USC § 103 of this office action, cited “ However, Vijayaraghavan teaches: wherein the polymer coating is resistant to etching by the etchant ( Vijayaraghavan, [0124], a new PMMA layer (PMMA 950 3 wt % in anisole) is spin-coated (3000 rpm for 60 s) and baked (130° C. for 5 mins) onto the graphene; [0125], The graphene-PMMA membrane with tape support window is then submerged in an aqueous potassium hydroxide solution (30 wt %) for up to 5 hours until the tape support window and graphene-PMMA membrane lifts off the Si/SiO2 substrate and floats on the surface of the solution ). ”. Therefore, Vijayaraghavan teaches wherein the polymer coating is resistant to etching by the etchant.
Applicant’s remarks regarding ( Original ) Claims 24: on page 14, line 11, cited “ Nowhere in Adiga is there disclosed in a single embodiment such a final product that consists of the layers as claimed. As is evident from the novelty of the claimed method, Adiga fails to direct or enable the manufacture of such a thin product … the silicon layer has a thickness of less than 100 nm. ”.
Examiner’s response: please refer to claim 24 in Claim Rejections - 35 USC § 102 of this office action, cited “ optionally, a silicon layer on the second planar surface, the silicon layer having a thickness of less than 100 nm ( Adiga, [0004], a thin spacer sandwiched between two chips with thin (less than about 100 nanometer (nm)) silicon nitride membranes; [0023], first and the second oxide layers are each about 50 nm to 300 nm thick, or about 200 nm thick ). ”. Therefore, Adiga teaches the silicon layer has a thickness of less than 100 nm.
Applicant’s remarks regarding dependent claims of Claims 1: on pages 11 – 13, including claims 2, 6, 9 – 11, 13 – 16, 17, 19, 20, 21 – 22.
Examiner’s response: please refer to claims 2, 6, 9 – 11, 13 – 16, 17, 19, 20, 21-22 in Claim Rejections - 35 USC § 103 of this office action, including:
claim 2, cited “ However, He teaches: wherein the polymer coating comprises a polymer ( He, page 2, column on the right, line 13, PMMA ) and a dopant ( He, page 2, column on the right, line 13, F4TCNQ ), wherein the polymer has a first doping effect ( He, page 2, column on the right, line 15, hole-doping ) on graphene and the dopant has an opposite and substantially equal ( He, page 2, column on the right, line 13, charge-neutral graphene ) second doping effect ( He, page 2, column on the right, line 15, electron-doping ) on graphene ( He, page 2, column on the right, line 11, The resulting carrier density could be fine-tuned by the total annealing time. For a concentration of 7% of F4TCNQ in PMMA by weight, charge-neutral graphene is achieved after annealing at T = 160 °C for 5 min. Shorter annealing times yield hole-doping and longer times yield electron-doping (Supplementary Fig. 1) ). ”.
claim 6, cited “ However, Kil teaches: wherein the insulative layer is formed by ALD ( Kil, [0026], FIG. 5 is a timing diagram showing gas supply to a chamber when the HfO2 and Al2O3 alloyed dielectric layer is formed by employing an atomic layer deposition (ALD) technique in accordance with the first preferred embodiment of the present invention ) and/or in a water-free process ( Kil, [0029], FIG. 7B is a diagram showing an alloyed state of (HfO2)1-x(Al2O3 )x formed by a reaction between a single molecular source gas of Hf-Al and a reaction gas of ozone (O3) ). ”.
claims 9 – 11, cited “ However, Ishiwata teaches: wherein the polymer coating comprises HDPE ( Ishiwata, Abstract, a surface-protection method during chemical etching of a plate material, which comprises sticking a radiation-curable adhesive tape onto the area of plate material where etching should not be effected; column 7, line 6, The radiation-curable adhesive was coated onto the surface of a 100 µm-thick film support made of a high-density polyethylene resin; column 7, line 24, This radiation-curable adhesive tape was stuck onto a silicon wafer; column 7, line 30, Then the wafer was dipped for 5 min in an etching liquid of a mixture of nitric acid (concentration: 61%) and hydrofluoric acid (concentration: 46%) (mixing volume ratio: 10:1), to etch the wafer ). ”.
claims 13 – 16, cited “ However, Chen teaches: wherein the method comprises forming a light sensitive or light emitting structure ( Chen, FIG. 5B, 16; [0055], electroluminescent material 16 ) on a first portion of the graphene monolayer or multi-layer structure ( Adiga, FIG. 2I, 252 ) in step (iv), and forming a first contact ( Chen, FIG. 5B, 18; [0058], cathode material 18 ) on the light sensitive or light emitting structure ( Chen, FIG. 5B, 16 ) in step (iv), and forming a second contact (Chen, FIG. 5B, 12):
(a) on the exposed surface of the insulative layer after step (vi); or
(b) on a second portion of the graphene monolayer or multi-layer structure ( Chen, FIG. 5B, 12; [0026], the layer of doped graphene 12 serves as a bottom transparent conductive electrode of an OLED device. In other embodiments, the layer of doped graphene 12 can serve as a top transparent conductive electrode of an OLED device ) in step (iv); or
(c) on a second portion of the graphene monolayer or multi-layer structure after step (vii). ”.
claim 17, cited “ However, Cheng teaches: wherein the electronic device precursor is a biosensor device precursor ( Cheng, [0043] FIG. 2 shows a sensor 100 utilizing the graphene sheet 10 disposed in a cavity 108 … the sensor 100 is structured as an ion-sensitive field effect transistor (ISFET) … ), wherein no further layers are formed in step (iv), wherein first and second electrical contacts ( Cheng, [0043], electrodes 102, 104 ) are formed on the graphene monolayer or multi-layer structure ( Cheng, [0043], sensor 100 ) in step (iv), wherein the method comprises depositing a biologically sensitive material between the first and second electrical contacts ( Cheng, [0043], electrodes 102, 104 ) on an exposed surface of the graphene monolayer or multi-layer structure after step (vii),
and, optionally, the silicon wafer is removed or thinned to less than 10 nm in step (vi) and a third electrical contact is formed, opposite the biologically sensitive material ( Cheng, [0043], sensor 100 ), on the exposed surface of the insulative layer or on the thinned silicon wafer. ”.
claim 19, cited “ However, Adkisson teaches: wherein the electronic device precursor is a transistor ( Adkisson, [0001], graphene field effect transistor (FET) ) device precursor,
wherein the method comprises in step (iv):
(a) forming a dielectric layer ( Adkisson, FIG. 8, 50; [0026], gate dielectric 50 ) on a first portion of the graphene monolayer or multi-layer structure ( Adkisson, FIG. 8, 30; [0021], graphene 30 ),
(b) forming a first contact ( Adkisson, FIG. 8, 45; [0025], source/drain electrodes 45) on a second portion of the graphene monolayer or multi-layer structure ( Adkisson, FIG. 8, 30; [0021], graphene 30 ),
(c) forming a second contact ( Adkisson, FIG. 8, 50; [0026], gate electrodes 55 ) on the dielectric layer ( Adkisson, FIG. 8, 50; [0026], gate dielectric 50 ), and
(d) either:
a third contact ( Adkisson, FIG. 7, 45; [0025], source/drain electrodes 45; FIG. 16, 100, 105; [0037], Wires/interconnects 100 may comprise any suitable conductive material, such as Cu, Al, etc., formed by CVD on the liner 105 in the trenches ), ”.
claim 20, cited “ However, Kawa teaches: wherein the electronic device precursor is a capacitor ( Kawa, Abstract, a capacitor device includes 10,000 layers of interleaved graphene separated by 9,999 layers of HfO ) device precursor,
wherein the method comprises in step (iv):
(a) forming a dielectric layer ( Kawa, FIG. 5I, 522; [0049], dielectric material layer 522 ) on a first portion of the graphene ( Kawa, FIG. 5I, 520, 524; [0049], odd conductive layer 520; even conductive layer 524 ) monolayer or multi-layer structure,
(b) forming a first contact ( Kawa, FIG. 5I, 516, 518; [0049], first and second contact pads 516, 518 ) on a second portion of the graphene monolayer or multi-layer structure,
(c) forming a second graphene ( Kawa, FIG. 5I, 520, 524; [0049], odd conductive layer 520; even conductive layer 524 ) monolayer or multi-layer structure on the dielectric layer,
(d) forming a second contact ( Kawa, FIG. 5I, 516, 518; [0049], first and second contact pads 516, 518 ) on the second graphene ( Kawa, FIG. 5I, 520, 524; [0049], odd conductive layer 520; even conductive layer 524 ) monolayer or multi-layer structure, ”.
claims 21-22, cited “ However, Polley teaches: wherein the electronic device precursor is a Hall-sensor device ( Polley, Abstract, Graphene Hall sensor (GHS) ) precursor, wherein the method comprises:
(a) forming a further insulative layer ( Polley, [0027], another layer of dielectric 108 is formed over the graphene layer ) on the graphene ( Polley, [0027], A layer of graphene 102 ) monolayer or multi-layer structure in step (iv),
(b) a further step, between steps (iii) and (iv) or between steps (iv) and (v), of shaping the graphene monolayer or multi-layer structure into a Hall-sensor configuration ( Polley, [0008], FIG. 1 is an illustration of an exemplary a Graphene Hall sensor (GHS) device ), and
(c) forming a plurality of electrical contacts ( Polley, [0027], Contact regions 106 are formed in contact with the graphene layer ) in direct contact with the graphene monolayer or multilayer structure. ”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached Monday thru Friday E.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817