Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 19-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oganesian (US PGPub 2013/0164867).
Claim 19: Oganesian teaches (Fig. 10) a sensor device comprising: a carrier substrate (10) having at least one contact via (36,40) for guiding an electrical contact from a bottom surface to a top surface of the carrier substrate and at least one first cavity; an integrated circuit (64) arranged in the first cavity (28); at least one sensor element arranged on or integrated into the integrated circuit; and a first conductor track (50) formed on the carrier substrate and electrically connecting the at least one contact via with the integrated circuit; and an at least partially transparent encapsulation material (46) covering at least the integrated circuit and the first conductor track.
Claim 20: Oganesian teaches (Fig. 10) the carrier substrate comprises at least a second cavity (28) in which an optoelectronic component (56) is arranged.
Claim 21: Oganesian teaches (Fig. 10) the carrier substrate comprises at least one further contact via and a second conductor track (bond wire), and wherein the second conductor track is formed on the carrier substrate and electrically connects the at least one further contact via with the optoelectronic component.
Claim 22: Oganesian teaches (Fig. 10) the first cavity is formed such that a top surface of the integrated circuit does not project beyond the top surface of the carrier substrate.
Claim 23: Oganesian teaches (Fig. 10) at least the at least one first conductor track is formed by a planar interconnect.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, and 9-18 are rejected under 35 U.S.C. 103 as being unpatentable over A Tharumalingam (US PGPub 2016/0307957) in view of Ramasamy (USPGPub 2013/0164867).
Claim 1: A Tharumalingam teaches (Fig. 3) a sensor device comprising: a carrier substrate (304) having at least one contact via (308) for guiding an electrical contact from a bottom surface to a top surface of the carrier substrate; an integrated circuit (106/206/306) arranged on the top surface of the carrier substrate; at least one sensor element arranged on or integrated into the integrated circuit; at least one optoelectronic component (316) arranged on the top surface of the carrier substrate at a distance from the integrated circuit; at least one first electrically conductive contact element arranged on the at least one contact via and electrically connected thereto; a substantially opaque first encapsulation material (330), which encloses the at least one sensor element, the at least one optoelectronic component, the components being electrically connected together [0030] at least one first electrically conductive contact element in lateral direction in such a way that at least one surface of the at least one sensor element and of the at least one optoelectronic component opposite the carrier substrate remains uncovered by the substantially opaque first encapsulation material. A Tharumalingam does not teach at least one first conductor track formed on the substantially opaque first encapsulation material and electrically connecting the at least one first electrically conductive contact element and the integrated circuit, and at least one second conductor track formed on the substantially opaque first encapsulation material and electrically connecting the integrated circuit with the at least one optoelectronic component. Ramasamy teaches at least one first conductor track (210/215) formed on the substantially opaque first encapsulation material (201) and electrically connecting the at least one first electrically conductive contact element and the integrated circuit, and at least one second conductor track (210/215) formed on the substantially opaque first encapsulation material and electrically connecting the integrated circuit with the at least one optoelectronic component to reduce package sizes [0019, 0009]. Using these types of connections are common in the art as further evidenced by references listed in PTO-892. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by A Tharumalingam to have had the conductor tracks a claimed to help reduce package size as taught by Ramasamy [0009, 0019] as well as them being common in the art.
Claim 2: A Tharumalingam teaches (Fig. 5) a structured layer of a substantially opaque material (338) is arranged on the substantially opaque first encapsulation material (332) in such a way that the photosensitive region of the at least one sensor element and the light-emitting region of the at least one optoelectronic component remain uncovered of the substantially opaque material of the structured layer.
Claim 3: A Tharumalingam teaches (Fig. 5) the structured layer of the substantially opaque material comprises a photostructurable lacquer, in particular a black photostructurable epoxy or acrylic lacquer. Black photosturcurable epoxies are well known in the optical semiconductor art for blocking unwanted light and crosstalk between devices.
Claim 4: A Tharumalingam teaches (Fig. 3) at least the photosensitive region of the at least one sensor element and the light-emitting region of the at least one optoelectronic component remain uncovered.
Claim 5: A Tharumalingam teaches (Fig. 3) the photosensitive region of the at least one sensor element and the light- emitting region of the at least one optoelectronic component are covered by an at least partially transparent material (310,320).
Claim 6: A Tharumalingam teaches (Fig. 3) a total height
Claim 7: A Tharumalingam teaches the at least one optoelectronic device is formed by an infrared light emitting VCSEL [0025]or an infrared light emitting LED.
Claim 9: A Tharumalingam teaches (Fig. 5) at least one second electrically conductive contact elementsubstrate remain uncovered by the substantially opaque second encapsulation material.
Claim 10: Ramasamy teaches (Fig. 7) at least one third conductor track is formed on the substantially opaque second encapsulation material electrically connecting the at least one sensor element with the at least one second electrically conductive contact element.
Claim 11: A Tharumalingam teaches (Fig. 3) a window is formed in the substantially opaque second encapsulation material above the at least one optoelectronic component.
Claim 12: A Tharumalingam teaches (Fig. 3) [0038-0038] wherein the window is filled with an at least partially transparent material.
Claim 13: Ramasamy teaches (Fig. 13) an at least partially transparent encapsulation material
Claim 14: A Tharumalingam teaches (Fig. 3) the substantially opaque first encapsulation material
Claim 15: Ramasamy teaches (Fig. 7) at least one of the at least one first, the at least one second and the at least one third conductor track is formed by a planar interconnect.
Claim 16: Ramasamy teaches (Fig. 7) at least one of the at least one first and the at least one second electrically conductive contact element is formed by a metallic ellipsoid.
Claim 17: Ramasamy teaches (Fig. 7) at least one of the at least one first and the at least one second electrically conductive contact element is formed by at least two stud bumps stacked on top of each other or by at least two nailheads produced by a ball bonding method. “The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Claim 18: Ramasamy teaches (Fig. 7) at least one of the at least one first and the at least one second electrically conductive contact element is formed by an opening through the substantially opaque first encapsulation material the side surfaces of which are metallized.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over A Tharumalingam (US PGPub 2016/0307957) in view of Ramasamy (USPGPub 2013/0164867) as applied to claim 1 above and further in view of Liu et al. (US PGPub 2017/0033062)
Regarding claim 8, as described above, A Tharumalingam and Ramasamy substantially read on the invention as claimed, except A Tharumalingam and Ramasamy do not teach at least one sensor element is arranged on the integrated circuit and the substantially opaque first encapsulation material is substantially flush with a surface of the at least one optoelectronic component and of the integrated circuit opposite the carrier substrate. Liu teaches at least one sensor element is arranged on the integrated circuit and the substantially opaque first encapsulation material is substantially flush with a surface of the at least one optoelectronic component and of the integrated circuit opposite the carrier substrate to provide a flat surface for additional interconnect layers on the device (Fig. 3d) [0046-0047]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by A Tharumalingam and Ramasamy to have had the encapsulation material flush with the surface of the optoelectronic component and the IC to provide a planar surface for subsequent RL layers are taught by Liu (Fig. 3d) [0046-0047].
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Oganesian (US PGPub 2013/0164867) as applied to claim 19 above, and further in view of A Tharumalingam (US PGPub 2016/0307957).
Regarding claim 24, as described above, Oganesian substantially reads on the invention as claimed, except Oganesian does not teach at least one optoelectronic component is formed by an infrared light emitting VCSEL or an infrared light emitting LED. A Tharumalingam teaches at least one optoelectronic component is formed by an infrared light emitting VCSEL or an infrared light emitting LED which are common the art of optical semiconductors. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have specified the use of VCSEL or an infrared light emitting LED as they are common in the art.
Claims 25-27 and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over A Tharumalingam (US PGPub 2016/0307957).
Claim 25: A Tharumalingam teaches (Fig. 3) (see claim 1) sensor device comprising: a lead frame having at least a first and a second electrical contact region; an integrated circuit arranged on the top surface of the first electrical contact region; at least one sensor element integrated in the integrated circuit; at least one optoelectronic component arranged on the integrated circuit at a distance from the at least one sensor element; a first electrical lead, in particular a bonding wire, electrically connecting the second electrical contact region with the integrated circuit; and a substantially opaque first encapsulation material enclosing the at least one sensor element and the at least one optoelectronic component in lateral direction in such a way that at least one surface of the at least one sensor element and of the at least one optoelectronic component opposite the lead frame remains uncovered by the substantially opaque first encapsulation material. One of ordinary skill in the art would be able to swap out a PCB for a leadframe. Additionally applicant’s specification use the same substrate (2) to depict said leadframe and carrier substrate.
Claim 26: A Tharumalingam teaches (Fig. 3) a cavity or window is formed in the substantially opaque first encapsulation material above the at least one sensor element.
Claim 27: A Tharumalingam teaches (Fig. 3) the window or cavity is filled with an at least partially transparent material.
Claim 30: A Tharumalingam teaches (Fig. 3) at least a second electrical contact of the at least one optoelectronic component is electrically connected to the integrated circuit by means of a bonding wire.
Claim 31: A Tharumalingam teaches (Fig. 3) the at least one optoelectronic component is in the form of a flip chip. Flip chip is commonly known in the art of semiconductors.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over A Tharumalingam (US PGPub 2016/0307957) as applied to claim 25 above and further in view of Liu et al. (US PGPub 2017/0033062).
Regarding claim 28, as described above Oganesian substantially reads on the invention as claimed, except Oganesian does not teach the substantially opaque first encapsulation material.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over A Tharumalingam (US PGPub 2016/0307957) as applied to claim 25 above and further in view of Ramasamy (USPGPub 2013/0164867).
Regarding claim 29, as described above A Tharumalingam substantially reads on the invention as claimed, except A Tharumalingam does not teach at least a first electrical contact of the at least one optoelectronic component is electrically connected to the integrated circuit by means of a planar interconnect. Ramasamy teaches a first electrical contact of the at least one optoelectronic component is electrically connected to the integrated circuit by means of a planar interconnect to reduce package sizes [0019, 0009]. Using these types of connections are common in the art as further evidenced by references listed in PTO-892. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by A Tharumalingam to have had planar contacts a claimed to help reduce package size as taught by Ramasamy [0009, 0019] as well as them being common in the art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814