DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the Amendment filed on 01/14/2026.
In the instant Amendment, claim 12 has been amended; and claims 1, 8, and 15 are independent claims. Claims 1-20 have been examined and are pending. This Action is made Non-Final.
Response to Arguments
The rejection of claim 12 under 35 U.S.C. § (b) is withdrawn as the claims have been amended.
Applicants’ arguments with respect to claims 1-14 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 1-2 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 2022/0150260; Hereinafter “Zhang”).
Regarding claim 1, Zhang teaches a memory module, comprising:
a plurality of dynamic random access memory (DRAM) devices (Zhang: Para. [0173], Further, in an optional embodiment, there are one or more processors, and there are one or more memories. Optionally, the memory may be integrated with the processor, or the memory and the processor are separately disposed. The memory may include a read-only memory (ROM) and a random access memory (RAM), and provide instructions and data to the processor. Para. [0174], The volatile memory may be a RAM that is used as an external cache. For example, but not limitation, many forms of RAMs are available, for example, a static random-access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random-access memory (SDRAM), a double data rate (DDR) synchronous dynamic random-access memory (DDR SDRAM), an enhanced synchronous dynamic random-access memory (ESDRAM), a synchlink dynamic random-access memory (SLDRAM), and a direct Rambus (DR) random-access memory (DR RAM); and,
a first integrated circuit including nonvolatile memory to store a cryptographically signed certificate that includes at least one value that is based on at least a first binding data value physically originating from within a second integrated circuit on the memory module (Zhang: Para. [0015], where the ciphertext is obtained after at least two of a plurality of pieces of hardware carried on a physical carrier respectively encrypt the first verification data by using respective keys, and the binding relationship information is used to indicate a binding relationship between the at least two pieces of hardware., Para. [0114], In FIG. 7, the AIK certificate includes a basic field and an extension field. The basic field includes a version, a serial number, an issuer signature algorithm, subject public key information, and an issuer's signature. The public key information stores the AIK public key, and the issuer signature is a digital signature obtained after the CA signs the binding relationship. Para. [0054], Para. [0015], Para. [0016], Para. [0017], and storing the binding relationship information includes registering the keys of the at least two pieces of hardware to obtain a notarization certificate, and storing the notarization certificate, where the notarization certificate includes the binding relationship between the keys corresponding to the at least two pieces of hardware).
Regarding claim 2, Zhang teaches the memory module of claim 1, wherein the second integrated circuit is one of a plurality of DRAM devices (Zhang: Para. [0010], the keys corresponding to the at least two pieces of hardware are generated by the at least two pieces of hardware respectively based on respective hardware identifiers. Para. [0062], The hardware includes but is not limited to a processor, a microcontroller unit (MCU), a trusted platform module (TPM), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), and the like. Para. [0173], Further, in an optional embodiment, there are one or more processors, and there are one or more memories. Optionally, the memory may be integrated with the processor, or the memory and the processor are separately disposed. Para. [0174]).
Regarding claim 6, Zhang teaches the memory module of claim 1, wherein the cryptographically signed certificate is further based on a second binding data value physically originating from within a third integrated circuit on the memory module (Zhang: Para. [0031], the second obtaining module is configured to register the keys of the at least two pieces of hardware to obtain a notarization certificate, where the notarization certificate includes the binding relationship between the keys corresponding to the at least two pieces of hardware, and further includes a digital signature of the binding relationship; the storage module is configured to store the notarization certificate; Para. [0035], and the ciphertext is obtained after the at least two pieces of hardware respectively encrypt the first verification data by using respective private keys, and the binding relationship information is obtained based on a binding relationship between public keys corresponding to the at least two pieces of hardware. [2nd hardware meets third IC limitation]).
Regarding claim 7, Zhang teaches the memory module of claim 6, wherein the cryptographically signed certificate is based on a digest function based on the first binding data value and the second binding data value (Zhang: Para. [0008], where the notarization certificate includes a binding relationship between the keys corresponding to the at least two pieces of hardware, and further includes a digital signature of the binding relationship; the verifying the ciphertext and the binding relationship information includes verifying, based on the digital signature in the notarization certificate, whether the binding relationship included in the binding relationship information is correct. Para. [0007], [signature calculation may include hash or digest function]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2022/0150260; Hereinafter “Zhang”) in view of Ware et al. (US 2017/0103800; Hereinafter “Ware”).
Regarding claim 3, Zhang teaches the memory module of claim 1. Zhang does not explicitly teach wherein the second integrated circuit is a registered clock driver (RCD) integrated circuit device.
In an analogous art, Ware teaches wherein the second integrated circuit is a registered clock driver (RCD) integrated circuit device (Ware: Para. [0029], An address-buffer component 140, alternatively called a “Registered Clock Driver” (RCD), relays module commands received from controller component 110 via primary address interface DCA[26:0] to each memory component 130 via one of three secondary command interfaces QCAB, QCCD, and QCEF. Address-buffer component 140 also controls the flow of data through data-buffer components 135 via a common buffer interface BCOM.).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Ware with the system and method of Zhang to include wherein the second integrated circuit is a registered clock driver (RCD) integrated circuit device because this functionality provides forms of error detection and correction to manage DRAM errors while controlling data flow through components (Ware: Para. [0004]).
Claim(s) 4, 8-10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2022/0150260; Hereinafter “Zhang”) in view of Shaeffer et al. (US 10,381,067; Hereinafter “Shaeffer”).
Regarding claim 4, Zhang teaches the memory module of claim 1. Zhang does not explicitly teach wherein the second integrated circuit is a data buffer integrated circuit.
In an analogous art, Shaeffer teaches wherein the second integrated circuit is a data buffer integrated circuit (Shaeffer: Fig. 11, Col. 14, Lines 19-52, FIG. 11 illustrates a device 1100 including a plurality of integrated circuit memory dies 1101a-d and a buffer die 1100a housed in or upon a common package 1110 according to embodiments. As described herein in other embodiments and illustrated in FIGS. 12-15 and 35, a plurality of integrated circuit memory dies 1101a-d and buffer die 1100a are disposed in multiple package type embodiments. For example, a plurality of integrated circuit memory dies 1101a-d and a buffer die 1100a may be stacked, on a flexible tape, side-by-side or positioned in separate packages on a device substrate.)
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Shaeffer with the system and method of Zhang to include wherein the second integrated circuit is a data buffer integrated circuit because this functionality provide signals, including control/address/clock information and data, between a plurality of integrated circuit memory dies and a device interface (Shaeffer: Col. 14, Lines 19-52).
Regarding claim 8, Zhang teaches a memory module, comprising: having nonvolatile memory to store a cryptographically signed certificate that certifies at least one value that is based on at least a first binding data value to be received from a second integrated circuit disposed on the substrate (Zhang: Para. [0053], generating, by the computing device, an identifier (e.g., a public identifier IDLs public), a certificate (e.g., ID.sub.L1 certificate), and a key (e.g., K.sub.L1 public), wherein the identifier is associated with an identity of the computing device, and the certificate is generated using the message; and sending, by the computing device, the identifier, the certificate, and the key to the host device, wherein the host device is configured to verify the identity of the computing device using the identifier, the certificate, and the key. Para. [0054], Para. [0015], Para. [0016]); and
a plurality of dynamic random access memory (DRAM) devices (Zhang: Para. [0092], In one embodiment, the memory regions 111, 113, . . . , 119 can include any combination of different types of non-volatile memory components. In some embodiments, the volatile memory 123 can be, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM). Fig. 1, Fig. 4-5, Fig. 8).
Zhang does not explicitly teach a substrate having a memory module form factor; a serial presence detect (SPD) device, disposed on the substrate, disposed on the substrate.
In an analogous art, Shaeffer teaches a substrate having a memory module form factor; a serial presence detect (SPD) device, disposed on the substrate (Shaeffer: Fig. 16, Col. 15, Lines 62-67 to Col. 16, Lines 1-2, FIG. 16 illustrates a memory module having an SPD 1603 according to an embodiment. Memory module 1610 includes a plurality of integrated circuit memory devices (or dies) and buffer devices (or dies) disposed on substrate 930 along with SPD 1603. FIG. 16 illustrates a memory module 1610 having a single SPD 1603 that can be accessed by each buffer device 100a-b positioned on substrate 930. Signal path 1601 allows access to SPD 1603 from connector interface 920 and one or more buffers 100a-b. In an embodiment, signal path 1601 is a bus. SPD 1603 may have configuration and/or parameter information written to or read by a master by way of connector interface 920 and signal path 1601. Likewise, buffers 100a-b may write to or read from SPD 1603 via signal path 1601.),
a plurality of dynamic random access memory (DRAM) devices disposed on the substrate (Shaeffer: Col. 7, Lines 7-20, Col. 11, Lines 1-18, FIG. 9A illustrates a top view of a memory module topology including a plurality of integrated circuit memory devices and a plurality of integrated circuit buffer devices coupled to a connector interface.).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Shaeffer with the system and method of Zhang to include a substrate having a memory module form factor; a serial presence detect (SPD) device, disposed on the substrate, disposed on the substrate because this functionality provides a form factor to include multiple integrated circuits on a single substrate (Shaeffer: Col. 11, Lines 1-13).
Regarding claim 9, Zhang, in combination with Shaeffer, teaches the memory module of claim 8, wherein the first binding data value is received from a first DRAM device of the plurality of DRAM devices (Zhang: Para. [0053], generating, by the computing device, an identifier (e.g., a public identifier IDLs public), a certificate (e.g., ID.sub.L1 certificate), and a key (e.g., K.sub.L1 public), wherein the identifier is associated with an identity of the computing device, and the certificate is generated using the message; and sending, by the computing device, the identifier, the certificate, and the key to the host device, wherein the host device is configured to verify the identity of the computing device using the identifier, the certificate, and the key. Para. [0054], Para. [0015], Para. [0016]; Shaeffer: Col. 7, Lines 7-20, Col. 11, Lines 1-18, FIG. 9A illustrates a top view of a memory module topology including a plurality of integrated circuit memory devices and a plurality of integrated circuit buffer devices coupled to a connector interface. [binding data of Zhang revied from one of plurality of IC devices]).
Regarding claim 10, Zhang, in combination with Shaeffer, teaches the memory module of claim 9, wherein the first binding data value is based on configuration information that is to be received from the first DRAM device (Zhang: Para. [0173], Optionally, the memory may be integrated with the processor, or the memory and the processor are separately disposed. The memory may include a read-only memory (ROM) and a random access memory (RAM), and provide instructions and data to the processor. The memory may further include a nonvolatile random access memory (NVRAM). For example, the memory may further store information about a device type. [device type meets configuration information limitation] Zhang: Para. [0053], Para. [0054], Para. [0015], Para. [0016]).
Regarding claim 13, Zhang, in combination with Shaeffer, teaches the memory module of claim 8, wherein the cryptographically signed certificate that certifies at least a second value that is based on at least a second binding data value to be received from a third integrated circuit disposed on the substrate (Zhang: Para. [0031], the second obtaining module is configured to register the keys of the at least two pieces of hardware to obtain a notarization certificate, where the notarization certificate includes the binding relationship between the keys corresponding to the at least two pieces of hardware, and further includes a digital signature of the binding relationship; the storage module is configured to store the notarization certificate; Para. [0035], and the ciphertext is obtained after the at least two pieces of hardware respectively encrypt the first verification data by using respective private keys, and the binding relationship information is obtained based on a binding relationship between public keys corresponding to the at least two pieces of hardware. [2nd hardware meets third IC limitation]).
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2022/0150260; Hereinafter “Zhang”) in view of Block et al. (US 2020/0099536; Hereinafter “Block”).
Regarding claim 5, Zhang teaches the memory module of claim 1, wherein the cryptographically signed certificate is stored in the first integrated circuit during a manufacturing process of the memory module. Zhang does not explicitly teach wherein the cryptographically signed certificate is stored in the first integrated circuit during a manufacturing process of the memory module.
In an analogous art, Block teaches wherein the cryptographically signed certificate is stored in the first integrated circuit during a manufacturing process of the memory module (Block: Claim 24, wherein the TPM on each of the compute nodes is provisioned with a platform certificate and a signed attestation key (AK) certificate, and wherein the AK certificate of each compute node's TPM is created by the TPM utilizing a network connection to a trusted certificate authority (CA) and stored in the TPM at manufacturing TPM provisioning time).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Block with the system and method of Zhang to include wherein the cryptographically signed certificate is stored in the first integrated circuit during a manufacturing process of the memory module because this functionality enhances security in multi-nodal systems by utilizing provisioned node certificates (Block: Para. [0001]).
Claim(s) 14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2022/0150260; Hereinafter “Zhang”) in view of Shaeffer et al. (US 10,381,067; Hereinafter “Shaeffer”) in view of Ware et al. (US 2017/0103800; Hereinafter “Ware”).
Regarding claim 14, Zhang, in combination with Shaeffer, teaches the memory module of claim 13, wherein the second binding data value is a device identification value (Zhang: Para. [0173], Optionally, the memory may be integrated with the processor, or the memory and the processor are separately disposed. The memory may include a read-only memory (ROM) and a random access memory (RAM), and provide instructions and data to the processor. The memory may further include a nonvolatile random access memory (NVRAM). For example, the memory may further store information about a device type. [device type meets device identification value limitation] Zhang: Para. [0053], Para. [0054], Para. [0015], Para. [0016]).
Zhang, in combination with Shaeffer, does not explicitly teach the third integrated circuit is a register clock driver device.
In an analogous art, Ware teaches the third integrated circuit is a register clock driver device (Ware: Para. [0029], An address-buffer component 140, alternatively called a “Registered Clock Driver” (RCD), relays module commands received from controller component 110 via primary address interface DCA[26:0] to each memory component 130 via one of three secondary command interfaces QCAB, QCCD, and QCEF. Address-buffer component 140 also controls the flow of data through data-buffer components 135 via a common buffer interface BCOM.).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Ware with the system and method of Zhang and Shaeffer to include the third integrated circuit is a register clock driver device because this functionality provides forms of error detection and correction to manage DRAM errors while controlling data flow through components (Ware: Para. [0004]).
Claim(s) 15-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2022/0150260; Hereinafter “Zhang”) in view of Patrick Koeberl et al. (“Evaluation of a PUF Device Authentication Scheme on a Discrete 0.13um SRAM”, November 27, 2011, Trusted Systems, Springer Berlin Heidelberg, Berlin, Pages 271-288.; Hereinafter “Koeberl”).
Regarding claim 15, Zhang teaches a method of authenticating a memory module, comprising:
receiving, from a nonvolatile memory in a first integrated circuit that is disposed on the memory module, a cryptographically signed certificate that certifies at least one value that is based on at least a first binding data value that may be received from a second integrated circuit disposed on the memory module (Zhang: Para. [0015], where the ciphertext is obtained after at least two of a plurality of pieces of hardware carried on a physical carrier respectively encrypt the first verification data by using respective keys, and the binding relationship information is used to indicate a binding relationship between the at least two pieces of hardware., Para. [0114], In FIG. 7, the AIK certificate includes a basic field and an extension field. The basic field includes a version, a serial number, an issuer signature algorithm, subject public key information, and an issuer's signature. The public key information stores the AIK public key, and the issuer signature is a digital signature obtained after the CA signs the binding relationship. Para. [0054], Para. [0015], Para. [0016], Para. [0017], and storing the binding relationship information includes registering the keys of the at least two pieces of hardware to obtain a notarization certificate, and storing the notarization certificate, where the notarization certificate includes the binding relationship between the keys corresponding to the at least two pieces of hardware);
receiving, from the second integrated circuit, at least a second binding data value (Zhang: Para. [0173], Optionally, the memory may be integrated with the processor, or the memory and the processor are separately disposed. The memory may include a read-only memory (ROM) and a random access memory (RAM), and provide instructions and data to the processor. The memory may further include a nonvolatile random access memory (NVRAM). For example, the memory may further store information about a device type. [device type meets device identification value limitation] Zhang: Para. [0053], Para. [0054], Para. [0015], Para. [0016]).
Zhang does not explicitly teach based on the first binding data value, second binding data value, and the cryptographically signed certificate, determine an authenticity indicator associated with the second integrated circuit.
In an analogous art, Koeberl teaches based on the first binding data value, second binding data value, and the cryptographically signed certificate, determine an authenticity indicator associated with the second integrated circuit (Koeberl: Page 275, Sec. 3.1, For our applications we can divide this off-line authentication scheme on two phases: an enrolment phase Figure 2 and an evaluation phase Figure 3. Page 276 The verifier then reads the certificate stored in the NVM of the device from a first integrated circuit of a memory module and a binding value from a second integrated circuit).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Koeberl with the system and method of Zhang to include based on the first binding data value, second binding data value, and the cryptographically signed certificate, determine an authenticity indicator associated with the second integrated circuit because this functionality provides improvements to the device authentication scheme (Koeberl: Page 277, Section 3.2).
Regarding claim 16, Zhang, in combination with Koeberl, teaches the method of claim 15, wherein the authenticity indicator is associated with the second integrated circuit being authentic (Koeberl: Page 272, In their scheme, each device is embedded with a small SRAM PUF which serves as an intrinsic unclonable fingerprint of the device. At manufacturing time, the manufacturer evaluates the PUF and extracts the m-bit PUF result into a short k-bit device ID. The manufacturer then creates a device certificate based on the device ID. Any verifier can authenticate the device by evaluating the SRAM PUF, re-computing the device ID, and verifying the device certificate. This scheme is simple and practical as it does not require any online databases or onchip cryptographic operations. For hardware devices which already have SRAM and non-volatile storage embedded, this scheme takes almost no additional cost.).
Regarding claim 17, Zhang, in combination with Koeberl, teaches the method of claim 15, wherein the authenticity indicator is associated with at least one of the first integrated circuit and the second integrated circuit being counterfeit (Koeberl: Page 276, Both the enrolment and evaluation phases use the post-processing functions to map an m-bit string to a k-bit string. The security of the device authentication scheme [8] relies on the value of m. They assume that it is too expensive or uneconomical for an adversary to embed an m-bit PUF simulator into the nonvolatile memory or circuit of a counterfeit device. Thus it is important to keep m reasonably large, while keeping k small to reduce the size of device certificate.).
Regarding claim 20, Zhang, in combination with Koeberl, teaches the method of claim 15, wherein the second integrated circuit is a dynamic random access memory (DRAM) device (Zhang: Para. [0173], Further, in an optional embodiment, there are one or more processors, and there are one or more memories. Optionally, the memory may be integrated with the processor, or the memory and the processor are separately disposed. The memory may include a read-only memory (ROM) and a random access memory (RAM), and provide instructions and data to the processor. Para. [0174], The volatile memory may be a RAM that is used as an external cache. For example, but not limitation, many forms of RAMs are available, for example, a static random-access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random-access memory (SDRAM), a double data rate (DDR) synchronous dynamic random-access memory (DDR SDRAM), an enhanced synchronous dynamic random-access memory (ESDRAM), a synchlink dynamic random-access memory (SLDRAM), and a direct Rambus (DR) random-access memory (DR RAM)).
Claim(s) 18-19 are rejected under 35 U.S.C. 103 as being unpatentable as being unpatentable over Zhang et al. (US 2022/0150260; Hereinafter “Zhang”) in view of Patrick Koeberl et al. (“Evaluation of a PUF Device Authentication Scheme on a Discrete 0.13um SRAM”, November 27, 2011, Trusted Systems, Springer Berlin Heidelberg, Berlin, Pages 271-288.; Hereinafter “Koeberl”) in view of Ware et al. (US 2017/0103800; Hereinafter “Ware”).
Regarding claim 18, Zhang, in combination with Koeberl, teaches the method of claim 15. Zhang, in combination with Koeberl, does not explicitly teach wherein the second integrated circuit is a registered clock driver.
In an analogous art, Koeberl teaches wherein the second integrated circuit is a registered clock driver (Ware: Para. [0029], An address-buffer component 140, alternatively called a “Registered Clock Driver” (RCD), relays module commands received from controller component 110 via primary address interface DCA[26:0] to each memory component 130 via one of three secondary command interfaces QCAB, QCCD, and QCEF. Address-buffer component 140 also controls the flow of data through data-buffer components 135 via a common buffer interface BCOM.).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Ware with the system and method of Zhang and Koeberl to include wherein the second integrated circuit is a registered clock driver because this functionality provides forms of error detection and correction to manage DRAM errors while controlling data flow through components (Ware: Para. [0004]).
Regarding claim 19, Zhang, in combination with Koeberl and Ware, teaches the method of claim 18, wherein the second binding data value includes device identification information (Zhang: Para. [0173], Optionally, the memory may be integrated with the processor, or the memory and the processor are separately disposed. The memory may include a read-only memory (ROM) and a random access memory (RAM), and provide instructions and data to the processor. The memory may further include a nonvolatile random access memory (NVRAM). For example, the memory may further store information about a device type. [device type meets device identification information limitation]).
Allowable Subject Matter
Regarding Claims 11-12, Claims 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Giddins whose telephone number is (571)272-7993. The examiner can normally be reached on Monday - Friday, 9:00 AM - 5:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Linglan Edwards can be reached at (571) 270-5440. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NELSON S. GIDDINS/ Primary Examiner, Art Unit 2408
Prosecution Insights