DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 09/02/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
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Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshida (US 2012/0206658 A1, which a prior art of record).
Yoshida discloses (in Figs. 2 and 4) display device comprising:
a plurality of pixel circuits arranged in a matrix (e.g., circuits including 17a/17b/17A/17B, see [0053] and Exhibit A), each of the plurality of pixel circuits
including:
a holding capacitor Cb/Ca (Figs. 2, 4 and [0053]) formed of an upper electrode 7ab formed in an island shape (Figs. 2 and 4), a lower electrode 37a/37b (Figs. 2 and 4, note “upper” and “lower” are relative terms depending on some chosen point of references, e.g., when Fig. 4 is viewed upside-down), and a first insulating layer 22 (Fig. 4 and [0070 sandwiched between the upper electrode 7ab and the lower electrode 37a/37b, wherein an entirety of an outer peripheral end of the upper electrode 7a overlaps with the lower electrode 37a/37b in a plan view (Fig. 4); and
a drive transistor (see “drive transistor” in Exhibit A) including a gate electrode connected to the holding capacitor (i.e., the gate electrode of the “drive transistor” is at least capacitively coupled, or connect through a gate insulating layer, to the holding capacitor in Exhibit A); and
a first connection wiring line (Exhibit A, “first connection wiring”) electrically e.g., at least 37b in Fig. 4 and Exhibit A) of the one (17b in Exhibit A) of the plurality of pixel circuits and the lower electrode of the other one (17B in Exhibit A) of the plurality of the pixel circuits that are adjacent to each other in the row direction.
Therefore, Yoshida anticipates claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Lee (US 2017/0012094 A1, which is a prior art of record).
Regarding claim 2:
Yoshida anticipates claim 1 but is silent with respect to metallization layers of the display device; accordingly, Yoshida does not disclose the limitations in the current claim.
Lee teaches, in a display device (Fig. 9), first to fourth metal layers sequentially provided on a semiconductor layer A2 [0088] via an insulating layer GI1 [0098], wherein an upper electrode CM2 [0105] is included in the third metal layer, and a lower electrode Cst2 [0073] and a first connection wiring line CM1 [0103] are included in the second metal layer. In other words, Lee discloses first (Cst1), second (Cst2), third (CM2), and fourth (120) metal layers sequentially provided on a semiconductor layer (e.g., S1/G1/A1/D1 in Fig. 9), each of the first, second, third, and fourth metal layers having a corresponding insulating layer provided beneath, wherein an upper electrode CM2 (Fig. 9) is included in the third metal layer (CM2), and a lower electrode Cst2 (Fig. 9) and a first connection wiring line (CM1) are included in the second metal layer.
Since Yoshida is silent with respect to metallization layers, it would have been obvious to one of ordinary skill in the art to incorporate metallization layers, as taught by Lee, because Lee metallization layers are well suited for a display device, and the incorporation would provide a complete, functional device.
Regarding claims 3-10 and 16:
re claim 3, Kim discloses wherein the first metal layer includes an auxiliary electrode Cst1 (Fig. 9 and [0067]) formed in an island shape, and the auxiliary electrode Cst1, the lower electrode Cst2, and a second insulating layer GI2 [0100] sandwiched between the auxiliary electrode Cst1 and the lower electrode Cst2 form an auxiliary holding capacitor Cst;
re claim 4, Kim discloses wherein a thickness of the second insulating layer GI2 (e.g., a thickness immediately to the right edge of “Cst1” in Fig. 9) is larger than a thickness of the first
insulating layer GI1 (e.g., a thinnest portion of “GI1” in Fig. 9);
re claim 5, Yoshida (in view of Kim) does not disclose specific thickness ranges for layers; however, this claim is deemed obvious because the prior art discloses the general conditions of the claimed invention, and given the prior art, one of ordinary skill in the art would have been able to determine a workable or optimum range in thickness for the second insulating layer, wherein a range in thickness of 150 nm or more is considered to be an optimum or workable range that one of ordinary skill in the art would have been able to determine without extensive experimentation given specific design requirement for a desired display device. Note it has been held that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05). In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955);
re claim 6, Kim discloses a second connection wiring line (e.g., see wiring line connected to “Cst1” in the circuit schematic in Fig. 5) configured to electrically connect the auxiliary
electrode Cst1 to an upper electrode (e.g., in Fig. 5, “Cst1” connects to an upper electrode, anode, of “OLED”, wherein “configured to electrically connect” does not require “in direct physical contact with...”);
re claim 7, Kim discloses wherein the second connection wiring line is included in the fourth metal layer (e.g., in the Fig. 5 circuit schematic, “Cst1” is electrically connected to “D6”, which is connected to the pixel electrode 120, or anode, of “OLED”; and in Fig. 9, the pixel electrode 120 is connected to wiring included in the fourth metal layer “CM2”);
re claim 8, Although not explicitly shown by Yoshida (in view of Kim), the upper electrode and the second connection wiring line would be connected to each other via a first contact hole, and the auxiliary electrode and the second connection wiring line would be connected to each other via a second contact hole different from the first contact hole, otherwise the capacitor electrodes would be electrically shorted (in any case, Kim disclose “CM1” and “CM2” are formed in first and second contact holes different from each other);
re claim 9, Kim discloses the second contact hole (for “CM2” in Fig. 9) does not overlap the second metal layer Cst2 (Fig. 9);
re claim 10, Kim discloses a gate electrode G2 (Fig. 9) of a drive transistor T2 is integrated (in a same layer) with the auxiliary electrode Cst1; and
re claim 16, Kim discloses wherein the gate electrode G2 (Fig. 9) of the drive transistor T2 is included in the first metal layer.
Therefore, claims 3-10 and 16 are rendered obvious by Yoshida (in view of Kim).
Regarding claim 11:
Yoshida anticipates claim 1 but is silent with respect to metallization layers of the display device; accordingly, Yoshida does not disclose the limitations in the current claim.
Lee teaches, in a display device (Fig. 9), first to third metal layers sequentially provided on a semiconductor layer A2 [0088] via an insulating layer GI1 [0098], wherein an upper electrode Cst2 is included in the second metal layer, and a lower electrode Cst1 is included in the first metal layer, and a first connection wiring line CM1 is included in the third metal layer.
Since Yoshida is silent with respect to metallization layers, it would have been obvious to one of ordinary skill in the art to incorporate metallization layers, as taught by Lee, because Lee metallization layers are well suited for a display device, and the incorporation would provide a complete, functional device.
Regarding claims 12-15:
re claim 12, Kim discloses wherein one end of the first connection wiring line CM1 (Fig. 9) is connected to the upper electrode Cst2 via a third contact hole;
re claim 13, Kim discloses wherein another end of the first connection wiring line CM1 is connected to the first connection wiring line CM1 adjacent in the row direction via the first metal layer (i.e., the current claim essentially requires the ends of the first connection wiring to be connected, which is readily obvious or inherent to Kim);
re claim 14, Kim discloses wherein a gate electrode G2 (Fig. 9) of the drive transistor T2 is integrated with the lower electrode Cst (i.e., integrated in a same layer); and
re claim 15, Kim discloses wherein a constant potential is applied to the upper electrode Cst (Fig. 9) via the first connection wiring line CM1.
Therefore, claims 12-15 are rendered obvious by Yoshida (in view of Kim).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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