Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 06/19/2026 in regards to the rejection(s) under Tayanaka et al.(US 20130234220 A1, hereafter Tayanaka) in view of Tanaka et al.(US 20080273105 A1, hereafter Tanaka) and under Yun et al.(US 20200119066 A1, hereafter Yun) in view of Tanaka have been fully considered but they do not place the application in the conditions for allowance. Firstly, the examiner disagrees with the contention that the prior art ratio of 10:1 is not close to a claimed ratio of 150:1. This is because the concept of the ratio needing to increase by over an order of magnitude is largely a function of how the ratio is presented and not a statement of absolute distance. For example, if these ratios we re-expressed as percentages, then a value of 91 percent(10/11) would be close to a value of 99 percent(150/151). Secondly, as stated in the Non-final office action dated 03/20/2026, the direction of the prior art trends towards the maximizing of the ratio of active photodiode to floating diffusion area. As further evidence for this assertion and not used as a new grounds for rejection, the prior art of Kusuhara et al.(See attached NPL, “Kusuhara 2016”, hereafter Kusuhara) and Nasuno et al.(See attached NPL, “Nasuno 2016”, hereafter Nasuno) is cited, wherein in an effort to reduce the capacitance of a floating diffusion region, Kusuhara creates a CMOS image sensor with a floating diffusion area of 0.1496 μm2 and teaches a CMOS image sensor with a floating diffusion area of just 0.03 μm-2(See page 96, Table 3, Paragraph 1). When related to a typical CMOS image sensor dimensions of pitch 5.6 μm and a 30.4 percent fill factor(See page 118 of Nasuno, final paragraph), this generates an active photodiode area of 9.53 μm2, meaning that a ratio of a photodiode region to a floating diffusion region in the prior art has reached an order of roughly 60:1 to 300:1. Furthermore, with consideration of structures such as the shared floating diffusion region by four photodiode areas taught by prior art such as Yun, the development of ever-smaller floating diffusion regions, such as by Kusuhara, appears to have reached such a ratio as 150:1.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation "the source-follower transistor" in Line 1. There is insufficient antecedent basis for this limitation in the claim. Claim 1 does not appear to recite a source-follower transistor. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun, Tanaka, and Kenichi(US 20100237390 A1, hereafter Kenichi), further in view of Kusuhara.
Regarding Claim 2,
Yun and Tanaka do not specifically provide an active area of each pinned photodiode of the plurality of pinned photodiodes is at least 25 μm2.
In the same field of endeavor, Kenichi discloses an active area of a pinned photodiode as between 9 µm2 and 100 µm2(see paragraph 0039).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further produce Yun’s device along the lines of Kenichi. In producing Yun’s device, one of ordinary skill in the art would look to the prior art for guidance on the specific dimensions of the respective components, such as the area of the pinned photodiode. For this they may have used the teaching of Kenichi to produce a photodiode with a size of more than 25 µm2. When a claimed range overlaps with a range given by the prior art, a prima facie case of obviousness exists. As Yun does not provide an explicit instruction on the dimensions of their photodiode regions, one of ordinary skill in the art could have implemented Kenichi’s guidance to produce Yun’s device. Performing this production would have generated a predictable result in the creation of Yun’s device with a specified dimension of the pinned photodiodes.
Furthermore, neither Yun nor Tanaka teach or disclose the area of the floating diffusion region is less than 0.1 μm2.
In the same field of endeavor, Kusuhara discloses a floating diffusion area with an area of 0.1496 μm2, and teaches that with a miniaturized processing technology, a floating diffusion area of 0.03 μm2 is possible.
It would have been further obvious to one of ordinary skill in the art to arrive at the claimed limitation based on the teaching of Kusuhara. As floating diffusion regions are typically produced to be at a minimum size, one of ordinary skill in the art would naturally be driven to adopt Kusuhara’s teaching to produce a floating diffusion region which is as small as possible when producing a photodiode structure. Therefore, a predictable result arises when producing Yun’s device under the specifications laid out by Kusuhara, which is Yun’s photodiode structure with a laid-out set of dimensions of the photodiode area and the floating diffusion area.
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun and Tanaka, further in view of Kim(US 20170250212 A1, hereafter Kim).
Regarding Claim 15,
Neither Yun nor Tanaka disclose:
a substrate layer;
a P-type epitaxial layer disposed on the substrate layer;
a deep N-well disposed on the P-type epitaxial layer;
a P-type region disposed in the deep N-well region; and
a pinning layer disposed on the P-type region, wherein the pinning layer completely overlaps the P-type region.
In the same field of endeavor, Kim discloses:
a substrate layer(Fig. 3 [102]);
a P-type epitaxial layer(Fig. 3 [104]) disposed on the substrate layer(Fig. 3 [102]);
a deep N-well(Fig. 3 [122/106]) disposed on the P-type epitaxial layer(Fig. 3 [104]);
a P-type region(Fig. 3 [112]) disposed in the deep N-well region(Fig. 3 [122/106]); and
a pinning layer(Fig. 3 [114]) disposed on the P-type region(Fig. 3 [112]), wherein the pinning layer(Fig. 3 [114]) completely overlaps the P-type region(Fig. 3 [112]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to produce the device disclosed by Yun and Tanaka along the lines of Kim. The structure provided by Kim appears to constitute a standard pinned photodiode structure, and as such a cross-sectional view is not provided by either Yun nor Tanaka, requiring a further use of the prior art to produce any device. Performing this production would have generated a predictable result in the creation of an alternate embodiment of Yun’s device, further with a known cross-sectional structure.
Regarding Claim 16,
Yun discloses a transfer gate(Fig. 3 [TG]) disposed between a respective pinned photodiode(Fig. 3 [PD]) and the floating diffusion region(Fig. 3 [FD]).
Yun does not teach or disclose the respective transfer gate is disposed on the deep N-well,
Wherein the P-type region extends from the respective transfer fate to an edge of the pixel,
Wherein a portion of the respective transfer gate overlaps a portion of the pinning layer.
In the same field of endeavor, Kim discloses the respective transfer gate(Fig. 3 [150/154]) is disposed on the deep N-well(Fig. 3 [106/122]),
Wherein the P-type region(Fig. 3 [112]) extends from the respective transfer gate(Fig. 3 [150/154]) to an edge of the pixel(Fig. 1 [PD]),
Wherein a portion of the respective transfer gate(Fig. 3 [150/154]) overlaps a portion of the pinning layer(Fig. 3 [114]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to produce the device disclosed by Yun and Tanaka along the lines of Kim. The structure provided by Kim appears to constitute a standard pinned photodiode structure, and as such a cross-sectional view is not provided by either Yun nor Tanaka, requiring a further use of the prior art to produce any device. Performing this production would have generated a predictable result in the creation of an alternate embodiment of Yun’s device, further with a known cross-sectional structure.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun, Tanaka, and Kim, further in view of Shinohara(US 20120154650 A1, hereafter Shinohara).
Regarding Claim 17,
Neither Yun, Tanaka, nor Kim teach or disclose each pinned photodiode further comprises an N-type region disposed in the deep N-well under the P-type region and the pinning layer.
In the same field of endeavor, Shinohara teaches an N-type region(Fig. 5 [14]) disposed in the deep N-well(Fig. 5 [8]) under the P-type region(Fig. 5 See figure below) and the pinning layer(Fig. 5 [13]).
It would have been further obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Yun along the lines of Shinohara. One might have been motivated to better accumulate charges below the P-type regions. Performing this modification would have generated a predictable result in the creation of an alternate embodiment of Yun’s device, further with a portion of Shinohara’s cross-sectional structure.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun, Tanaka, and Kim, further in view of Adkisson et al.(US 20090001427 A1, hereafter Adkisson).
Regarding Claim 18,
Neither Yun, Tanaka, nor Kim teach or disclose the additional diffusion region or its respective limitations.
In the same field of endeavor, Adkisson discloses an additional diffusion region(Fig. 2B [30]) disposed between the floating diffusion region(Fig. 2B [18b]) and the respective pinned photodiode(Fig. 2B [14b]), wherein the additional diffusion region(Fig. 2B [30]) is disposed under the respective transfer gate(Fig. 2B [16b]) and is configured to isolate the floating diffusion region(Fig. 2B [18b]) from a portion of the deep N-well(Fig. 2C [15-2]) under the respective transfer gate(fig. 2B [16B]).
It would have been further obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Yun along the lines of Adkisson. One might have been motivated to better facilitate the transfer of charges into the floating diffusion region. Performing this modification would have generated a predictable result in the creation of an alternate embodiment of Yun’s device, further with a portion of Adkisson’s device in cross-section.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun and Tanaka, further in view of Mao et al.(US 20210358993 A1, hereafter Mao).
Regarding Claim 20,
Neither Yun nor Tanaka teach or disclose a dual conversion control transistor disposed between the reset transistor and the floating diffusion region.
In the same field of endeavor, Mao discloses a dual conversion control transistor(Fig. 4 [440]) between a reset transistor(Fig. 4 [RST]) and a floating diffusion region(Fig. 4 [FD1/FD2]).
It would have been further obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Yun along the lines of Mao. One might have been motivated to include this transistor to control the plurality of signals coming in from the plurality of photodiode regions. Performing this modification would have generated a predictable result in the creation of an alternate embodiment of Yun’s device, further with an additional transistor to manage the plurality of signal inputs from each photodiode.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al.(US 20190131328 A1) discloses a shared floating diffusion region wherein the area of the PN junction is maximized in order to increase photoelectric efficiency(See paragraph 0027).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARSHALL MU-NUO HATFIELD whose telephone number is (703)756-1506. The examiner can normally be reached Mon-Thus 11:00 AM-9:00PM EST.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897
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