(UDetailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-8 in the reply filed on 01/07/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tayanaka et al.(US 20130234220 A1, hereafter Tayanaka) in view of Tanaka et al.(US 20080273105 A1, hereafter Tanaka).
Regarding Claim 1, Tayanaka discloses:
A plurality of pinned photodiodes(Fig. 2 [1]); and
A floating diffusion region(Fig. 2 [FD]).
Tayanaka does not teach or disclose a ratio of an active area of the plurality of pinned photodiodes to an area of the floating diffusion region is greater than 150. However, Tayanaka does disclose that the light receiving area should be large in order to maximize the amount of charges moved by the light and increase the brightness of the device(See paragraph 0185).
In the same field of endeavor, Tanaka discloses an area of pinned photodiodes(Fig. 2 [11]) as being about ten times that of the area of a floating diffusion region(Fig. 2 [12a], See dimensions Fig. 2 [Da], 1100 nm, [Wa], 750 nm, [12a] 400nm x 400 nm, See paragraph 0062).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitations based off of the teachings of Tayanaka in view of Tanaka. While the prior art does not explicitly disclose the ratio of 150 or more to one of the area of the pinned photodiodes to an area of the floating diffusion region, the prior art of record discloses guidance for maximizing the pinned photodiode area, which would lead one of ordinary skill in the art towards the claimed range. Producing a device of these dimensions would have generated a predictable result in the creation of Tayanaka’s photosensor device with a maximized light-absorbing area.
Claim(s) 1, 4, 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al.(US 20200119066 A1, hereafter Yun) in view of Tanaka.
Regarding Claim 1, Yun discloses:
A pixel(Fig. 2) for an ambient light and/or color sensor comprising:
A plurality of pinned photodiodes(Fig. 3 [PD]); and
A floating diffusion region(Fig. 3 [FD]).
Yun does not teach or disclose a ratio of an active area of the plurality of pinned photodiodes to an area of the floating diffusion region is greater than 150.
In the same field of endeavor, Tanaka discloses an area of pinned photodiodes(Fig. 2 [11]) as being about ten times that of the area of a floating diffusion region(Fig. 2 [12a], See dimensions Fig. 2 [Da], 1100 nm, [Wa], 750 nm, [12a] 400nm x 400 nm, See paragraph 0062).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed device limitation from the prior art of Yun and Tanaka. In cases where a claimed range is close to a range provided in the prior art, a case for obviousness may be made if the claimed range can be reasonably expected to behave similarly as the range in the prior art(See MPEP 2144.05). Furthermore, a motivation for going from a ratio of about 10:1, as taught by Tanaka when comparing active photodiode area to 150:1 exists in the prior art, as it is known to be optimal to make the active photodiode region larger in order to gain more charges from absorbing more incident light, improving sensitivity of a pixel. Producing Yun’s device with these dimensions would have generated a predictable result in the creation of Yun’s device with a set of dimensions suggested by the prior art.
Regarding Claim 4, Yun further discloses:
The pixel(Fig. 3) is an active pixel(Fig. 4) comprising:
A reset transistor(Fig. 4 [RX]) configured to reset the floating diffusion region(Fig. 4 [FD]) to a reference voltage;
A plurality of transfer gates(Fig. 4 [TG1-4]), each transfer gate configurable to transfer a charge from one of the plurality of pinned photodiodes(Fig. 4 [PD1-4]) to the floating diffusion region(Fig. 4 [FD]);
A read-out transistor configured as a source-follower transistor(Fig. 4 [SF]) for sampling a voltage at the floating diffusion region(Fig. 4 [FD]).
Regarding Claim 6,
Yun discloses some of the features of claim 4, but Yun does not teach or disclose a read-out transistor formed with a width of less than 1 micron.
In the same field of endeavor, Tanaka discloses a read-out transistor with a size of 400 nm(See paragraph 0062).
It would have been further obvious to produce Yun’s device along the lines of Tanaka. In producing Yun’s device, one of ordinary skill in the art would look to the prior art for guidance on the specific dimensions of the respective components, such as the read-out transistor. For this they may have used the teaching of Tanaka to produce a transistor with a size of less than 1 micron. As the general direction of transistor size trends downwards, one might have been motivated to produce a transistor with such dimensions in order to create a circuit structure accompanying the pixel photodiode structures that is small enough as to not interfere with the packing efficiency of the pixels. Producing this device would have generated a predictable result in the creation of Yun’s device with a specific set of dimensions.
Regarding Claim 7,
Yun discloses some of the features of claim 4, but Yun does not teach or disclose signals for controlling each transfer gate and/or reset transistor and/or any metal lines for shielding such signals are routed at a minimum distance of at least 1 micron from the floating diffusion region.
However, as can be seen by Fig. 7 of Yun, the reset transistor and other transistors, and signals for controlling the transfer gates(See Fig. 7 [TR71/72/73/74]) are in an area outside of the main photodiode active region(Fig. 7 [PR1-4]). Furthermore, from the prior art of Tanaka, it can be seen that the photodiode regions(Fig. 2 [11]) would need to be at least on the micron scale.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to produce the device disclosed by Yun along the lines of Tanaka. Even by adopting the dimensions Fig. 2 Wa and Da of Tanaka to the respective photodiode regions of Yun, this claim would necessarily be satisfied as any lines directed from the peripheral transistors to the transfer gates would need to be greater than a micron. For this reason, this feature would have generated a predictable result in the creation of Yun’s device with a set of dimensions set forth by claim 1 of the present application.
Regarding Claim 8, Yun further discloses:
Four pinned photodiodes(Fig. 3 [PD1/PD2/PD3/PD4]) arranged around the floating diffusion region(Fig. 3 [FD]).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun and Tanaka, further in view of Kenichi(US 20100237390 A1, hereafter Kenichi)
Regarding Claim 2,
Yun discloses a device in accordance with some of the limitations of Claim 1.
Yun does not teach or disclose an active area of each pinned photodiode of the plurality of pinned photodiodes is at least 25µm2.
In the same field of endeavor, Kenichi discloses an active area of a pinned photodiode as between 9 µm2 and 100 µm2(see paragraph 0039).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further produce Yun’s device along the lines of Kenichi. In producing Yun’s device, one of ordinary skill in the art would look to the prior art for guidance on the specific dimensions of the respective components, such as the area of the pinned photodiode. For this they may have used the teaching of Kenichi to produce a photodiode with a size of more than 25 µm2. When a claimed range overlaps with a range given by the prior art, a prima facie case of obviousness exists. As Yun does not provide an explicit instruction on the dimensions of their photodiode regions, one of ordinary skill in the art could have implemented Kenichi’s guidance to produce Yun’s device. Performing this production would have generated a predictable result in the creation of Yun’s device with a specified dimension of the pinned photodiodes.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun and Tanaka, further in view of Park et al.(US 20180240826 A1, hereafter Park).
Regarding Claim 3,
Yun discloses a device in accordance with some limitations of claim 1.
Yun does not teach or disclose the floating diffusion region is configured to have a capacitance of 2.5 femtofarads or less.
In the same field of endeavor, Park discloses a floating diffusion region(Fig. 3A [FD]) with a capacitance of 2 femtofarads(See paragraph 0069).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further produce Yun’s device along the lines of Park. In producing Yun’s device, one of ordinary skill in the art would look to the prior art for guidance on the specific properties of the respective components, such as the capacitance of the floating diffusion region. For this they may have used the teaching of Park to produce a floating diffusion region with capacitance under 2.5 femtofarads. When a claimed range overlaps with a range given by the prior art, a prima facie case of obviousness exists. As Yun does not provide an explicit instruction on the capacitance of their floating diffusion regions, one of ordinary skill in the art could have implemented Park’s guidance to produce Yun’s device. Performing this production would have generated a predictable result in the creation of Yun’s device with a specified capacitance of the floating diffusion region.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun and Tanaka, further in view of Sato et al.(US 20170250216 A1, hereafter Sato).
Regarding Claim 5,
Yun discloses a device in accordance with some limitations of claim 1.
Yun does not teach or disclose the threshold voltage of the reset transistor is configured to be greater than 0.1 volts.
In the same field of endeavor, Sato discloses a reset transistor with a threshold voltage of 0.5 V(See paragraph 0124).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further produce Yun’s device along the lines of Sato. In producing Yun’s device, one of ordinary skill in the art would look to the prior art for guidance on the specific properties of the respective components, such as the threshold voltage of the reset transistor. For this they may have used the teaching of Sato to arrive at a reset transistor with a threshold voltage of above 0.1 volts. When a claimed range overlaps with a range given by the prior art, a prima facie case of obviousness exists. As Yun does not provide an explicit instruction on the threshold voltage of their reset transistor, one of ordinary skill in the art could have implemented Sato’s guidance to produce Yun’s device. Performing this production would have generated a predictable result in the creation of Yun’s device with a specified threshold voltage of the reset transistor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al.(US 20190131328 A1) discloses a shared floating diffusion region wherein the area of the PN junction is maximized in order to increase photoelectric efficiency(See paragraph 0027).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897