DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 17, 18 ,19,20, & 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation "the second support body" in line 6 of claim 17 There is insufficient antecedent basis for this limitation in the claim.
The limitations of claim 18 is unclear. Claim 18 states “the laminated body comprises a plurality of laminated bodies , the recessed portion comprises a plurality of recessed portions” depending from claim 4. Claim 4 states “the plurality of recessed portions comprises a plurality of first recessed portions aligned in a row and a plurality of second recessed portions aligned in a row, and the disposing comprises disposing each of the plurality of laminate bodies between a respective one of the plurality of first recessed portions and a respective one of the plurality of second recessed portions.” It is unclear if the laminated bodies of claim 18 are the same laminated bodies of claim 4 or is there a separate set of laminated bodies. It is unclear if the recessed portions of claim 18 are the same recessed portions of claim 4 or is there a separate set of recessed portions. To further prosecution the examiner interprets a plurality of laminated bodies of claim 18 is the same as the plurality of laminated bodies of claim 4. The examiner interprets a plurality recess portions of claim 18 as being the same as the plurality of recessed portions as stated in claim 4. Appropriate correction is required.
With regards to claims 6 and claim 19: It is unclear if “a second support body” of claim 19 is the same second support body of claim 6 or if there is an additional second support body. Examiner interprets that second support body of claim 19 is the same second support body of claim 6. Appropriate correction is required.
Claim 19 recites the limitation "the forming of the plurality of substrates" in line 7 of claim 19. There is insufficient antecedent basis for this limitation in the claim.
With regards to claims 6 and claim 20: It is unclear if “a second support body” of claim 20 is the same second support body of claim 6 or if there is an additional second support body. Examiner interprets that second support body of claim 20 is the same second support body of claim 6. Appropriate correction is required.
Claim 20 recites the limitation "the forming of the plurality of substrates" in line 7 of claim 20. There is insufficient antecedent basis for this limitation in the claim.
Claim 21 recites the limitation "the forming of the plurality of substrates" in line 6 of claim 21. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 23 & 42 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ozawa (US 2005/0035176 A1).
Regarding claim 1, Ozawa et al discloses A manufacturing method for a semiconductor device(fig. 2/fig. 7) comprising: preparing a laminate body (22,23,24,25)comprising a plurality of semiconductor layers(22,23,24,25)[0034], and a first support body (31)comprising an upper surface, a side surface, and a
recessed portion (45) comprising an opening adjacent to the upper surface and the side
surface[0063]: bonding and disposing the laminate body(22,23,24,25) to the upper surface of the first support body(31)[0038]; forming a first end surface at the laminate body(22,23,24,25); and forming a first dielectric layer (27)on the first end surface[0034] fig. 2-fig. 7.
Regarding claim 2, Ozawa et al discloses wherein the disposing is subsequent to the forming of the end surface fig. 2- fig. 7[0044][0047].
Regarding claim 23, Ozawa et al discloses A semiconductor device(1)(fig. 1/fig. 7) comprising: a substrate(22) comprising an upper surface, a side surface, and a recessed portion(45) comprising an opening adjacent to the upper surface and the side surface[0063] (fig. 2/fig. 7); a laminate body(20-23,24,25) disposed on the upper surface of the substrate(22)[0033-0034], the laminate body(20-23,24,25)
comprising a first end surface and a second end surface that are opposed to each other fig. 4b; and a dielectric layer(27) disposed on the first end surface[0027], wherein
the upper surface comprises a mounting region(30)[0032], the mounting region(30) having a stripe shape fig. 1, and the laminate body(20-23,24,25) is positioned on the mounting region[0032].
Regarding claim 42, Ozawa et al discloses A semiconductor apparatus (100)comprising: the semiconductor device(1) according to claim 23; and
a package(10) mounted with the semiconductor device(1) fig. 1 [0031].
Claim(s) 1-4, 12, 16, 18, 23-27, 31,35, & 36 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hata (US Pub no. 2008/0219309 A1)
Regarding claim 1, Hata et al discloses A manufacturing method for a semiconductor device comprising: preparing a laminate body(80) comprising a plurality of semiconductor layers(33-38)[0088-0090][0093], and a first support body(31) comprising an upper surface(31b), a side surface, and a recessed portion(portions of 31 on either side of 31b) fig. 24 comprising an opening adjacent to the upper surface and the side
surface(fig. 24)[0111]: bonding and disposing the laminate body (80)to the upper surface (31b)of the first support body(31)[0112]; forming a first end surface(side surface of 80) at the laminate body(80)[0092]; and
forming a first dielectric layer (41-41a/41b)on the first end surface(side surface of 80) [0092].
Regarding claim 2, Hata et al discloses wherein the disposing is subsequent to the forming of the end surface(side surface80)[0091-0092][0097][0111] .
Regarding claim 3 , Hata et al discloses wherein the laminate body (80)comprises a plurality of laminate bodies(fig. 17), the recessed portion comprises a plurality of recessed portions[0093][0112], and the disposing comprises disposing the plurality of laminate bodies(80) corresponding to the plurality of recessed portions of the first support body(80) [0112].
Regarding claim 4, Hata et al discloses wherein the plurality of recessed portions(portions of 31 on either side of 31b) comprises a plurality of first recessed portions (portions of 31 on either side of 31b) aligned in a row and a plurality of second recessed portions(portions of 31 on either side of 31b) aligned in a row, and the disposing comprises disposing each of the plurality of laminate bodies(80) between a respective one of the plurality of first recessed portions (portions of 31 on either side of 31b) and a respective one of the plurality of second recessed portions(portions of 31 on either side of 31b) [0112].
Regarding claim 12, Hata et al discloses wherein each of the plurality of semiconductor layers(33-38) comprises a second end surface, and the forming of the first dielectric layer(41a) comprises forming a second dielectric layer (41b)on the second end surface(fig. 24)[0092].
Regarding claim 16, Hata et al discloses wherein the disposing comprises bonding the laminate body (80)epitaxially laterally grown on a wafer(50) to the first support substrate(31), and then peeling the laminate body (80)from the wafer(50) [0096-0097].
Regarding claim 18, Hata et al discloses wherein the laminate body (80)comprises a plurality of laminate bodies(80), the recessed portion comprises a plurality of recessed portions, and
the disposing comprises disposing the plurality of laminate bodies corresponding
to the plurality of recessed portions( portions of 31 on either side of 31b) of the first support body(80) [0112], and wherein forming a plurality of substrates(31), each of the plurality of substrates(31) being disposed with a respective one of the plurality of laminate bodies(80), by dividing the first support body(31)[0079][0101].
Regarding claim 23, Hata et al discloses a semiconductor device (fig. 24)comprising: a substrate(31) comprising an upper surface(31b), a side surface, and a recessed portion (side surface of 31b and 31)comprising an opening adjacent to the upper surface and the side surface(fig. 24)[0112]; a laminate body (80)disposed on the upper surface of the substrate(31), the laminate body(80) comprising a first end surface and a second end surface that are opposed to each other fig. 24); and a dielectric layer (41)disposed on the first end surface(side surface of 80)[0083] fig. 24, wherein the upper surface (31b)comprises a mounting region(fig. 24), the mounting region having a stripe shape[0112][0115], and the laminate body(80) is positioned on the mounting region (fig. 24)[0115].
Regarding claim 24, Hata et al discloses wherein at least one of the first end surface or the second end surface(end surfaces are the side surfaces of 80 having element 41 thereon ) is a cleavage surface[0100].
Regarding claim 25, Hata et al discloses wherein the dielectric layer(41) is further disposed on the side surface of the substrate(31) fig. 24[0083][0112].
Regarding claim 26, Hata et al discloses wherein the dielectric layer(41) is further disposed on a bottom surface of the recessed portion(fig. 24)[0112].
Regarding claim 27, Hata et al discloses the dielectric layer(41) is disposed on a bonding member(44) bonding the laminate body (80)and the substrate(31) fig. 24[0114].
Regarding claim 31, Hata et al discloses wherein the substrate (31)comprises
a first recessed portion positioned on a side of the first end surface, and
a second recessed portion positioned on a side of the second end surface(fig. 24) (first and second recess portions are created by protrusion 31b).
Regarding claim 35, Hata et al discloses wherein the laminate body (80)comprises a body comprising a plurality of semiconductor layers(32-38), a first electrode(45) disposed on an upper surface of the body(80), a second electrode (40)disposed on a lower surface of the body(80), and a routing wiring (46)configured to route the first electrode(45) to a position below the body(80) fig. 24)[0118].
Regarding claim 36, Hata et al discloses wherein a wiring (47)is disposed on the upper surface of the substrate(31), the second electrode(40) is connected to the wiring(47), and the first electrode(45) is connected to the wiring (47)through the routing wiring(46) fig. 24 [0118].
Claim(s) 1, 2, 15, 23, 27,28,31,32,34,37,42 , & 46 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US Pub no. 2010/0123154 A1).
Regarding claim 1, Lee et al discloses A manufacturing method for a semiconductor device (fig. 1) comprising: preparing a laminate body(120) comprising a plurality of semiconductor layers, and a first support body(110) comprising an upper surface(upper surface 110) , a side surface, and a recessed portion (117)comprising an opening adjacent to the upper surface and the side
surface[0044](fig. 1) : bonding and disposing the laminate body(120) to the upper surface of the first support body(110)[0037][0039-0041]forming a first end surface(123) at the laminate body(120) fig.1; and forming a first dielectric layer (150)on the first end surface(123)[0053].
Regarding claim 2, Lee et al discloses wherein the disposing is subsequent to the forming of the end surface(123)[0036][0039-0041].
Regarding claim 15, Lee et al discloses wherein the disposing comprises disposing the laminate body(120) in a manner that the first end surface is positioned outside the recessed portion (117)of the first support body(110) [0045] fig. 1.
Regarding claim 23, Lee et al discloses A semiconductor device(fig. 1) comprising: a substrate (110)comprising an upper surface, a side surface, and a recessed portion (117)[0034][0044](grooves 117 form upper surface and side surfaces of 110)comprising an opening adjacent to the upper surface and the side surface[0045]; a laminate body(120) disposed on the upper surface of the substrate, the laminate body (120)comprising a first end surface and a second end surface that are opposed to each other; and a dielectric layer (150)disposed on the first end surface, wherein the upper surface comprises a mounting region (adhesion part 133), the mounting region having a stripe shape, and the laminate body (120)is positioned on the mounting region(adhesion part 133)[0037] fig. 1.
Regarding claim 27, Lee et al discloses wherein the dielectric layer(150) is disposed on a bonding member (133)bonding the laminate body(120) and the substrate(110) fig. 1.
Regarding claim 28, Lee et al discloses wherein an area of a bottom surface of the recessed portion (117)is smaller than an area of a side surface of the recessed portion(117)(fig. 1).
Regarding claim 31, Lee et al discloses wherein the substrate comprises a first recessed portion (117)positioned on a side of the first end surface, and a second recessed portion(117) positioned on a side of the second end surface fig. 1[0044-0045].
Regarding claim 32, Lee et al discloses wherein
the first end surface of the laminate body(120) is positioned on an opening of the first recessed portion(117) fig. 1.
Regarding claim 34, Lee et al discloses wherein a bottom surface of the second recessed portion(117) Is positioned outside an irradiation region of the second end surface(fig. 1).
Regarding claim 37, Lee et al discloses wherein the substrate (110)comprises a protruding portion side portion of 110 extending laterally from 117) protruding outside from the side surface of the recessed portion(117), and the wiring(131) is disposed on an upper surface of the protruding portion (side portion of 110 extending laterally from 117) fig. 1
Regarding claim 42, Lee et al discloses the semiconductor device according to claims 23, and a package(112) mounted with the semiconductor device(fig. 1).
Regarding claim 46, Lee et al discloses wherein the first recessed portion (117)is spread in a tapered manner toward the side surface, and the second recessed portion (117)is spread in a tapered manner toward another side surface opposing the side surface fig. 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5,10 & 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hata (US Pub no. 2008/0219309 A1).
Regarding claim 5, Hata et al discloses all the claim limitations of claim 1 in embodiment 1 (fig. 24) but fails to teach wherein the disposing comprises preparing a second support body, and disposing the laminate body in a sandwiched manner between the first support body and the second support body.
However, according to the fourth embodiment, Hata et al discloses preparing a second support body(252) , and disposing the laminate body (80)in a sandwiched manner between the first support body (80)and the second support body(252).It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first embodiment of Hata et al with the teachings of the fourth embodiment of Hata et al to assist in the peeling process.
Regarding claim 10, Hata et al discloses wherein the disposing comprises positioning the first support body(231) and the second support body (252)in a manner that the first support body(231) and the second support body(252) are in contact with each other fig. 47 (first and second support body are in contact by way of 280).
Regarding claim 11, Hata et al discloses the disposing comprises positioning the first support body(231) and the second support body(252) in a manner that the first support body (231)and the second support body(252) are separated from each other(fig. 47-separation occurs by way of isolation 281).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub no. 2010/0123154 A1).
Regarding claim 13, Lee et al discloses all the claim limitation of claim 1 but fails to teach wherein a wiring is routed on an upper surface of the first support body, and the disposing comprises disposing the laminate body on the wiring.
However, in the tenth embodiment, Lee et al discloses wherein a wiring(131b/132b) is routed on an upper surface of the first support body(110c), and the disposing comprises disposing the laminate body(120) on the wiring(131b/132b)[0106-0107]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first embodiment of Lee et al with the teachings of the tenth embodiment of Lee et al to enhance reflection.
Claim(s) 42 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hata (US Pub no. 2008/0219309 A1) in view of Hayashi (US Pub no. 2012/0224817 A1).
Regarding claim 42, Hata et al discloses all the claim limitations of claim 23 but fails to teach a package mounted with the semiconductor device.
However, Hayashi et al teaches packaging (310)of a laser diode (250) [0149]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Hata et al with the teachings of Hayashi et al to accommodate the semiconductor device and provide protection from environmental contaminates.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
Prosecution Insights