DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites limitation “the gate voltage” lines 4-5 and 7) that lacks antecedent basis in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over JP 03069159 A to Tamagawa in view of Suekawa et al. (US 2015/0008450, cited in IDS of 08/28/2023, hereinafter Suekawa).
With respect to claim 1, Tamagawa discloses a semiconductor device (e.g., a vertical power MOS transistor and a horizontal sensing MOS transistor on the same substrate) (Tamagawa, Figs. 1-3, pp. 1-4) comprising a vertical semiconductor transistor (18) and a horizontal semiconductor transistor (19) provided on a same semiconductor base (e.g., N+ substrate 1) (Tamagawa, Figs. 1-3, pp. 3-4), wherein
a gate electrode (13) of the vertical semiconductor transistor (18) and a gate electrode (13) of the horizontal semiconductor transistor (19) are electrically connected,
a source electrode (15) of the vertical semiconductor transistor (18) and a source electrode (15) of the horizontal semiconductor transistor (19) are electrically connected,
a drain electrode (17) of the vertical semiconductor transistor (18) and a drain electrode (16) of the horizontal semiconductor transistor (19) are provided on opposite sides with respect to the semiconductor base (1),
a threshold voltage of the horizontal semiconductor transistor (19) (Tamagawa, Figs. 1-3, p. 3) and a threshold voltage of the vertical semiconductor transistor (18), and
the drain electrode (16) of the horizontal semiconductor transistor (19) is an electrode connected to an electric power supply (e.g., power supply terminal 28) applying a voltage to the horizontal semiconductor transistor.
Further, Tamagawa does not specifically disclose that a threshold voltage of the horizontal semiconductor transistor is higher than a threshold voltage of the vertical semiconductor transistor.
However, Tamagawa teaches that a threshold voltage of the horizontal MOS transistor (19) (Tamagawa, Figs. 1-3, p. 3) is determined by the concentration of the P-type channel region (5) of the horizontal MOS transistor (19).
Further, Suegawa teaches forming a semiconductor device (Suegawa, Figs. 1-3 ¶0047-¶0067) comprising a vertical MOSFET transistor and a horizontal MOSFET transistor, wherein a threshold voltage (e.g., 25V) of the horizontal semiconductor transistor is higher than a threshold voltage (e.g., 20 V) of the vertical semiconductor transistor, so that during normal operation within the maximum voltage rating of 20 V, the horizontal MOSFET transistor has no effect on the operation of the vertical MOSFET (Suegawa, Figs. 1-3 ¶0066-¶0067), and to prevent breakdown of the vertical MOSFET.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Tamagawa by adjusting the concentration of the P-type channel region of the horizontal MOS transistor to have a specific threshold voltage of the horizontal MOS transistor as taught by Tamagawa, wherein relationship between threshold voltages of the horizontal semiconductor transistor and the vertical semiconductor transistor is obtained as taught by Suegawa to have the semiconductor device, wherein a threshold voltage of the horizontal semiconductor transistor is higher than a threshold voltage of the vertical semiconductor transistor, in order to provide stable operation of the vertical MOSFET transistor with no effect of the horizontal semiconductor transistor on the operation of the vertical MOSFET during normal operation, and to prevent breakdown of the vertical MOSFET (Suegawa, ¶0065-¶0067).
Regarding claim 2, Tamagawa in view of Suegawa discloses the semiconductor device according to claim 1. Further, Tamagawa discloses the semiconductor device, wherein the semiconductor base (1) includes a semiconductor (e.g., Si), and each of the vertical semiconductor transistor (18) and the horizontal semiconductor transistor (19) includes a MOSFET, but does not specifically disclose that the semiconductor base includes a wide bandgap semiconductor.
However, Suegawa teaches forming a semiconductor device (Suegawa, Figs. 1-3 ¶0047-¶0067) comprising SiC wafer as a wide bandgap semiconductor, wherein the vertical MOSFET transistor and the horizontal MOSFET transistor includes SiC wafer, to reduce a drop in a forward voltage (on-voltage), and thus to reduce the number of unit cells and the chip size (Suegawa, Figs. 1-3 ¶0032-¶0040, ¶0048).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Tamagawa/Suegawa by forming the vertical semiconductor transistor and the horizontal semiconductor transistor including SiC wafer as taught by Suegawa to have the semiconductor device, wherein the semiconductor base includes a wide bandgap semiconductor, in order to reduce a drop in a forward voltage (on-voltage), and thus to reduce the number of unit cells and the chip size (Suegawa, ¶0032-¶0040, ¶0048).
Regarding claim 3, Tamagawa in view of Suegawa discloses the semiconductor device according to claim 1. Further, Tamagawa discloses the semiconductor device, wherein a gate insulating film (12) (Tamagawa, Fig. 2-3, pp. 3-4) of the vertical semiconductor transistor (18) and a gate insulating film (12) of the horizontal semiconductor transistor (19) have a same material and a same thickness.
Regarding claim 6, Tamagawa in view of Suegawa discloses a method of manufacturing the semiconductor device according to claim 1. Further, Tamagawa does not specifically disclose that a gate insulating film of the vertical semiconductor transistor and a gate insulating film of the horizontal semiconductor transistor are formed in a same step.
However, Tamagawa teaches that a gate insulating film (12) (Tamagawa, Fig. 2-3, pp. 3-4) of the vertical semiconductor transistor (18) and a gate insulating film (12) of the horizontal semiconductor transistor (19) have a same material and a same thickness.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of manufacturing the semiconductor device of Tamagawa/Suegawa by forming the vertical semiconductor transistor and the horizontal semiconductor transistor by the same process as taught by Tamagawa to have the method, wherein a gate insulating film of the vertical semiconductor transistor and a gate insulating film of the horizontal semiconductor transistor are formed in a same step, in order to provide improved method of forming the vertical semiconductor transistor and the horizontal semiconductor transistor on the same substrate (Tamagawa, pp.1, 3-4).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over JP 03069159 A to Tamagawa in view of Suekawa (US 2015/0008450) as applied to claim 1, and further in view of Kitamura (US 2011/0068387).
Regarding claim 4, Tamagawa in view of Suegawa discloses the semiconductor device according to claim 1. Further, Tamagawa does not specifically disclose that each of a drain pad corresponding to the drain electrode of the vertical semiconductor transistor and a drain pad corresponding to the drain electrode of the horizontal semiconductor transistor is wire-bonded.
However, Kitamura teaches forming a semiconductor device (Kitamura, Fig. 1, ¶0003, ¶0008, ¶0030-¶0040, ¶0051) comprising a vertical transistor and a horizontal transistor, wherein each of a drain pad (16) corresponding to the drain electrode (34) of the vertical semiconductor transistor (31) and a drain pad (16) corresponding to the drain electrode (54) of the horizontal semiconductor transistor (51) is wire-bonded (e.g., external wire 18 are bonded to the pads 16 corresponding to the drain 34 of the vertical semiconductor transistor and the drain 54 of the horizontal semiconductor transistor), to provide semiconductor device that can restrict changes in electrical properties and stress due to bonding the external wires.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Tamagawa/Suegawa by coupling the vertical semiconductor transistor and the horizontal semiconductor transistor to the external devices through the external wires as taught by Kitamura to have the semiconductor device, wherein each of a drain pad corresponding to the drain electrode of the vertical semiconductor transistor and a drain pad corresponding to the drain electrode of the horizontal semiconductor transistor is wire-bonded, in order to provide improved semiconductor device that can restrict changes in electrical properties and stress due to bonding the external wires (Kitamura, ¶0003, ¶0008, ¶0030, ¶0033, ¶0051).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over JP 03069159 A to Tamagawa in view of Suekawa (US 2015/0008450) as applied to claim 1, and further in view of Anderson et al. (US 2017/0309616, hereinafter Anderson).
Regarding claim 5, Tamagawa in view of Suegawa discloses the semiconductor device according to claim 1. Further, Tamagawa does not specifically disclose that a gate insulating film of the horizontal semiconductor transistor is thicker than a gate insulating film of the vertical semiconductor transistor.
However, Anderson teaches forming a semiconductor device comprising a vertical field effect transistor (100b) (Anderson, Fig. 10, ¶0003-¶0004, ¶0056-¶0060, ¶0082-¶0086) and a lateral metal oxide semiconductor device (100a), wherein a gate insulating film of the horizontal semiconductor transistor (100a) is thicker (Anderson, Fig. 10, ¶0060, ¶0086) than a gate insulating film of the vertical semiconductor transistor (100b) for application in higher voltages.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Tamagawa/Suegawa by forming a gate insulating film of the horizontal semiconductor transistor with an increased thickness as taught by Anderson to have the semiconductor device, wherein a gate insulating film of the horizontal semiconductor transistor is thicker than a gate insulating film of the vertical semiconductor transistor, in order to provide lateral metal oxide semiconductor device for application in higher voltages (Anderson, ¶0003-¶0004, ¶0060, ¶0086).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over JP 03069159 A to Tamagawa in view of Suekawa (US 2015/0008450) as applied to claim 1, and further in view of Seki (US Patent No. 5,986,282).
Regarding claim 7, Tamagawa in view of Suegawa discloses the semiconductor device according to claim 1. Further, Tamagawa does not specifically disclose a method of manufacturing the semiconductor device, comprising: obtaining a first electrical characteristic of the horizontal semiconductor transistor before application of the gate voltage and obtaining a second electrical characteristic of the horizontal semiconductor transistor after application of the gate voltage by applying a gate voltage that is a predetermined voltage or higher to the horizontal semiconductor transistor without applying the gate voltage to the vertical semiconductor transistor; and, selecting semiconductor devices that satisfy a predetermined standard based on the first electrical characteristic and the second electrical characteristic.
However, Seki teaches a method of manufacturing a semiconductor device by measuring electrical characteristics of the semiconductor circuits including MOSFET structure (Seki, Figs. 1-5, Col. 1, lines 16-40; Col. 2, lines 28-37; Col. 3, lines 38-63; Col. 4, lines 31-67; Col. 5, lines 1-67; Col. 6, lines 1-39) in a semiconductor wafer state, wherein the electrical characteristics are evaluated during aging the semiconductor circuits including MOSFET structure on a semiconductor wafer state without applying the voltage to the pads in a single semiconductor circuit to determined initial failure, and then probing is performed by applying the voltage to the pads in a single semiconductor circuit to test the electrical characteristics of the semiconductor circuit independently and individually, and then to select the semiconductor chips in accordance with their evaluating characteristics by using a first electrical characteristic and a second electrical characteristic after aging and probing to form a packaged semiconductor device (Seki, Figs. 1-5, Col. 5, lines 39-57; Col. 6, lines 16-39).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of manufacturing the semiconductor device of Tamagawa/Suegawa by measuring electrical characteristics of the semiconductor circuits including MOSFET structure after aging and probing as taught by Seki, wherein the MOSFET structure includes horizontal semiconductor transistor of Tamagawa to have a method of manufacturing the semiconductor device, comprising: obtaining a first electrical characteristic of the horizontal semiconductor transistor before application of the gate voltage and obtaining a second electrical characteristic of the horizontal semiconductor transistor after application of the gate voltage by applying a gate voltage that is a predetermined voltage or higher to the horizontal semiconductor transistor without applying the gate voltage to the vertical semiconductor transistor; and, selecting semiconductor devices that satisfy a predetermined standard based on the first electrical characteristic and the second electrical characteristic, in order to provide an improved method of measuring electrical characteristics of the semiconductor circuits including MOSFET structure with improved operability in the test (Seki, Col. 1, lines 9-40; Col. 2, lines 28-37; Col. 6, lines 16-39).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over JP 03069159 A to Tamagawa in view of Suekawa (US 2015/0008450) as applied to claim 1, and further in view of Zoels et al. (US 2013/0328596, hereinafter Zoels).
Regarding claim 8, Tamagawa in view of Suegawa discloses the semiconductor device according to claim 1. Further, Tamagawa does not specifically disclose a method of replacing the semiconductor device, comprising: measuring threshold voltages of the vertical semiconductor transistor and the horizontal semiconductor transistor at different points of time; and replacing the semiconductor device when determined, based on the threshold voltages of the vertical semiconductor transistor and the threshold voltages of the horizontal semiconductor transistor measured at different points of time, that the threshold voltages of the vertical semiconductor transistor after a predetermined period exceed a predetermined threshold.
However, Zoels teaches power switch health monitoring (Zould, Figs. 1-2, ¶0002, ¶0011- ¶0014, ¶0030, ¶0038, ¶0041, ¶0045-¶0046, ¶0052, ¶0053, ¶0055-¶0056) by accurately determining the remaining lifetime of a power switch in operation, wherein the health monitoring is performed based on a comparison of the measured values to the standard value of characteristics within designated time threshold, and is used to indicate whether the switch may need to be replaced. The power switch includes MOSFETs or IGBTs, and the characteristics that describe the health of the power switch includes threshold voltage (Vgeth). The measurements of threshold voltage (Vgeth) is used to detect delamination of semiconductor layers or debonding of the gate terminal. During operation, continuous or periodic measurement of selected characteristics (e.g., Vgeth) then are compared to the base values for monitoring the health of the power switch, and the information including measured selected characteristics is communicated to the controller to identify one or more of the plurality of power switches to be replaced.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of manufacturing the semiconductor device of Tamagawa/Suegawa by monitoring power switch health including threshold voltage characteristics of the MOSFETs during operation periodically at different time points as taught by Zoels, wherein the MOSFETs include the vertical semiconductor transistor and the horizontal semiconductor transistor to have a method of replacing the semiconductor device, comprising: measuring threshold voltages of the vertical semiconductor transistor and the horizontal semiconductor transistor at different points of time; and replacing the semiconductor device when determined, based on the threshold voltages of the vertical semiconductor transistor and the threshold voltages of the horizontal semiconductor transistor measured at different points of time, that the threshold voltages of the vertical semiconductor transistor after a predetermined period exceed a predetermined threshold, in order to provide improved method to accurately determine the remaining lifetime of a power switch in operation (Zoels, ¶0002, ¶0011- ¶0014, ¶0030, ¶0041, ¶0045-¶0046, ¶0052-¶0053, ¶0055-¶0056).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891