Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group A in the reply filed on 12/23/2025 is acknowledged. Claims 11-15 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claims 1-10 and 16-19 are examined in this office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9, and 16-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi et al. (US Patent Pub 20210091320 A1).
Regarding Claim 1, Choi teaches a display panel, comprising:
a substrate comprising a display area and a peripheral area outside the display (Fig. 5B, substrate 100 having display area DA and peripheral area PA),
wherein the peripheral area comprises a circuit area and a blocking area sequentially distributed along a direction away from the display area (Fig. 5B, see annotated figure below);
a driving device layer arranged on a side of the substrate and covering the display area and the peripheral area (Fig. 5B, Layers 103, 105, 107, and thin-film transistor (TFT) Layers (131, 132, 133, 134, and 136) make up the driving device layer. These layers cover both the display area DA and the peripheral area PA);
a planarization layer arranged on a side of the driving device layer away from the substrate, wherein a boundary of an orthographic projection of the planarization layer on the substrate is located within the circuit area (Fig. 5B, planarization layer (111 and 113), a portion of an orthographic projection of 111 and 113 is located within the circuit area (See annotated figure for reference));
a light emitting layer arranged on a surface of the planarization layer away from the substrate, wherein an orthographic projection of the light emitting layer on the substrate at least covers the display area (Fig. 5B, light emitting layer OLED (230/220/210) on a surface of planarization layer (111 and 113) and covers the display area DA);
a blocking dam arranged on a side of the driving device layer away from the substrate and arranged around the display area, wherein an orthographic projection of the blocking dam on the substrate is located in the blocking area (Fig. 5B, blocking dam (PW1 and PW2) on side of driving device layer away from substrate and arranged around (not in) display area. An orthographic projection of the blocking dam on the substrate is located in the blocking area (see annotated figure below));
a first inorganic encapsulation layer covering the light emitting layer and the blocking dam, wherein an orthographic projection of the first inorganic encapsulation layer on the substrate covers the display area and the peripheral area (Fig. 5B, first inorganic encapsulation layer 310. Paragraph 130 teaches 310 is inorganic. 310 covers the light emitting layer OLED and the blocking dam (PW1 and PW2), and an orthographic projection of the first inorganic encapsulation layer on the substrate covers the display area and the peripheral area);
an organic encapsulation layer arranged on a surface of the first inorganic encapsulation layer away from the substrate, wherein an orthographic projection of the planarization layer on the substrate is located within an orthographic projection of the organic encapsulation layer on the substrate (Fig. 5B, organic encapsulation layer 320 on the surface of first inorganic encapsulation layer. An orthographic projection of the planarization layer (111 and 113) on the substrate is located within an orthographic projection of the organic encapsulation layer 320 on the substrate);
and a second inorganic encapsulation layer covering the organic encapsulation layer, wherein an orthographic projection of the second inorganic encapsulation layer on the substrate covers the display area and the peripheral area (Fig. 5B, second inorganic encapsulation layer 330 covering organic encapsulation layer 320. Paragraph 130 teaches 330 is inorganic. An orthographic projection of the second inorganic encapsulation layer on the substrate covers the display area and the peripheral area).
Regarding Claim 2, Choi teaches the display panel according to claim 1, wherein the planarization layer comprises:
a first planarization layer covering the driving device layer, wherein a boundary of an orthographic projection of the first planarization layer on the substrate is located within the circuit area (Fig. 5B, first planarization layer 111. A portion of 111 is within circuit area (see annotated figure below)):
and a second planarization layer arranged on a side of the first planarization layer away from the substrate, wherein a boundary of an orthographic projection of the second planarization layer on the substrate is located within the circuit area, and the light emitting layer is arranged on a surface of the second planarization layer away from the substrate (Choi, Fig. 5B, second planarization layer 113. . A boundary of an orthographic projection of the second planarization layer on the substrate is located within the circuit area (see annotated figure below). Light emitting layer OLED on a surface of the second planarization layer away from the substrate).
Regarding Claim 3, Choi teaches the display panel according to claim 2, wherein the light emitting layer comprises:
a first electrode layer arranged on the side of the second planarization layer away from the substrate, wherein the first electrode layer comprises a first electrode and an interconnection portion, an orthographic projection of the first electrode on the substrate is located in the display area, and an orthographic projection of the interconnection portion on the substrate is located in the circuit area (Choi, Fig. 5B, 210 and 75 are the first electrode layer, 210 being the first electrode and 75 being the interconnection portion. An orthographic projection of the first electrode 210 on the substrate is located in the display area DA, and an orthographic projection of the interconnection portion 75 on the substrate is located in the circuit area (see annotated figure below));
a pixel definition layer arranged on a surface of the second planarization layer away from the substrate, wherein an orthographic projection of the pixel definition layer on the substrate covers the display area and the circuit area, and the pixel definition layer is provided with a pixel opening exposing the first electrode and an interconnection opening exposing the interconnection portion (Fig. 5B, pixel definition layer 180. An orthographic projection of the pixel definition layer on the substrate covers the display area DA and the circuit area (see annotated figure below). Paragraph 0114 teaches 180 may include an opening that exposes at least part of the first electrode 210. Fig. 5B shows 180 has an interconnection opening exposing the interconnection portion (see annotated figure below));
a light emitting functional layer covering the pixel definition layer and the first electrode, wherein an orthographic projection of the light emitting functional layer on the substrate is located in the display area (Fig. 5B, light emitting functional layer 220. 220 covers the pixel definition layer (in the DPX area) and the first electrode. An orthographic projection of the light emitting functional layer on the substrate is located in the display area DA):
and a second electrode layer covering the light emitting functional layer, wherein a boundary of an orthographic projection of the second electrode layer on the substrate is located in the circuit area, and the second electrode layer is connected to the interconnection portion through the interconnection opening; wherein the first inorganic encapsulation layer covers the second electrode layer (Choi, Fig. 5B, second electrode layer 230. 230 covers the light emitting functional layer 220. A boundary of an orthographic projection of the second electrode layer 230 on the substrate is located in the circuit area (see annotated figure below). 230 is electrically connected to the interconnection portion through the interconnection opening (opening of 180). First encapsulation layer 310 covers second electrode layer 230).
Regarding Claim 4, Choi teaches the display panel according to claim 3, wherein the blocking dam comprises a first dam and a second dam, and the second dam surrounds the first dam (Choi, Fig. 5B, first dam PW1 and second dam PW2. Paragraph 0144 teaches second dam PW2 may surround first dam PW1).
Regarding Claim 5, Choi teaches the display panel according to claim 4, wherein
the first dam is arranged in the same layer as the pixel definition layer (Choi, Fig. 5B, first dam PW1 arranged in same layer as pixel definition layer 180),
the second dam comprises a first blocking layer and a second blocking layer stacked in a direction away from the substrate the first blocking layer is arranged in the same layer as the second planarization layer, and the second blocking layer is arranged in the same layer as the pixel definition layer (Choi, Fig. 5B, second dam PW2 comprises a first blocking layer and second blocking layer stacked in a direction away from the substrate. The first blocking layer is arranged in the same layer as the second planarization layer, and the second blocking layer is arranged in the same layer as the pixel definition layer (see annotated figure below).
Regarding Claim 6, Choi teaches the display panel according to claim 5, wherein the first electrode layer further comprises:
an extension portion connected to the interconnection portion, wherein an orthographic projection of the extension portion on the substrate is located in the blocking area (Fig. 5B, extension portion (see annotated figure) in electrical connection with interconnection portion 75 of first electrode layer 210. An orthographic projection of the extension portion on the substrate is located in the blocking area (see annotated figure below);
wherein the first dam is arranged on a surface of the extension portion away from the substrate (Fig. 5B, first dam PW1 on a surface of extension portion (see annotated figure) away from substrate).
Regarding Claim 7, Choi teaches the display panel according to claim 6, wherein the driving device layer comprises:
an active layer arranged on a side of the substrate, wherein an orthographic projection of the active layer on the substrate is located in the display area and the circuit area (Choi, Fig. 5B, active layer 134. An orthographic projection of active layer 134 located in the display area DA and the circuit area (134 in PC located in display area as well as DPC-A located in circuit area. See annotated figure below));
a first gate insulating layer covering the active layer and the substrate (Choi, Fig. 5B, first gate insulating layer 103 covering active layer 134) ;
a gate arranged on a surface of the first gate insulating layer away from the substrate, wherein an orthographic projection of the gate on the substrate is located in the display area and the circuit area (Choi, Fig. 5B, gate 136 located in the display area DA and circuit area (see annotated figure below) and on surface of first gate insulating layer 103);
a second gate insulating layer covering the gate and the first gate insulating layer (Choi, Fig. 5B, second gate insulating layer 105, which covers the gate 136 and the first gate insulating layer 103);
an interlayer dielectric layer covering the second gate insulating layer (Choi, Fig. 5B, interlayer dielectric layer 107, which covers the second gate insulating layer 105);
a source and drain layer arranged on a surface of the interlayer dielectric layer away from the substrate, wherein an orthographic projection of the source and drain layer on the substrate is located in the display area and the circuit area (Choi, Fig. 5B, source and drain layer on surface of interlayer dielectric layer 107 away from the substrate (boxed, see annotated figure below). An orthographic projection of the source and drain layer on the substrate is located in the display area and the circuit area (see annotated figure below);
and the first planarization layer arranged on a side of the source and drain layer away from the substrate (first planarization layer 111 on a side of the source and drain layer away from the substrate (See annotated figure));
wherein the display panel further comprises:
a connection layer arranged on a surface of the first planarization layer away from the substrate and connected to the source and drain layer, wherein an orthographic projection of the connection layer on the substrate is located in the display area (Choi, Fig. 5B, connection layer PL. PL located in the display area and on a surface of the first planarization layer 111 and electrically connected to the source and drain layer (boxed, see annotated figure)).
a signal line arranged on a side of the blocking dam close to the substrate (Fig. 5B, signal line (170 and 171) on side of blocking dam close to substrate)
wherein the signal line comprises a first line layer and a second line layer stacked sequentially in a direction away from the substrate (Fig. 5B, first line layer 170 and second line layer 171),
the first line layer is arranged in the same layer as the source and drain (Fig. 5B, 170 in same layer as source and drain layer (see annotated figure)
the second line layer is arranged in the same layer as the connection layer (Fig. 5B, 171 in the same layer as connection layer )
and at least a partial area of the second dam is arranged on a surface of the second line layer away from the substrate (Fig. 5B, second dam PW2 is partially arranged on a surface of second line layer 171):
wherein the extension portion is arranged on a surface of the signal line away from the substrate (Fig. 5B, extension portion (see annotated figure) arranged on a surface of the signal line away from the substrate).
Regarding Claim 8, Choi teaches the display panel according to claim 3, wherein the second planarization layer is provided with a first blocking groove penetrating through the second planarization layer and the first planarization layer (Choi, Fig. 5B, first blocking groove (circled, see annotated figure below) penetrating though second planarization layer 113 and first planarization layer 111),
and an orthographic projection of the first blocking groove on the substrate is located in the circuit area and surrounds the display area (Choi, Fig. 5B, first blocking groove (see annotated figure below) located in circuit area, and surrounds the display area DA) .
Regarding Claim 9, Choi teaches the display panel according to claim 7, wherein the interlayer dielectric layer is provided with a second blocking groove and an orthographic projection of the second blocking groove on the substrate surrounds the second dam (Fig. 5B, second blocking groove provided (107 ends where 114 begins, forming the second blocking groove) and surrounds the second dam DM2 (see annotated figure below)).
Regarding Claim 16, Choi teaches a display device, comprising a display panel, wherein the display panel comprises:
a substrate comprising a display area and a peripheral area outside the display area (Fig. 5B, substrate 100 having display area DA and peripheral area PA),
wherein the peripheral area comprises a circuit area and a blocking area sequentially distributed along a direction away from the display area (Choi, Fig. 5B. see annotated figure below);
a driving device layer arranged on a side of the substrate and covering the display area and the peripheral area (Fig. 5B, Layers 103, 105, 107, and thin-film transistor (TFT) Layers (131, 132, 133, 134, and 136) make up the driving device layer. These layers cover both the display area DA and the peripheral area PA);
a planarization layer arranged on a side of the driving device layer away from the substrate, wherein a boundary of an orthographic projection of the planarization layer on the substrate is located within the circuit area (Fig. 5B, planarization layer (111 and 113), a portion of an orthographic projection of 111 and 113 is located within the circuit area (See annotated figure for reference));
a light emitting layer arranged on a surface of the planarization layer away from the substrate, wherein an orthographic projection of the light emitting layer on the substrate at least covers the display area (Fig. 5B, light emitting layer OLED (230/220/210) on a surface of planarization layer (111 and 113) and covers the display area DA);
a blocking dam arranged on a side of the driving device layer away from the substrate and arranged around the display area, wherein an orthographic projection of the blocking dam on the substrate is located in the blocking area (Fig. 5B, blocking dam (PW1 and PW2) on side of driving device layer away from substrate and arranged around (not in) display area. An orthographic projection of the blocking dam on the substrate is located in the blocking area (See annotated figure below));
a first inorganic encapsulation layer covering the light emitting layer and the blocking dam, wherein an orthographic projection of the first inorganic encapsulation layer on the substrate covers the display area and the peripheral area (Fig. 5B, first inorganic encapsulation layer 310. Paragraph 130 teaches 310 is inorganic. 310 covers the light emitting layer OLED and the blocking dam (PW1 and PW2), and an orthographic projection of the first inorganic encapsulation layer on the substrate covers the display area and the peripheral area);
an organic encapsulation layer arranged on a surface of the first inorganic encapsulation layer away from the substrate, wherein an orthographic projection of the planarization layer on the substrate is located within an orthographic projection of the organic encapsulation layer on the substrate (Fig. 5B, organic encapsulation layer 320 on the surface of first inorganic encapsulation layer. An orthographic projection of the planarization layer (111 and 113) on the substrate is located within an orthographic projection of the organic encapsulation layer 320 on the substrate);
and a second inorganic encapsulation layer covering the organic encapsulation layer, wherein an orthographic projection of the second inorganic encapsulation layer on the substrate covers the display area and the peripheral area (Fig. 5B, second inorganic encapsulation layer 330 covering organic encapsulation layer 320. Paragraph 130 teaches 330 is inorganic. An orthographic projection of the second inorganic encapsulation layer on the substrate covers the display area and the peripheral area).
Regarding Claim 17, Choi teaches the display device according to claim 16, wherein the planarization layer comprises:
a first planarization layer covering the driving device layer, wherein a boundary of an orthographic projection of the first planarization layer on the substrate is located within the circuit area (Fig. 5B, first planarization layer 111. A portion of 111 is within circuit area (See annotated figure below)):
and a second planarization layer arranged on a side of the first planarization layer away from the substrate, wherein a boundary of an orthographic projection of the second planarization layer on the substrate is located within the circuit area, and the light emitting layer is arranged on a surface of the second planarization layer away from the substrate (Choi, Fig. 5B, second planarization layer 113. . A boundary of an orthographic projection of the second planarization layer on the substrate is located within the circuit area (See annotated figure below). Light emitting layer OLED on a surface of the second planarization layer away from the substrate).
Regarding Claim 18, Choi teaches the display device according to claim 17, wherein the light emitting layer comprises:
a first electrode layer arranged on the side of the second planarization layer away from the substrate, wherein the first electrode layer comprises a first electrode and an interconnection portion,
an orthographic projection of the first electrode on the substrate is located in the display area, and an orthographic projection of the interconnection portion on the substrate is located in the circuit area (Choi, Fig. 5B, 210 and 75 are the first electrode layer, 210 being the first electrode and 75 being the interconnection portion. An orthographic projection of the first electrode 210 on the substrate is located in the display area DA, and an orthographic projection of the interconnection portion 75 on the substrate is located in the circuit area (See annotated figure below));
a pixel definition layer arranged on a surface of the second planarization layer away from the substrate, wherein an orthographic projection of the pixel definition layer on the substrate covers the display area and the circuit area, and the pixel definition layer is provided with a pixel opening exposing the first electrode and an interconnection opening exposing the interconnection portion (Fig. 5B, pixel definition layer 180. An orthographic projection of the pixel definition layer on the substrate covers the display area DA and the circuit area (See annotated figure below). Paragraph 0114 teaches 180 may include an opening that exposes at least part of the first electrode 210. Fig. 5B shows 180 has an interconnection opening exposing the interconnection portion (See annotated figure below));
a light emitting functional layer covering the pixel definition layer and the first electrode, wherein an orthographic projection of the light emitting functional layer on the substrate is located in the display area (Choi, Fig. 5B, light emitting functional layer 220. 220 covers the pixel definition layer (in the DPX area) and the first electrode. An orthographic projection of the light emitting functional layer on the substrate is located in the display area DA):
and a second electrode layer covering the light emitting functional layer, wherein a boundary of an orthographic projection of the second electrode layer on the substrate is located in the circuit area,
and the second electrode layer is connected to the interconnection portion through the interconnection opening; wherein the first inorganic encapsulation layer covers the second electrode layer (Choi, Fig. 5B, second electrode layer 230. 230 covers the light emitting functional layer 220. A boundary of an orthographic projection of the second electrode layer 230 on the substrate is located in the circuit area (see annotated figure below). 230 is electrically connected to the interconnection portion through the interconnection opening (opening of 180). First encapsulation layer 310 covers second electrode layer 230).
Regarding Claim 19, Choi teaches the display device according to claim 18, wherein the blocking dam comprises a first dam and a second dam, and the second dam surrounds the first dam (Choi, Fig. 5B, first dam PW1 and second dam PW2. Paragraph 0144 teaches second dam PW2 may surround first
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dam PW1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Chen et al. (US Patent Pub 20180061728 A1).
Regarding Claim 10, Choi teaches the display panel according to claim 4, wherein:
a distance between a boundary of the second planarization layer and the first dam is a first distance, and a distance between a boundary of the second planarization layer and the second dam is a second distance (Choi, Fig. 5B, first distance is distance between second planarization layer 113 and first dam PW1. The second distance is the distance between second planarization layer 113 and second dam PW2. See annotated figure below).
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Choi fails to specifically teach the ratio of the second distance to the first distance is 7/5.
However, Chen teaches a display panel with a dam structure having a distance between a boundary of the second planarization layer and the first dam is a first distance, and a distance between a boundary of the second planarization layer and the second dam is a second distance, and a ratio of the second distance to the first distance is 7/5 (Chen, Fig. 5. Paragraph 0032 teaches distances between first dam 16’ and second dam 17 ranges from 45 µm to 105 µm. Paragraph 0039 teaches an example wherein first distance LSR is 117.24 µm, which is the distance from the second planarization layer 130 to the first dam. Calculating the second distance to be 167.24 µm (distance between first dam and second dam being 50 µm + LSR distance of 117.24 µm) and dividing by the first distance LSR to find the ratio of the second distance to the first distance, you get 1.42, or 7/5).
It would have been obvious to one of ordinary skill in the at the time of invention to incorporate the teachings of Chen into the method of Choi by forming a distance between a boundary of the second planarization layer and the first dam with a first distance, and a distance between a boundary of the second planarization layer and the second dam with a second distance, with the ratio of the second distance to the first distance being 7/5. The ordinary artisan would have been motivated to modify Choi in the manner set forth above for at least the purpose of ensuring that the organic capping layer would not be overflowed to the lateral surface of the substrate, prevent water vapor/oxygen permeance at the lateral sides, and also increase the path for water vapor/oxygen permeance by extending the length of the organic capping layer, improving the quality of the display panel (Chen, paragraph 0044).
Conclusion
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/V.R.G./Examiner, Art Unit 2899
/JOHN M PARKER/Examiner, Art Unit 2899