DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 08/31/2023 addition of new claims 16-31 has been noted and entered.
The 08/31/2023 cancellation of claims 1-15 has been noted and entered.
Priority
The foreign priority date of 03/03/2021 of the instant application is noted and entered. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/31/2023, 08/02/2024, 02/07/2025 and 04/25/2025 were filed after the mailing date of the application on 02/15/2022. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-23, 25 and 27-31 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20200044116 A1 (Chen) in view of Park et al, US 20190148601 A1 (Park).
Regarding claim 16; Chen teaches an optoelectronic semiconductor component (1) comprising: a layer stack (Layer Stack – see annotated Figure (3A) of Chen shared in this OA for convenience) comprising: a first semiconductor region of a first conductivity type (202), a second semiconductor region of a second conductivity type (201), an active zone (203) arranged between the first (202) and second (201) semiconductor regions, a side face or a plurality of side faces comprising a first side region delimiting the first semiconductor region (202) sideways and a second side region partially delimiting the second side region sideways, and a first main face (top face of (202)) and a second main face (bottom face of (201)) lying opposite the first main face (top face of (202)), the one or more side faces connecting the first main face (top face of (202)) and the second main face (bottom face of (201)) to one another; a first contact (72) arranged on the first main face (top face of (202)) and configured for electrical contacting the first semiconductor region (202); a second contact (71) arranged on the one or more side faces and configured for the electrical contacting of the second semiconductor region (201); and a dielectric layer (30) arranged between the second contact (71) and the layer stack (Layer Stack – see annotated Figure (3A) of Chen shared in this OA), wherein at least one second side region is at least partially not covered by the dielectric layer (30), wherein the second contact (71) covers a region not covered by the dielectric layer (30), and wherein the second contact (71) is configured for horizontal current injection into the second semiconductor region (201) (see paragraph [0053] of the specification of Chen: “[0053] The light-emitting device 1 includes a plurality of vias 200, and the amount and the arrangement of the plurality of vias 200 are not limited. The plurality of vias 200 may be regularly arranged with a regular interval so that an electrical current can be uniformly spread along the horizontal direction.”).
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Chen does not teach wherein the second semiconductor region comprises a current spreading layer, which is formed from a semiconductor material and which is delimited sideways by the at least one second side region.
Park teaches wherein the second semiconductor region (120) comprises a current spreading layer (122), which is formed from a semiconductor material and which is delimited sideways by the at least one second side region (side region covered by (190) – see Figure (32) and (33) of Park). Chen and Park are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the incident application, to a person having ordinary skill in the art, to modify Chen by using the current spreading layer as disclosed by Park to improve the distribution of the current in the lateral direction leading to a better performance of the light emitting device.
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Regarding claim 17; Chen in view of Park teach all the limitations of claim 16.
Further, Chen teaches wherein the at least one second side region, which is at least partially not covered by the dielectric layer (30), delimits sideways a part of the second semiconductor region (201) extending laterally beyond the first semiconductor region (202).
Regarding claim 18; Chen in view of Park teach all the limitations of claim 16.
Further, Chen teaches wherein the layer stack (Layer Stack – see annotated Figure (3A) of Chen shared in this OA) has a first part forming a first mesa (First Mesa – see annotated Figure (3A) of Chen shared in this OA), which comprises at least the first semiconductor region (202), and a second part forming a second mesa (Second Mesa – see annotated Figure (3A) of Chen shared in this OA), which at least partially protrudes laterally beyond the first part forming the first mesa (First Mesa – see annotated Figure (3A) of Chen shared in this OA) and comprises a part of the second semiconductor region (202).
Regarding claim 19; Chen in view of Park teach all the limitations of claim 18.
Further, Chen teaches wherein the dielectric layer (30) covers at least one first side region.
Regarding claim 20; Chen in view of Park teach all the limitations of claim 16.
Further, Chen teaches wherein the second main face (bottom face of (201)) is substantially not covered by the second contact (71).
Regarding claim 21; Chen in view of Park teaches all the limitations of claim 16.
Further, Chen teaches wherein the one or more side face are at least mostly covered by the second contact (71).
Regarding claim 22; Chen in view of Park teaches all the limitations of claim 16.
Further, Chen teaches wherein the second contact (71) comprises a TCO, a metal or graphene (see paragraph (130) of the specification of Chen: “[0130] The bottom electrode 71 and the top electrode 72 include a metal material including chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or an alloy of the above materials. The bottom electrode 71 and the top electrode 72 include single layer or multilayers. For example, the bottom electrode 71 or the top electrode 72 includes Ti/Au stack, Ti/Pt/Au stack, Cr/Au stack, Cr/Pt/Au stack, Ni/Au stack, Ni/Pt/Au stack or Cr/Al/Cr/Ni/Au stack.”).
Regarding claim 23; Chen in view of Park teaches all the limitations of claim 16.
Further, Chen teaches wherein the second contact (71) consists of a TCO, a metal or graphene (see paragraph (130) of the specification of Chen: “[0130] The bottom electrode 71 and the top electrode 72 include a metal material including chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or an alloy of the above materials. The bottom electrode 71 and the top electrode 72 include single layer or multilayers. For example, the bottom electrode 71 or the top electrode 72 includes Ti/Au stack, Ti/Pt/Au stack, Cr/Au stack, Cr/Pt/Au stack, Ni/Au stack, Ni/Pt/Au stack or Cr/Al/Cr/Ni/Au stack.”).
Regarding claim 25; Chen in view of Park teaches all the limitations of claim 16.
Further, Chen teaches wherein the optoelectronic semiconductor component is externally contactable on the first main face (top surface of (202)) by the first contact (72) and the second contact (71).
Regarding claim 27; Chen in view of Park teaches all the limitations of claim 16.
Further, Chen teaches a method for producing at least one optoelectronic semiconductor component of claim 16, the method comprising: providing a semiconductor wafer comprising a carrier (10) and a semiconductor layer sequence arranged on the carrier; producing at least one layer stack (Layer Stack - see annotated Figure (3) of Chen shared in this OA) by forming at least one first recess (First Recess - see annotated Figure (3) of Chen shared in this OA) in the semiconductor wafer starting from a side (top side) of the semiconductor layer sequence facing away from the carrier (10) and by forming at least one second recess (Second Recess - see annotated Figure (3) of Chen shared in this OA) in the semiconductor wafer starting from the first recess (First Recess - see annotated Figure (3) of Chen shared in this OA); applying the dielectric layer (30) onto the semiconductor wafer such that at least one second side region of the side face of the layer stack (Layer Stack - see annotated Figure (3) of Chen shared in this OA) is at least partially not covered by the dielectric layer (30); and applying an electrically conductive layer (layer that contains the second electrode (71)) configured to form the second contact (71) onto the dielectric layer such that the electrically conductive layer (layer that contains the second electrode (71)) covers the region of the second side region not covered by the dielectric layer (30), wherein the at least one second recess (Second Recess - see annotated Figure (3) of Chen shared in this OA) is at least partially delimited laterally by the at least one second side region.
Regarding claim 28; Chen in view of Park teaches all the limitations of claim 27.
Further, Chen teaches wherein the dielectric layer (30) is generated before the at least one second recess (Second Recess - see annotated Figure (3) of Chen shared in this OA) is produced.
Regarding claim 29; Chen in view of Park teaches all the limitations of claim 27
Further, Chen teaches wherein the at least one first recess (First Recess - see annotated Figure (3) of Chen shared in this OA) is wider than the second recess (Second Recess - see annotated Figure (3) of Chen shared in this OA).
Regarding claim 30; Chen in view of Park teaches all the limitations of claim 27.
Further, Chen teaches wherein the at least one first recess (First Recess - see annotated Figure (3) of Chen shared in this OA) is laterally delimited by first side regions of neighboring layer stacks (Layer Stack - see annotated Figure (3) of Chen shared in this OA) and the at least one second recess (Second Recess - see annotated Figure (3) of Chen shared in this OA) is laterally delimited by second side regions of neighboring layer stacks (Layer Stack - see annotated Figure (3) of Chen shared in this OA).
Regarding claim 31; Chen in view of Park teaches all the limitations of claim 27.
Further, Chen teaches wherein the at least one first recess (First Recess - see annotated Figure (3) of Chen shared in this OA) and the at least one second recess (Second Recess - see annotated Figure (3) of Chen shared in this OA) are generated by etching (see paragraph [0043] of the specification of Chen: “[0043] As shown in FIG. 2 and FIG. 3, the semiconductor stack 20 is selectively etched to form a via 200, a recess 204 and a semiconductor mesa 205 on the semiconductor stack 20.”).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20200044116 A1 (Chen) in view of Park et al, US 20190148601 A1 (Park) in further view of You et al, US 20170365743 A1 (You)
Regarding claim 24; Chen in view of Park teaches all the limitations of claim 16.
However, Chen in view of Park does not teach wherein the second contact is a mirror for the layer stack.
You teaches wherein the second contact (40) is a mirror for the layer stack (see paragraph [0035] of the specification of You: “[0035]… The lower electrode 40 may include a reflective layer 33 and a cover layer 35.”). Chen in view of Park and You are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen in view of Park by making the second electrode a mirror for the layer stack as disclosed by You to improve the efficiency of light extraction from the light emitting device.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20200044116 A1 (Chen) in view of Park et al, US 20190148601 A1 (Park) in further view of Li, US 20210050481 A1 (Li)
Regarding claim 26; Chen in view of Park teaches all the limitations of claim 16.
However, Chen in view of Park does not teach wherein the optoelectronic semiconductor component is a micro-LED chip having lateral dimensions in a range of between 5 µm and 20 µm, inclusive.
Li teaches wherein the optoelectronic semiconductor component is a micro-LED chip having lateral dimensions in a range of between 5 µm and 20 µm, inclusive (see paragraph [0048] of the specification of Li: [0048]… In other embodiments, the light-emitting device may also be a flip-chip type micro LED. The so-called “micro” LED refers to that the LED has a size of 1 μm to 100 μm. In some embodiments, the micro LED may have a maximum width of 20 μm, 10 μm or 5 μm.”). Chen in view of Park and Li are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen in view of Park by using micro-LED devices as disclosed by Li to improve the resolution and quality of the light emitting device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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/MOATAZ KHALIFA/Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815