DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 03/24/2026 amendments of claims 16-17, 27-28 and 31 have been noted and entered.
The 03/24/2026 addition of new claims 32-34 have been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 7-9, filed 03/24/2026, with respect to the rejection(s) of claim(s) 16-31 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Chen et al, US 20200044116 A1 (Chen).
New Grounds of Rejection
New grounds of rejection, prior art reference Chen et al, US 20200044116 A1 (Chen) appears below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 27-31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al, US 20200044116 A1 (Chen).
Regarding claim 27; Chen teaches a method for producing at least one optoelectronic semiconductor component (Chen: First Version of Annotated Fig (3A) shared in this OA: 1), the method comprising:
providing a semiconductor wafer comprising a carrier (10) and a semiconductor layer sequence (Layer Stack) arranged on the carrier (10),
the semiconductor layer sequence (Layer Stack) comprising a first semiconductor region of a first conductivity type (202),
a second semiconductor region of a second conductivity type (201) and an active zone (203) between the first region (202) and the second region (201);
producing at least one layer stack (Layer Stack) by forming at least one first recess (Second Version of Annotated Fig (3A) shared in this OA: First Recess) in the semiconductor wafer starting from a side (First Version of Annotated Fig (3A) shared in this OA: First Main Side) of the semiconductor layer sequence (Layer Stack) facing away from the carrier (10) and by forming at least one second recess(Second Version of Annotated Fig (3A) shared in this OA: Second Recess) in the semiconductor wafer starting from the first recess (Second Version of Annotated Fig (3A) shared in this OA: First Recess); applying a dielectric layer (30) onto the semiconductor wafer such that at least one second side region (First Version of Annotated Fig (3A) shared in this OA: Second Side Region) of a side face (Second Component of the Second Side Face) of the second semiconductor region (201) is not covered by the dielectric layer (30); and applying an electrically conductive layer (71) configured to form a second contact (71) onto the dielectric layer (30) such that the electrically conductive layer (71) covers the at least one second side region (Second Side Region) wherein the second contact (71) is configured for horizontal current injection along a width direction (Y-direction, [0053]: “The light-emitting device 1 includes a plurality of vias 200, and the amount and the arrangement of the plurality of vias 200 are not limited. The plurality of vias 200 may be regularly arranged with a regular interval so that an electrical current can be uniformly spread along the horizontal direction.”. Given that the second contact, composed of element 71 which includes the via 200, covers the side surface of the semiconductor layers and that Chen explicitly states that the current will travel in a horizontal direction and that it is known in the art that spreading the current in the horizontal direction creates a better performing device in terms of the homogeneity of the light produced, it would is reasonable to assume that the current will be injected along a width direction of the semiconductor regions) via the at least one second side region (Second Side Region) into the second semiconductor region (201).
PNG
media_image1.png
922
2003
media_image1.png
Greyscale
Regarding claim 28; Chen teaches all the limitations of the method of claim 27.
Further, Chen teaches wherein the dielectric layer (Chen: Second Version of Annotated Fig (3A) shared in this OA: 30) is formed before forming the at least one second recess (Second Recess).
PNG
media_image2.png
955
1589
media_image2.png
Greyscale
Regarding claim 29; Chen teaches all the limitations of the method of claim 27
Further, Chen teaches wherein the at least one first recess (Chen: Second Version of Annotated Fig (3A) shared in this OA: First Recess) is wider than the second recess (Second Recess).
Regarding claim 30; Chen teaches all the limitations of the method of claim 27.
Further, Chen teaches wherein the at least one first recess (Chen: Second Version of Annotated Fig (3A) shared in this OA: First Recess) is laterally delimited by first side regions of neighboring layer stacks (Layer Stack) and the at least one second recess (Second Recess) is laterally delimited by second side regions of neighboring layer stacks (Layer Stack).
Regarding claim 31; Chen in view of Park teaches all the limitations of the method of claim 27.
Further, Chen teaches wherein the at least one first recess (Chen: Second Version of Annotated Fig (3A) shared in this OA: First Recess) and the at least one second recess (Second Recess) are formed by etching ([0043]: “As shown in FIG. 2 and FIG. 3, the semiconductor stack 20 is selectively etched to form a via 200, a recess 204 and a semiconductor mesa 205 on the semiconductor stack 20.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 16-23, 25 and 32-34 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20200044116 A1 (Chen) in view of Park et al, US 20190148601 A1 (Park).
Regarding claim 16; Chen teaches an optoelectronic semiconductor component (Chen: First Version of Annotated Fig (3A) shared in this OA: 1) comprising:
a layer stack (Layer Stack) comprising: a first semiconductor region of a first conductivity type (202),
a second semiconductor region of a second conductivity type (201),
an active zone (203) arranged between the first (202) and second semiconductor regions (201),
a side face or a plurality of side faces (First Side Face, First and Second Components of the Second Side Face) comprising a first side region (First Side Region) delimiting the first semiconductor region (202) sideways and a second side region (Second Side Region) delimiting the second semiconductor region (201) sideways, and
a first main face (First Main Face) and a second main face (Second Main Face) lying opposite the first main face (First Main Face),
the one or more side faces (First Side Face, First and Second Components of the Second Side Face) connecting the first main face (First Main Face) and the second main face (Second Main Face) to one another;
a first contact (72) arranged on the first main face (First Main Face) and configured for electrical contacting the first semiconductor region (202);
a second contact (71) arranged on the one or more side faces (First Component of Second Side Face) and configured for the electrical contacting of the second semiconductor region (201); and
a dielectric layer (30) arranged between the second contact (71) and the layer stack (Layer Stack), wherein a portion of the second side region (Second Side Region) is at least partially not covered by the dielectric layer (30),
wherein the second contact (71) covers a region not covered by the dielectric layer (30),
wherein the second semiconductor region (201) comprises a current spreading layer, which comprises a semiconductor material and which is delimited sideways by the portion of the second side region (Second Side Region), and
wherein the second contact (71) is configured for horizontal current injection along a width direction (Y-direction, [0053]: “The light-emitting device 1 includes a plurality of vias 200, and the amount and the arrangement of the plurality of vias 200 are not limited. The plurality of vias 200 may be regularly arranged with a regular interval so that an electrical current can be uniformly spread along the horizontal direction.”. Given that the second contact, composed of element 71 which includes the via 200, covers the side surface of the semiconductor layers and that Chen explicitly states that the current will travel in a horizontal direction and that it is known in the art that spreading the current in the horizontal direction creates a better performing device in terms of the homogeneity of the light produced, it would is reasonable to assume that the current will be injected along a width direction of the semiconductor regions) via the portion of the second side region into the second semiconductor region (201).
Chen does not teach wherein the second semiconductor region comprises a current spreading layer, which is formed from a semiconductor material and which is delimited sideways by the at least one second side region.
Park teaches wherein the second semiconductor region (Park: Figs (32)-(33): 120) comprises a current spreading layer (122), which is formed from a semiconductor material and which is delimited sideways by the at least one second side region (side region covered by (190)).
Chen and Park are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the incident application, to a person having ordinary skill in the art, to modify Chen by using the current spreading layer as disclosed by Park to improve the distribution of the current in the lateral direction leading to a better performance of the light emitting device.
PNG
media_image3.png
415
729
media_image3.png
Greyscale
PNG
media_image4.png
583
653
media_image4.png
Greyscale
Regarding claim 17; Chen in view of Park teach all the limitations of the optoelectronic semiconductor component of claim 16.
Further, Chen teaches wherein the portion of the second side region (Chen: First Version of Annotated Fig (3A) shared in this OA: Second Side Region) delimits sideways a part of the second semiconductor region (201) extending laterally beyond the first semiconductor region (202).
Regarding claim 18; Chen in view of Park teach all the limitations of the optoelectronic semiconductor component of claim 16.
Further, Chen teaches wherein the layer stack (Chen: Second Version of Annotated Fig (3A) shared in this OA: Layer Stack) has a first part forming a first mesa (First Mesa), which comprises at least the first semiconductor region (202), and a second part forming a second mesa (Second Mesa), which at least partially protrudes laterally beyond the first part forming the first mesa (First Mesa) and comprises a part of the second semiconductor region (202).
Regarding claim 19; Chen in view of Park teach all the limitations of the optoelectronic semiconductor component of claim 18.
Further, Chen teaches wherein the dielectric layer (Chen: First Version of Annotated Fig (3A) shared in this OA: 30) covers at least one first side region (First Side Region).
Regarding claim 20; Chen in view of Park teach all the limitations of the optoelectronic semiconductor component of claim 16.
Further, Chen teaches wherein the second main face (Chen: First Version of Annotated Fig (3A) shared in this OA: Second Main Face) is substantially not covered by the second contact (71).
Regarding claim 21; Chen in view of Park teaches all the limitations of the optoelectronic semiconductor component of claim 16.
Further, Chen teaches wherein the one or more side face (Chen: First Version of Annotated Fig (3A) shared in this OA: First Side Face, First Component of Second Side Face) are at least mostly covered by the second contact (71).
Regarding claim 22; Chen in view of Park teaches all the limitations of the optoelectronic semiconductor component of claim 16.
Further, Chen teaches wherein the second contact (Chen: First Version of Annotated Fig (3A) shared in this OA: 71) comprises a TCO, a metal or graphene ([0130]).
Regarding claim 23; Chen in view of Park teaches all the limitations of the optoelectronic semiconductor component of claim 16.
Further, Chen teaches wherein the second contact (Chen: First Version of Annotated Fig (3A) shared in this OA: 71) comprises a TCO, a metal or graphene ([0130]).
Regarding claim 25; Chen in view of Park teaches all the limitations of the optoelectronic semiconductor component of claim 16.
Further, Chen teaches wherein the optoelectronic semiconductor component is externally contactable on the first main face (Chen: First Version of Annotated Fig (3A) shared in this OA: First Main Surface) by the first contact (72) and the second contact (71).
Regarding claim 32; Chen in view of Park teaches a method for producing at least one optoelectronic semiconductor component of claim 16.
Further, Chen teaches the method comprising: providing a semiconductor wafer comprising a carrier (Chen: Second Version of Annotated Fig (3A) shared in this OA: 10) and a semiconductor layer sequence (Layer Stack) arranged on the carrier (10);producing at least one layer stack (Layer Stack) by forming at least one first recess (First Recess) in the semiconductor wafer starting from a side of the semiconductor layer sequence (Layer Stack) facing away from the carrier (10) and by forming at least one second recess (Second Recess) in the semiconductor wafer starting from the first recess (First Recess); applying the dielectric layer (30) onto the semiconductor wafer such that the portion of the second side region (First Version of Annotated Fig (3A) shared in this OA: Second Side Region) is not covered by the dielectric layer (30); and applying an electrically conductive layer (71) configured to form the second contact (71) onto the dielectric layer (30).
Regarding claim 33; Chen in view of Park teaches all the limitations of the method of claim 32.
Further, Chen teaches wherein the dielectric layer (Chen: Second Version of Annotated Fig (3A) shared in this OA: 30) is formed before forming the at least one second recess (Second Recess).
Regarding claim 34; Chen in view of Park teaches all the limitations of the method of claim 33.
Further, Chen teaches wherein the at least one first recess (Chen: Second Version of Annotated Fig (3A) shared in this OA: First Recess) is wider than the second recess (Second Recess).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20200044116 A1 (Chen) in view of Park et al, US 20190148601 A1 (Park) in further view of You et al, US 20170365743 A1 (You)
Regarding claim 24; Chen in view of Park teaches all the limitations of the optoelectronic semiconductor component of claim 16.
However, Chen in view of Park does not teach wherein the second contact is a mirror for the layer stack.
You teaches wherein the second contact (You: Fig (4B): 40) is a mirror for the layer stack ([0035]: “… The lower electrode 40 may include a reflective layer 33 and a cover layer 35.”).
Chen in view of Park and You are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen in view of Park by making the second electrode a mirror for the layer stack as disclosed by You to improve the efficiency of light extraction from the light emitting device.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20200044116 A1 (Chen) in view of Park et al, US 20190148601 A1 (Park) in further view of Li, US 20210050481 A1 (Li)
Regarding claim 26; Chen in view of Park teaches all the limitations of the optoelectronic semiconductor component of claim 16.
However, Chen in view of Park does not teach wherein the optoelectronic semiconductor component is a micro-LED chip having lateral dimensions in a range of between 5 µm and 20 µm, inclusive.
Li teaches wherein the optoelectronic semiconductor component is a micro-LED chip having lateral dimensions in a range of between 5 µm and 20 µm, inclusive (Li: [0048]).
Chen in view of Park and Li are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen in view of Park by using micro-LED devices as disclosed by Li to improve the resolution and quality of the light emitting device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights