Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-12 are pending and have been examined.
Priority
Acknowledgment is made of applicant's claim for foreign benefit based on JP2021-038902 filed on 03/11/2021.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-3, 6, 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagashima (US 20100237320 A1 – hereinafter Nagashima).
Regarding Claim 1, Nagashima teaches a manufacturing method of a circuitry including a planar diode (see the entire document; Fig. 6; specifically, ([0062]), and as cited below), comprising:
forming an insulating layer (35 – Fig. 6 – [0062]) having a first pattern shape (plurality of vertical 35) on a substrate (21 – [0062]); and
monolithically forming a functional material layer (29) having a second pattern shape (plurality of 29) complementary to the first pattern shape on the substrate (that is, 35 and 29 alternately formed),
wherein the functional material layer includes a material configured to function as a planar diode having a rectifying property based on a shape and a size (Non-ohmic elements 29 are diodes – see [0062]), and
wherein the second pattern shape has a shape of a circuitry including the planar diode (see [0062]), a first circuit element connected to a first electrode (first electrode 30) of the planar diode, and a second circuit element connected to a second electrode (second electrode 32 – [0062]) of the planar diode.
Regarding Claim 2, Nagashima teaches the manufacturing method of the circuitry including the planar diode according to claim 1, the method further including: laminating a metallic layer (28) at a single process on a first part of the functional material layer except at least a second part of the functional material layer that functions as the planar diode (that is, layer 28 is on the bottom surface of 29 – see Fig. 6).
Regarding Claim 3, Nagashima teaches the manufacturing method of the circuitry including the planar diode according to claim 2, wherein a thickness of the insulating layer is larger than a sum of a thickness of the functional material layer and a thickness of the metallic layer (Fig. 6 shows thickness of 35 is larger than thickness of {29+28}).
Regarding Claim 6, Nagashima teaches the manufacturing method of the circuitry including the planar diode according to claim 1, wherein the planar diode comprises a geometric diode (diode 29 has the same shape as layer 45B or 45D of Fig. 5B of applicant’s drawing).
Regarding Claim 8, Nagashima teaches the manufacturing method of the circuitry including the planar diode according to claim 1, wherein the forming the insulating layer includes forming the insulating layer with a polymer ([0006] teaches memory elements with variable resistance can be formed of a conductive polymer).
Regarding Claim 9, Nagashima teaches the manufacturing method of the circuitry including the planar diode according to claim 1, wherein the forming the insulating layer includes forming the insulating layer with a resist (see [0069]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nagashima.
Regarding Claim 4, Nagashima teaches claim 1 from which claim 4 depends. But, Nagashima does not expressly disclose the method further including: removing the insulating layer by selectively etching.
However, selective etching is a well-known manufacturing process in the art and Nagashima also teaches in [0069] an anisotropic etching process which is a selective etching process.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the anisotropic etching as disclosed by Nagashima to etch the insulating layer for the obvious benefit of stronger bonding and reduced postoperative sensitivity.
Allowable Subject Matter
Claims 5,7, 10-12 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 5: The manufacturing method of the circuitry including the planar diode according to claim 4, wherein the forming the functional material layer includes forming, on the insulating layer, another functional material layer separated from the functional material layer formed on the substrate, wherein the laminating the metallic layer on the second part of the functional material layer includes laminating, on the another functional material layer, another metallic layer separated from the metallic layer, and wherein the selectively etching includes selectively lifting off the another functional material layer and the another metallic layer.
Regarding claim 7: The manufacturing method of the circuitry including the planar diode according to claim 1, wherein the forming the insulating layer includes: forming the insulating layer that is integral on the substrate; pushing a nanoimprint mold against the insulating layer to form the first pattern shape on the insulating layer; and adjusting the first pattern shape of the insulating layer by dry-etching.
Regarding claim 10: The manufacturing method of the circuitry including the planar diode according to claim 1, wherein the forming the functional material layer includes: laminating a nickel layer having the first pattern shape on the substrate; and oxidizing the nickel layer by irradiating with ultraviolet ray at a temperature equal to or lower than 500°C.
Regarding claim 11: The manufacturing method of the circuitry including the planar diode according to claim 1, wherein the forming the functional material layer includes: laminating a nickel layer on the substrate; oxidizing the nickel layer by irradiating with ultraviolet ray at a temperature equal to or lower than 500°C; and realizing a self-forming of a shape of the planar diode included in the first pattern shape by a deformation of the nickel layer due to oxidation.
Regarding claim 12: The manufacturing method of the circuitry including the planar diode according to claim 1, wherein the circuitry including the shape of the second pattern shape further includes an antenna with a feed section connected to the first circuit element and the second circuit element.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898