DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/08/2025 have been fully considered but they are not persuasive.
Applicant argues on pages 17-18 of the REMARKS/ARGUMENTS, “Assuming, in arguendo, that these comparisons are accurate, Fuergut does not teach, suggest, or claim each feature of claim 1. As shown below in FIG. 5B of Fuergut, the encapsulant 23 and plurality of vertical contacts 25 (the claimed intermediate connecting portion 4) are not juxtaposed to the die carrier 21 (the claimed electronic device 2) in the lateral direction, as required by claim 1”. The Office respectfully disagrees. Claim 1 states “an intermediate connecting portion which is juxtaposed to the electronic device in the lateral direction, which includes a first insulation layer and a first wiring layer, and of which the first wiring layer is connected to the one surface of the metal block via a first conductive via that penetrates the first insulation layer”. Note that the claimed “portion” is not structurally limited nor defined in the claim language, and is interpreted by the Office as a region or part. The claimed portion is unbounded and not limited by the current claim language. As seen by the annotated Fig 1 below, the intermediate connecting portion is shown in a darker shade, and is formed of a region or portion comprising 23 and 25. This region comprises areas that are juxtaposed to 22. Juxtaposed is interpreted as placing unsimilar things close together or side by side. As seen by Fig 1, the portion or region comprising 23 and 25 is not similar to 21 and not similar to 22, and the portions are to a side of a portion of 21 and to a side of a part of 22. As seen in the dotted rectangular box, there are portions of 23,25 that include a first insulating layer 23 and first wiring layer 25 and are on the side of the electronic device 22. First wiring 25 is shown connected to the upper surface of block 21 via a first conductive via (see 25 passing vertically through 23) that penetrates the first insulation layer 23. Applicant is advised to better structurally and physically claim the “intermediate connecting portion”.
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Annotated Fig 1 from Fuergut (US 2022/0102311 A1)
Applicant argues on pages 17-18 of the REMARKS/ARGUMENTS, “Neither does Fuergut teach that the plurality of vertical contacts 25 (the claimed first wiring layer W1) are connected to the upper surface of die carrier 21 (the claimed one surface of the metal block3) via the plurality of vertical contacts 25 (the claimed first conductive via V1) that penetrates the encapsulant 23 (the claimed first insulation layer R1) as required by claim 1” It is unclear how the plurality of vertical contacts 25 could be connected to the upper surface of the die carrier 21 via themselves.. The Office respectfully disagrees. As seen in Fig 1 and 5, vertical contacts 24,25,26 ([0027]) comprises an elongated linear shape portion formed of metal extending vertically through the insulating layer 23 and a portion attached to 22A and attached to 21. Thus Fuergut discloses the plurality bonded contacts portions 25 interface and are connected to the upper surface of 21. The wider contact portions interface with the vertical elongated portion of 25 through 23. Note that the Applicant shows in Fig 2 of the Applicant’s figures V1 integrally interfacing with W1. Similarly, Fuergut teaches of an elongated portion of 24-26 through insulating 23 having a wider portion interfacing with the surfaces of 21 and 22.
Applicant argues on pages 17-18 of the REMARKS/ARGUMENTS, “Finally, it is clear from FIG. 5B of Fuergut, that Fuergut includes a step in the die carrier 21 itself, which clearly differs from the configuration of the intermediate connection 4 of the present application”. The Office respectfully disagrees. The claim has not structurally limited the surface of the metal block to not include a stepped surface. The claim requires “a metal block which has electrical conductivity and a heat-transfer property, which has one surface to which the first connecting terminal of the electronic device is connected, and of which a dimension in a lateral direction is larger than that of the electronic device”. Fuergut teaches of a metal block 21 which comprises a stepped upper surface the first connecting terminal 22B of the electronic device 22 is connected, and of which a dimension in a lateral direction (the dimension of the stepped upper surface of 21 is wider than the width of 22) is larger than that of the electronic device 22.
Applicant argues on pages 17-18 of the REMARKS/ARGUMENTS, “On the other hand, the closer the first wiring layer W1 and the second connection terminals 2b are, the greater the possibility of a short circuit occurring at high voltages. This problem is solved by claim 1 of the present application, but is not addressed by Fuergut, nor is it solved by the teachings or arrangements of Fuergut. Therefore, Fuergut does not teach, suggest, or claim each feature of claim 1”. The Office respectfully disagrees. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a short circuit occurring at high voltages) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant argues on pages 18-19 of the REMARKS/ARGUMENTS, “Further, the addition of Lin does not cure these deficiencies. Lin does not teach "an intermediate connecting portion which is juxtaposed to the electronic device in the lateral direction, which includes a first insulation layer and a first wiring layer, and of which the first wiring layer is connected to the one surface of the metal block via a first conductive via that penetrates the first insulation layer," as recited in claim 1. Instead, Lin is silent regarding these features. Additionally, similarly to Fuergut, Lin teaches a step in the substrate 100, which differs from the configuration of the present application. Therefore, neither Fuergut, nor Lin, nor their combinations teach each future of claim 1”. The Office respectfully disagrees. The claim has not structurally limited the surface of the metal block to not include a stepped surface. The claim requires “a metal block which has electrical conductivity and a heat-transfer property, which has one surface to which the first connecting terminal of the electronic device is connected, and of which a dimension in a lateral direction is larger than that of the electronic device”. Fuergut teaches of a metal block 21 which comprises a stepped upper surface the first connecting terminal 22B of the electronic device 22 is connected, and of which a dimension in a lateral direction (the dimension of the stepped upper surface of 21 is wider than the width of 22) is larger than that of the electronic device 22.
Allowable Subject Matter
Claims 6, 8, 14 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 17 is allowed.
The following is an examiner’s statement of reasons for allowance: the prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the independent claim 17, in such a manner that a rejection under 35 U.S.C. 102 or 103 would be improper.
The prior art fails to teach a combination of all the claimed features as presented in independent claim 17 with the allowable feature being: a manufacturing method of a device embedded substrate into which is embedded an electronic device provided with a first connecting terminal on one surface and a second connecting terminal on another surface, comprising: a block preparation step of preparing a metal block which has electrical conductivity and a heat-transfer property and of which a dimension in a lateral direction is larger than that of the electronic device; an intermediate connection step of separating a part of the inner wiring layer opposing the metal block by patterning as a first wiring layer and providing a first conductive via which connects the first wiring layer and one surface of the metal block to each other; a device accommodation step of exposing a part of the one surface of the metal block by counterboring and accommodating the electronic device so that the first connecting terminal comes into contact with the metal block.
One close prior art Fuergut (US 2022/0102311 A1) teaches of a manufacturing method (Fig 1,5) of a device embedded substrate (100) into which is embedded an electronic device (22) provided with a first connecting terminal (22B; [0023]) on one surface (lower surface of 22) and a second connecting terminal (22A) on another surface, the manufacturing method comprising: a block preparation step of preparing a metal block (21; [0037]) which has electrical conductivity ([0028,0037] “electrically connected”, “direct copper bond”; copper has electrical conductivity property) and a heat-transfer property (“metal block”, “direct copper bond”; metal and copper have heat transfer property) and of which a dimension (width of 21) in a lateral direction is larger than that of the electronic device (22); an embedding step of forming a second insulation layer (10; [0024]) and an inner wiring layer (layer of 24 interfacing with 22) so as to embed the metal block (21); a buildup step of stacking a third insulation layer (30) and a second wiring layer (40-42) on the inner wiring layer so as to embed the electronic device (22); and a via connection step of forming (Fig 5D), in the second wiring layer, a first terminal conducting portion which is connected to the first wiring layer by a second conductive via that penetrates the third insulation layer (23) and a second terminal conducting portion which is connected to the second connecting terminal of the electronic device by a third conductive via that penetrates the third insulation layer; however Fuergut does not teach an intermediate connection step of separating a part of the inner wiring layer opposing the metal block by patterning as a first wiring layer and providing a first conductive via which connects the first wiring layer and one surface of the metal block to each other; a device accommodation step of exposing a part of the one surface of the metal block by counterboring and accommodating the electronic device so that the first connecting terminal comes into contact with the metal block.
Therefore claims 17 is allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 4, 7, 9 – 12 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Fuergut (US 2022/0102311 A1).
Regarding Claim 1, Fuergut discloses a device embedded substrate (Fig 1,5) into which is embedded an electronic device (22) provided with a first connecting terminal (22B; [0023]) on one surface (lower surface of 22) and a second connecting terminal (22A) on another surface, the device embedded substrate (200) comprising: a metal block (21; [0037]) which has electrical conductivity ([0028,0037] “electrically connected”, “direct copper bond”; copper has electrical conductivity property) and a heat-transfer property (“metal block”, “direct copper bond”; metal and copper have heat transfer property), which has one surface (upper surface of 21) to which the first connecting terminal (22B) of the electronic device (22) is connected, and of which a dimension (width of 21) in a lateral direction is larger than that of the electronic device (22); an intermediate connecting portion (about 23,25) which is juxtaposed to the electronic device in the lateral direction, which includes a first insulation layer (23) and a first wiring layer (layer of 25 interfacing with 21), and of which the first wiring layer (25) is connected to the one surface (upper surface of 21) of the metal block via a first conductive via (see 25 passing vertically through 23 in Fig 5) that penetrates the first insulation layer (23); a second insulation layer (10; [0024]) which accommodates the metal block (21); and a third insulation layer (30; [0025]) which is stacked on the second insulation layer (10) so as to embed the electronic device (22) and on which a second wiring layer (40) is stacked, wherein the second wiring layer (40,41,42) includes a first terminal conducting portion (41) which is connected to the first wiring layer (layer where 25 interfaces with 21) via a second conductive via (30A.1) that penetrates the third insulation layer (30) and a second terminal conducting portion (40) which is connected to the second connecting terminal (22A) of the electronic device via a third conductive via (30A.1) that penetrates the third insulation layer (30).
Regarding Claim 2, Fuergut further discloses the device embedded substrate (Fig 1,5) according to claim 1, wherein a distance to the electronic device (22) in the lateral direction from the first wiring layer (layer with 25; a distance from 25 to 22 is greater than a distance from 23 to 22) is greater than a distance to the electronic device (22) in the lateral direction from the first insulation layer (23).
Regarding Claim 3, Fuergut further discloses the device embedded substrate (Fig 1,5) according to claim 1, wherein a conductive path constituted of the first conductive via (vertical connection at 25) and the second conductive via (30A.1) is provided on both sides in the lateral direction so as to sandwich the electronic device (22).
Regarding Claim 4, Fuergut further discloses the device embedded substrate (Fig 1,5) according to claim 1, wherein a distance from the second wiring layer (40,41,42) to the first wiring layer (layer with 25) is set the same as a distance (see Fig 1) from the second wiring layer (40,41,42) to the second connecting terminal (22A) of the electronic device.
Regarding Claim 7, Fuergut further discloses the device embedded substrate (Fig 1,5) according to claim 1, wherein the first conductive via (25) is a stacked via (vertically connecting structure at 25 is stacked onto 30A.1) or a staggered via.
Regarding Claim 9, Fuergut discloses a manufacturing method (Fig 1,5) of a device embedded substrate (100) into which is embedded an electronic device (22) provided with a first connecting terminal (22B; [0023]) on one surface (lower surface of 22) and a second connecting terminal (22A) on another surface, the manufacturing method comprising: a block preparation step of preparing a metal block (21; [0037]) which has electrical conductivity ([0028,0037] “electrically connected”, “direct copper bond”; copper has electrical conductivity property) and a heat-transfer property (“metal block”, “direct copper bond”; metal and copper have heat transfer property) and of which a dimension (width of 21) in a lateral direction is larger than that of the electronic device (22); an intermediate connection (about 23,25) step (Fig 5A) of connecting the first connecting terminal (22B) of the electronic device (22) to one surface of the metal block (21), stacking (Fig 5B) a first insulation layer (23) and a first wiring layer (layer of 25 interfacing with 21) by juxtaposing the first insulation layer (23) and the first wiring layer (layer of 25) in the lateral direction on the electronic device (22), and connecting the first wiring layer (layer of 25) with a first conductive via (see 25 passing vertically through 23 in Fig 5) that penetrates the first insulation layer (23); an accommodation step (Fig 5C) of accommodating the metal block (21) in a second insulation layer (10; [0024]); a buildup step of stacking a third insulation layer (30; [0025]) and a second wiring layer (40,41,42) on the second insulation layer (30) so as to embed the electronic device (22); and a via connection step of forming (Fig 5D), in the second wiring layer (40,41,42), a first terminal conducting portion (41) which is connected to the first wiring layer by a second conductive via (30A.1) that penetrates the third insulation layer (23) and a second terminal conducting portion (40) which is connected to the second connecting terminal (22A) of the electronic device by a third conductive via (30A.1) that penetrates the third insulation layer (30).
Regarding Claim 10, Fuergut further discloses the manufacturing method of a device embedded substrate (Fig 1,5) according to claim 9, wherein a distance to the electronic device (22) in the lateral direction from the first wiring layer (layer with 25; a distance from 25 to 22 is greater than a distance from 23 to 22) is set greater than a distance to the electronic device (22) in the lateral direction from the first insulation layer (23).
Regarding Claim 11, Fuergut further discloses the manufacturing method of a device embedded substrate (Fig 1,5) according to claim 9, wherein a conductive path constituted of the first conductive via (vertical connection at 25) and the second conductive via (30A.1) is provided on both sides in the lateral direction so as to sandwich the electronic device (22).
Regarding Claim 12, Fuergut further discloses the manufacturing method of a device embedded substrate (Fig 1,5) according to claim 9, wherein a distance from the second wiring layer (40,41,42) to the first wiring layer (layer with 25) is set the same as a distance (see Fig 1) from the second wiring layer (40,41,42) to the second connecting terminal (22A) of the electronic device.
Regarding Claim 15, Fuergut further discloses the manufacturing method of a device embedded substrate (Fig 1,5) according to claim 9, wherein the first conductive via (25) is a stacked via (vertically connecting structure at 25 is stacked onto 30A.1) or a staggered via.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Fuergut (US 2022/0102311 A1) as applied to claims 1 and 9 above, and further in view of Lin (US 2018/0019178 A1).
Regarding Claim 5, Fuergut discloses the limitations of the preceding claim including the second wiring layer, the first wiring layer and the second connecting terminal of the electronic device.
Fuergut does not disclose (in Fig 1) the device embedded substrate according to claim 1, wherein a distance from the second wiring layer to the first wiring layer is set shorter than a distance from the second wiring layer to the second connecting terminal of the electronic device.
Lin (US 2018/0019178 A1) teaches of a device embedded substrate (Fig 1), wherein a distance from a second wiring layer (130) to a metal block (102) is set shorter than a distance ([0031] “the first height H1 of the first top surface 101 in addition with the third height H3 at where the first chip 110 is disposed above the first top surface 101 may be smaller than the second height H2 of the second top surface 102 of the substrate 100”) from the second wiring layer (130) to a second connecting terminal (110) of an electronic device (110).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as disclosed by Fuergut, wherein a distance from the second wiring layer to the metal block is set shorter than a distance from the second wiring layer to the second connecting terminal of the electronic device as taught by Lin, in order to provide additional protection of the embedded component and increase product yield, and provide more manufacturing and production flexibility (Lin, [0063]), such that a distance from the second wiring layer to the first wiring layer is set shorter than a distance from the second wiring layer to the second connecting terminal of the electronic device.
Regarding Claim 13, Fuergut discloses the limitations of the preceding claim including the second wiring layer, the first wiring layer and the second connecting terminal of the electronic device.
Fuergut does not disclose (in Fig 1,5) the manufacturing method of a device embedded substrate according to claim 9, wherein a distance from the second wiring layer to the first wiring layer is set shorter than a distance from the second wiring layer to the second connecting terminal of the electronic device.
Lin (US 2018/0019178 A1) teaches of a device embedded substrate (Fig 1), wherein a distance from a second wiring layer (130) to a metal block (102) is set shorter than a distance ([0031] “the first height H1 of the first top surface 101 in addition with the third height H3 at where the first chip 110 is disposed above the first top surface 101 may be smaller than the second height H2 of the second top surface 102 of the substrate 100”) from the second wiring layer (130) to a second connecting terminal (110) of an electronic device (110).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the method as disclosed by Fuergut, wherein a distance from the second wiring layer to the metal block is set shorter than a distance from the second wiring layer to the second connecting terminal of the electronic device as taught by Lin, in order to provide additional protection of the embedded component and increase product yield, and provide more manufacturing and production flexibility (Lin, [0063]), such that a distance from the second wiring layer to the first wiring layer is set shorter than a distance from the second wiring layer to the second connecting terminal of the electronic device.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROSHN K VARGHESE/ Primary Examiner, Art Unit 2896