DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, directed to claims 1-4, 6-8, 10-13 and 15 in the reply filed on November 10, 2025 is acknowledged. Claims 5, 9 and 14 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6-8, 10-13 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 1, the claim recites, “and that insulation-isolates a gate and a semiconductor substrate from each other by an insulating film” which is indefinite as it does not provide a clear physical structure.
The claim recites, “a first step of depositing a protective dielectric film on a sidewall of the stacked film including the first semiconductor layers and the second semiconductor layers that are formed by the etching; a second step of subjecting the protective dielectric film to anisotropic etching in a vertical direction to expose a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer;” which is indefinite since as per step 1 the protective dielectric film is deposited only on the sidewall of the stacked film not on the horizontal surface of the lowermost semiconductor layer that is, the surface of the lowermost semiconductor layer is already exposed. Therefore, there would be no dielectric film to etch in the second step to exposed the surface as it would be already exposed.
The claim recites, “a third step of repeating the first step and the second step a plurality of times using a material of the insulating film different from that of the protective dielectric film, ...;” which is indefinite as it fails to clearly explain how the material substitution as required by the third step affects the structural result or how the steps are modified during repetition.
Claims 2-4 and 6-8 depend upon claim 1 and do not rectify the problem therefore, they are also rejected.
Regarding claim 7, the claim recites, “for insulation-isolating the gate and the semiconductor substrate is deposited and subjected to vertical etching”, which is indefinite as it is not clear if the insulating film and insulation-isolates recited in claim 1 are the same or different from the insulating film and insulation-isolating recited in claim 7.
Regarding claim 10, the claim recites, The claim recites, “a first step of depositing a protective dielectric film on a sidewall of the stacked film including the first semiconductor layers and the second semiconductor layers that are formed by the etching; a second step of subjecting the protective dielectric film to anisotropic etching in a vertical direction to expose a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer;” which is indefinite since as per step 1 the protective dielectric film is deposited only on the sidewall of the stacked film not on the horizontal surface of the lowermost semiconductor layer that is, the surface of the lowermost semiconductor layer is already exposed. Therefore, there would be no dielectric film to etch in the second step to exposed the surface as it would be already exposed.
The claim further recites, “a third step of repeating the first step and the second step a plurality of times using a material of an insulating film different from that of the protective dielectric insulating film”, which is indefinite as it fails to clearly explain how the material substitution as required by the third step affects the structural result or how the steps are modified during repetition. It is not clear what is the relationship of the insulating film to the structure.
The claim further recites, “forming a stacked film of protective dielectric films” which is indefinite as it not clear how this stacked film of protective dielectric films is structurally related to the protective dielectric film formed in the first step. The term stacked implies a layered arrangement yet the claim fails to specify whether the film from first step constitutes the first layer of the stack, acts as a base layer for the stack, or is entirely replaced by the stack. Without defining the spatial or physical interface between the initial protective dielectric film and the subsequent stacked film the scope of the resulting structure cannot be determined.
Claims 11-13 and 15 depend upon claim 10 and do not rectify the problem therefore, they are also rejected.
Regarding claim 15, “the claim recites, “wherein in the first step and the third step, the protective dielectric film is deposited by an ALD method”, which is indefinite and inconsistent as the protective film is formed in the first step whereas in the third step a distinct stacked protective film is formed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (US 10, 103,238 B1) in view of Song et al. (US 2023/0261079 A1; hereafter Song) and Ebrish et al. (US 2020/0279913 A1; hereafter Ebrish).
Regarding claim 1, Zang teaches a method for manufacturing a semiconductor device (see e.g., Figures 1, 11-16) that includes a stacked channel in which thin or sheet-shaped channels are stacked in a direction perpendicular to a substrate in a gate formation region (see e.g., nanosheet channel layers 10 are stacked in a direction perpendicular to the substrate 14 in a sacrificial gate structure 20 region, Column 3, Lines 5-20, Figure 11), and that insulation-isolates a gate and a semiconductor substrate from each other by an insulating film (see e.g., conformal dielectric layer 58 fills up the cavity 38 to define a dielectric isolation region 36, Figure 16),
the semiconductor device having a structure in which a stacked film is provided in which a plurality of first semiconductor layers and a plurality of second semiconductor layers are alternately stacked on the semiconductor substrate (see e.g., semiconductor layers 11 and 13 are formed in an alternating sequence on a substrate 14. The semiconductor layers 11 are composed of silicon and the semiconductor layers 13 are composed of silicon germanium, Column 2, Lines 25-35, Figure 1), the gate and a gate sidewall spacer film are further formed on the stacked film (see e.g., sacrificial gate structures 20 are formed on the top surface of the semiconductor layers 11, 13 in the layer stack. Each sacrificial gate structure 20 is covered by a dielectric cap 22 that is located on its top surface, and dielectric spacers 24 that are located adjacent to its vertical sidewalls, Colum 2, Lines 60-65, Figure 1), a part of the stacked film is removed by etching along the gate sidewall spacer film, and a part or all of a lowermost first semiconductor layer or a part or all of a lowermost second semiconductor layer formed on the lowermost first semiconductor layer are left without being etched (see e.g., the semiconductor layer 19 may have the same composition as of semiconductor layers 13 and maybe thicker than the individual semiconductor layers 13. Trenches 28 are formed that extend through the semiconductor layers 11 and 13 to form nanosheet channel layers 10 and sacrificial layers 12. The trenches 28 are not extended through the semiconductor layer 19, instead the trenches 28 are terminated at the top surface of the semiconductor layer 19, Column 7, Lines 4-11, Figure 11), the method comprising:
a first step of depositing a protective dielectric film on a sidewall of the stacked film including the first semiconductor layers and the second semiconductor layers that are formed by the etching (see e.g., a conformal dielectric layer 31 is formed on a sidewall of the nanosheet channel layers 10 and the sacrificial layers 12, Column 7, Lines 25-30, Figure 12);
a second step of subjecting the protective dielectric film to anisotropic etching in a vertical direction (see e.g., the conformal dielectric layer 31 is subjected to one or more etching processes, such as reactive ion etching (RIE) in a vertical direction, Column 7, Lines 30-36, Figures 12 and 13);
a fourth step of removing the lowermost first semiconductor layer or the lowermost first semiconductor layer and the lowermost second semiconductor layer by etching (see e.g., the sacrificial layer 18 is removed by etching, Column 7, Lines 51-60, Figure 15).
Zang does not explicitly teach
“… subjecting the protective dielectric film to anisotropic etching in a vertical direction to expose a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer”.
Zang teaches the specific sequence, etching the semiconductor layer first then forming the dielectric layer. Given the finite options of either forming the dielectric layer before or after patterning the semiconductor layer, switching the order of the steps is a matter of routine technique.
It would be obvious to try any one of the combination. The rationale to support a conclusion that the claim would have been obvious is that “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103.”KSR, 550 U.S. at 421, 82 USPQ2d at 1397. MPEP 2143 (E).
In a similar field of endeavor Song teaches
… subjecting the protective dielectric film to anisotropic etching in a vertical direction to expose a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer (see e.g., a protection layer may be conformally stacked on the entire surface of the substrate 100, and may then be anisotropically etched to form a protective spacer SSP thereby exposing a surface of the first semiconductor pattern SP1, Paras [0044], [0093], Figures 10B, 11B).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Song’s teachings of … subjecting the protective dielectric film to anisotropic etching in a vertical direction to expose a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer in the method of Zang as it is a routine technique in semiconductor manufacturing to achieve predictable results.
Zang does not explicitly teach
“a third step of repeating the first step and the second step a plurality of times using a material of the insulating film different from that of the protective dielectric film, and forming, on the sidewall, a stacked film of protective dielectric films including the protective dielectric film and a plurality of protective dielectric films different from the protective dielectric film; and”
In a similar field of endeavor Ebrish teaches
a third step of repeating the first step and the second step a plurality of times using a material of the insulating film different from that of the protective dielectric film, and forming, on the sidewall, a stacked film of protective dielectric films including the protective dielectric film and a plurality of protective dielectric films different from the protective dielectric film; and (see e.g., a nitride layer 502A, such as silicon nitride, is conformally deposited over the structure 100. Next, a protective oxide layer 602, such as silicon oxycarbide, silicon oxynitride, is deposited on the structure 100 by atomic layer deposition (ALD) with a thickness of about 1nm to 5nm. Because the thickness is in the range of 1nm to 5nm, this indicates that multiple ALD cycles are performed to build up the protective layer, Paras [0046], Figure 5).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Ebrish’s teachings of a third step of repeating the first step and the second step a plurality of times using a material of the insulating film different from that of the protective dielectric film, and forming, on the sidewall, a stacked film of protective dielectric films including the protective dielectric film and a plurality of protective dielectric films different from the protective dielectric film in the method of Zang in order prevent excess gauging during subsequent RIE processes that are applied during the semiconductor device fabrication process.
Regarding claim 3, Zang, as modified by Song and Ebrish, teaches the limitations of claim 1 as mentioned above. Zang further teaches
the first semiconductor layers are silicon germanium (see e.g., semiconductor layers 13 are composed of silicon germanium, Column 2, Lines 25-32, Figure 1), and the second semiconductor layers are silicon (see e.g., semiconductor layers 11 are composed of silicon, Column 2, Lines 25-32, Figure 1).
Zhao does not explicitly teach
wherein the semiconductor substrate is silicon,
In a similar field of endeavor Song teaches
wherein the semiconductor substrate is silicon (see e.g., the substrate maybe a silicon substrate, Para [0030], Figure 10B),
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Song’s teachings of wherein the semiconductor substrate is silicon in the method of Zang as it is a commonly used substrate in semiconductor manufacturing.
Regarding claim 10, Zang teaches a plasma processing method for performing plasma processing on a structure (see e.g., Figures 1, 11-16) in which a stacked film is provided in which a plurality of first semiconductor layers and a plurality of second semiconductor layers are alternately stacked on a semiconductor substrate (see e.g., nanosheet channel layers 10 are stacked in a direction perpendicular to the substrate 14 in a sacrificial gate structure 20 region, Column 3, Lines 5-20, Figure 11), a gate and a gate sidewall spacer film are further formed on the stacked film (see e.g., sacrificial gate structures 20 are formed on the top surface of the semiconductor layers 11, 13 in the layer stack. Each sacrificial gate structure 20 is covered by a dielectric cap 22 that is located on its top surface, and dielectric spacers 24 that are located adjacent to its vertical sidewalls, Colum 2, Lines 60-65, Figure 1), a part of the stacked film is removed by etching along the gate sidewall spacer film, and a part or all of a lowermost first semiconductor layer or a part or all of a lowermost second semiconductor layer formed on the lowermost first semiconductor layer are left without being etched (see e.g., the semiconductor layer 19 may have the same composition as of semiconductor layers 13 and maybe thicker than the individual semiconductor layers 13. Trenches 28 are formed that extend through the semiconductor layers 11 and 13 to form nanosheet channel layers 10 and sacrificial layers 12. The trenches 28 are not extended through the semiconductor layer 19, instead the trenches 28 are terminated at the top surface of the semiconductor layer 19, Column 7, Lines 4-11, Figure 11), the plasma processing method comprising continuously performing:
a first step of depositing a protective dielectric film on a sidewall of the stacked film including the first semiconductor layers and the second semiconductor layers that are formed by the etching (see e.g., a conformal dielectric layer 31 is formed on a sidewall of the nanosheet channel layers 10 and the sacrificial layers 12, Column 7, Lines 25-30, Figure 12);
a second step of subjecting anisotropic etching to the protective dielectric film in a vertical direction to expose a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer (see e.g., the conformal dielectric layer 31 is subjected to one or more etching processes, such as reactive ion etching (RIE) in a vertical direction, Column 7, Lines 30-36, Figures 12 and 13);
a fourth step of removing the lowermost first semiconductor layer or the lowermost first semiconductor layer and the lowermost second semiconductor layer by etching (see e.g., the sacrificial layer 18 is removed by etching, Column 7, Lines 51-60, Figure 15).
Zang does not explicitly teach
a third step of repeating the first step and the second step a plurality of times using a material of an insulating film different from that of the protective dielectric insulating film, and forming, on the sidewall, a stacked film of protective dielectric films; and
In a similar field of endeavor Ebrish teaches
a third step of repeating the first step and the second step a plurality of times using a material of an insulating film different from that of the protective dielectric insulating film, and forming, on the sidewall, a stacked film of protective dielectric films (see e.g., a nitride layer 502A, such as silicon nitride, is conformally deposited over the structure 100. Next, a protective oxide layer 602, such as silicon oxycarbide, silicon oxynitride, is deposited on the structure 100 by atomic layer deposition (ALD) with a thickness of about 1nm to 5nm. Because the thickness is in the range of 1nm to 5nm, this indicates that multiple ALD cycles are performed to build up the protective layer, Paras [0046], Figure 5);
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Ebrish’s teachings of a third step of repeating the first step and the second step a plurality of times using a material of an insulating film different from that of the protective dielectric insulating film, and forming, on the sidewall, a stacked film of protective dielectric films in the method of Zang in order prevent excess gauging during subsequent RIE processes that are applied during the semiconductor device fabrication process.
Zang does not explicitly teach
“…removing the lowermost first semiconductor layer or the lowermost first semiconductor layer and the lowermost second semiconductor layer by isotropic etching”
In a similar field of endeavor Song teaches
…removing the lowermost first semiconductor layer or the lowermost first semiconductor layer and the lowermost second semiconductor layer by isotropic etching (see e.g., isotropic etching process may be performed to remove the first semiconductor pattern SP1, Para [0094], Figure 10B, 11B)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Song’s teachings of …removing the lowermost first semiconductor layer or the lowermost first semiconductor layer and the lowermost second semiconductor layer by isotropic etching in the method of Zang in order to achieve desired structural definition.
Regarding claim 15, Zang, as modified by Song and Ebrish, teaches the limitations of claim 1 as mentioned above. Zang further teaches
wherein in the first step and the third step, the protective dielectric film is deposited by an ALD method (see e.g., conformal dielectric film 31 deposited by ALD, Column 3, Lines 53-60, Figure 12).
Claims 2, 6-8 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (US 10, 103,238 B1) in view of Song et al. (US 2023/0261079 A1; hereafter Song) and Ebrish et al. (US 2020/0279913 A1; hereafter Ebrish) and further in view of Zhou et al. (US 2019/0157095 A1; hereafter Zhou).
Regarding claim 2, Zang, as modified by Song and Ebrish, teaches the limitations of claim 1 as mentioned above. Zang does not explicitly teach
“wherein the first step to the fourth step are performed continuously in the same plasma processing apparatus”.
Zang is silent as to the processing steps are either performed in the same or different chambers thereby not precluding that all the processing steps maybe performed in the same plasma processing chamber.
In a similar field of endeavor Zhou teaches integration of ALD steps and etch steps in a plasma chamber. By using in-situ ALD rather than ALD conducted in a separate chamber standalone ALD tool and additional cleaning tools are eliminated. Furthermore, processing time and costs are reduced by eliminating additional substrate transfers and clean time.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement processing steps continuously in the same plasma apparatus since use of separate chambers for deposition and etching increases processing time, processing steps, and costs, thus adversely affecting throughput. Moreover, the use of separate chambers requires transferring substrates from one chamber to another, which entails vacuum breaks and increases the likelihood of unwanted materials or particles coming into contact with the substrates. This may cause loss of material functionality and/or integrity on the substrate.
Regarding claim 6, Zang, as modified by Song and Ebrish, teaches the limitations of claim 1 as mentioned above. Zang does not explicitly teach
“wherein vertical etching of the gate sidewall spacer film in order to form the gate sidewall spacer film, a step of removing a part of the stacked film including the first semiconductor layers and the second semiconductor layers by vertical etching, the first step to the fourth step, and a step of removing the stacked film of the protective dielectric films by isotropic etching are performed continuously in the same plasma processing apparatus”.
Zang is silent as to the processing steps are either performed in the same or different chambers thereby not precluding that all the processing steps maybe performed in the same plasma processing chamber.
In a similar field of endeavor Zhou teaches integration of ALD steps and etch steps in a plasma chamber. By using in-situ ALD rather than ALD conducted in a separate chamber standalone ALD tool and additional cleaning tools are eliminated. Furthermore, processing time and costs are reduced by eliminating additional substrate transfers and clean time.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement processing steps continuously in the same plasma apparatus since use of separate chambers for deposition and etching increases processing time, processing steps, and costs, thus adversely affecting throughput. Moreover, the use of separate chambers requires transferring substrates from one chamber to another, which entails vacuum breaks and increases the likelihood of unwanted materials or particles coming into contact with the substrates. This may cause loss of material functionality and/or integrity on the substrate.
Regarding claim 7, Zang, as modified by Song and Ebrish, teaches the limitations of claim 1 as mentioned above. Zang further teaches
a first insulating film for insulation-isolating the gate and the semiconductor substrate is deposited and subjected to vertical etching (see e.g., a conformal dielectric layer 58 deposited and isotopically etched to form dielectric spacers 60 that fill the cavities 29. The conformal dielectric layer 58 also fills the cavities 38 to define the dielectric isolation region 36, Column 7, Lines 6166, Column 8, Lines 1-5, Figure 16).
Zang does not explicitly teach
“wherein vertical etching of the gate sidewall spacer film in order to form the gate sidewall spacer film, a step of removing a part of the stacked film including the first semiconductor layers and the second semiconductor layers by vertical etching, and the first step to the fourth step are performed continuously in the same plasma processing apparatus”,
Zang is silent as to the processing steps are either performed in the same or different chambers thereby not precluding that all the processing steps maybe performed in the same plasma processing chamber.
In a similar field of endeavor Zhou teaches integration of ALD steps and etch steps in a plasma chamber. By using in-situ ALD rather than ALD conducted in a separate chamber standalone ALD tool and additional cleaning tools are eliminated. Furthermore, processing time and costs are reduced by eliminating additional substrate transfers and clean time.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement processing steps continuously in the same plasma apparatus since use of separate chambers for deposition and etching increases processing time, processing steps, and costs, thus adversely affecting throughput. Moreover, the use of separate chambers requires transferring substrates from one chamber to another, which entails vacuum breaks and increases the likelihood of unwanted materials or particles coming into contact with the substrates. This may cause loss of material functionality and/or integrity on the substrate.
Regarding claim 8, Zang, as modified by Song and Ebrish, teaches the limitations of claim 1 as mentioned above. Zang does not explicitly teach
“wherein after removing a part of the stacked film including the first semiconductor layers and the second semiconductor layers by vertical etching, sidewalls of the first semiconductor layers other than the lowermost layer are subjected to isotropic etching, and thereafter, the first step to the fourth step and a step of removing the stacked film of the protective dielectric films by isotropic etching are performed continuously in the same plasma processing apparatus”.
Zang is silent as to the processing steps are either performed in the same or different chambers thereby not precluding that all the processing steps maybe performed in the same plasma processing chamber.
In a similar field of endeavor Zhou teaches integration of ALD steps and etch steps in a plasma chamber. By using in-situ ALD rather than ALD conducted in a separate chamber standalone ALD tool and additional cleaning tools are eliminated. Furthermore, processing time and costs are reduced by eliminating additional substrate transfers and clean time.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement processing steps continuously in the same plasma apparatus since use of separate chambers for deposition and etching increases processing time, processing steps, and costs, thus adversely affecting throughput. Moreover, the use of separate chambers requires transferring substrates from one chamber to another, which entails vacuum breaks and increases the likelihood of unwanted materials or particles coming into contact with the substrates. This may cause loss of material functionality and/or integrity on the substrate.
Regarding claim 11, Zang, as modified by Song and Ebrish, teaches the limitations of claim 10 as mentioned above. Zang does not explicitly teach
“wherein vertical etching of the gate sidewall spacer film in order to form the gate sidewall spacer film, a step of removing a part of the stacked film including the first semiconductor layers and the second semiconductor layers by the vertical etching, the first step to the fourth step, and a step of removing the stacked film of the protective dielectric films by the isotropic etching are performed continuously in one plasma processing apparatus”.
Zang is silent as to the processing steps are either performed in the same or different chambers thereby not precluding that all the processing steps maybe performed in the same plasma processing chamber.
In a similar field of endeavor Zhou teaches integration of ALD steps and etch steps in a plasma chamber. By using in-situ ALD rather than ALD conducted in a separate chamber standalone ALD tool and additional cleaning tools are eliminated. Furthermore, processing time and costs are reduced by eliminating additional substrate transfers and clean time.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement processing steps continuously in the same plasma apparatus since use of separate chambers for deposition and etching increases processing time, processing steps, and costs, thus adversely affecting throughput. Moreover, the use of separate chambers requires transferring substrates from one chamber to another, which entails vacuum breaks and increases the likelihood of unwanted materials or particles coming into contact with the substrates. This may cause loss of material functionality and/or integrity on the substrate.
Regarding claim 12, Zang, as modified by Song and Ebrish, teaches the limitations of claim 10 as mentioned above. Zang does not explicitly teach
“wherein vertical etching of the gate sidewall spacer film in order to form the gate sidewall spacer film, a step of removing a part of the stacked film including the first semiconductor layers and the second semiconductor layers by vertical etching, and the first step to the fourth step are performed continuously in one plasma processing apparatus”.
Zang is silent as to the processing steps are either performed in the same or different chambers thereby not precluding that all the processing steps maybe performed in the same plasma processing chamber.
In a similar field of endeavor Zhou teaches integration of ALD steps and etch steps in a plasma chamber. By using in-situ ALD rather than ALD conducted in a separate chamber standalone ALD tool and additional cleaning tools are eliminated. Furthermore, processing time and costs are reduced by eliminating additional substrate transfers and clean time.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement processing steps continuously in the same plasma apparatus since use of separate chambers for deposition and etching increases processing time, processing steps, and costs, thus adversely affecting throughput. Moreover, the use of separate chambers requires transferring substrates from one chamber to another, which entails vacuum breaks and increases the likelihood of unwanted materials or particles coming into contact with the substrates. This may cause loss of material functionality and/or integrity on the substrate.
Regarding claim 13, Zang, as modified by Song and Ebrish, teaches the limitations of claim 10 as mentioned above. Zang further teaches
wherein after removing a part of the stacked film including the first semiconductor layers and the second semiconductor layers by the vertical etching, sidewalls of the first semiconductor layers other than the lowermost first semiconductor layer are subjected to isotropic etching (see e.g., after forming the nanosheet channel layers 10 and the sacrificial layers 12, the sacrificial layers 12 are partially laterally recessed with an isotropic etching process, Column 3, Lines 26-35, Figure 3)
Zang does not explicitly teach
“thereafter, the first step to the fourth step and a step of removing the stacked film of the protective dielectric film by the isotropic etching are performed continuously in one plasma processing apparatus”.
Zang is silent as to the processing steps are either performed in the same or different chambers thereby not precluding that all the processing steps maybe performed in the same plasma processing chamber.
In a similar field of endeavor Zhou teaches integration of ALD steps and etch steps in a plasma chamber. By using in-situ ALD rather than ALD conducted in a separate chamber standalone ALD tool and additional cleaning tools are eliminated. Furthermore, processing time and costs are reduced by eliminating additional substrate transfers and clean time.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement processing steps continuously in the same plasma apparatus since use of separate chambers for deposition and etching increases processing time, processing steps, and costs, thus adversely affecting throughput. Moreover, the use of separate chambers requires transferring substrates from one chamber to another, which entails vacuum breaks and increases the likelihood of unwanted materials or particles coming into contact with the substrates. This may cause loss of material functionality and/or integrity on the substrate.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (US 10, 103,238 B1) in view of Song et al. (US 2023/0261079 A1; hereafter Song) and Ebrish et al. (US 2020/0279913 A1; hereafter Ebrish) and further in view of Lai et al. (US 2022/0122893 A1; hereafter Lai).
Regarding claim 4, Zang, as modified by Song and Ebrish, teaches the limitations of claim 1 as mentioned above. Zang further teaches
wherein among the stacked film of the protective dielectric films, a film that is in contact with the sidewall of the stacked film including the first semiconductor layers and the second semiconductor layers is formed of a film containing a silicon element and a nitrogen element (see e.g., The conformal dielectric layer 31 may be composed of a dielectric material, such as silicon nitride (Si.sub.3N.sub.4), Column 3, Lines 50-60, Figure 12),
Zang does not explicitly teach
“a film that is located on an upper layer side of the stacked film of the protective dielectric films is formed of a film containing an aluminum element and an oxygen element”.
Ebrish teaches a dielectric stack comprising an inner dielectric layer 502 including e.g., silicon nitride and an outer dielectric layer 602 including e.g., SiOC, SiON.
In a similar field of endeavor Lai teaches utilizing a protective layer 242 composed of SiON or AlO over a SiN layer 240. Lai explicitly teaches 242 functions as an etch protection layer to prevent the underlying layer 240 from being etched in subsequent operations (see e.g., Paras [0028], [0029]).
Therefore, replacing the outer dielectric layer 602 in Ebrish with AlO material taught by Lai would be a predictable modification to achieve enhanced etch protection of the inner layer 502.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to have a stacked protective dielectric film with an outer layer comprising aluminum element and oxygen element to protect the inner layer from being etched in subsequent etching processes.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893