DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 01/09/2026.
Applicant’s amendments filed 01/09/2026 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claims 1, 5-6, 9, 12, and 15.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 4,170,502 to Watakabe in view of Rahimo et al. (US 2008/0164490, hereinafter Rahimo) and Rahimo et al. (US 2013/0207157, hereinafter Rahimo’157).
With respect to claim 1, a power semiconductor device (e.g., a gate turn-off (GTO) thyristor) (Watakabe, Fig. 6, Col. 2, lines 16-43; lines 61-68; Cols. 3-4) comprising a gate turn-off thyristor, a first main side (e.g. a top side of the P-type region 36) and a second main side (e.g., a bottom side of P-type region 32) opposite to the first main side,
wherein the gate turn-off thyristor comprises in the order from the first main side to the second main side:
- a cathode electrode (58) (Watakabe, Fig. 6, Col. 4, lines 18-21) arranged on the first main side,
- a cathode region (52) (Watakabe, Fig. 6, Col. 4, lines 6-14, lines 30-32) of a first conductivity type (N-type),
- a base layer (36) (Watakabe, Fig. 6, Col. 3, lines 15-17) of a second conductivity type (P-type) different than the first conductivity type (N-type) forming a first junction to the cathode region (52),
- a drift layer (30) (Watakabe, Fig. 6, Col. 2, lines 60-66) of the first conductivity type (N-type) forming a second junction with the base layer (36),
- an anode layer (32) (Watakabe, Fig. 6, Col. 3, lines 3-7) of the second conductivity type (P-type), and
- an anode electrode (54) (Watakabe, Fig. 6, Col. 4, lines 18-21) arranged on the second main side (e.g., the bottom side of P-type region 32),
wherein the gate turn-off thyristor further comprises a gate electrode (56) (Watakabe, Fig. 6, Col. 4, lines 18-21) which is arranged lateral to the cathode region (52),
wherein the base layer (36) comprises:
- a cathode base region (46) (Watakabe, Fig. 6, Col. 4, lines 33-38; lines 45-50) located between the cathode region (52) and the drift layer (30) and having a first depth (e.g., 20 mm to 50 mm),
- a gate base region (48) (Watakabe, Fig. 6, Col. 4, lines 33-38; lines 45-50) located between the gate electrode (56) and the drift layer (30) and having a second depth (e.g., 45 mm to 80 mm), and
- an intermediate base region (e.g., P-type region under oxide regions 44 having smaller thickness) (Watakabe, Fig. 6, Col. 3, lines 42-68) located between the cathode base region (46) and the gate base region (48) and having at least two different values of a third depth (e.g., two values of depths between a first depth and a second depth), wherein the at least two values of the third depth are both larger than the first depth and smaller than the second depth,
wherein a maximum doping concentration of the gate base region (e.g., P+ type region 48) (Watakabe, Fig. 6, Col. 4, lines 33-38, lines 43-50) is higher than a maximum doping concentration of the the cathode base region (e.g., P type region 46).
Further, Watakabe does not specifically disclose (1) a gate-commutated thyristor cell, (2) a maximum doping concentration of the gate base region is higher than a maximum doping concentration of the intermediate base region and wherein the maximum doping concentration of the intermediate base region is higher than a maximum doping concentration of the cathode base region.
Regarding (1), Rahimo teaches forming a four-layer power semiconductor device (Rahhimo, Figs. 2-3, ¶0026-¶0042, ¶0051-¶0067) configured as a gate turn-off thyristor (GTO) or a gate-commutated thyristor (GCT) comprising modulated main blocking junction provided by the doping density profile the base region that influences the field distribution at high turn-off current, to provide faster turn-off, and to turn-off considerably more current at high voltage.
Further, Rahimo’157 teaches forming integrated GCT comprising a plurality GCT cells Rahhimo’157, Figs. 4-6, ¶0025, ¶0029-¶0033, ¶0035-¶0041) with improved performance in view of thermal and electrical characteristics and reduced size.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the power semiconductor device of Watakabe by forming four-layer power semiconductor device configured as gate-commutated thyristor (GCT) as taught by Rahimo, wherein the GCT thyristor includes a plurality GCT cells as taught by Rahimo’157 to have the power semiconductor device comprising a gate-commutated thyristor cell, in order to provide a semiconductor device with faster turn-off, and to turn-off considerably more current at high voltage; and with improved performance in view of thermal and electrical characteristics and reduced size (Rahimo, ¶0026, ¶0037-¶0038, ¶0041-¶0042; Rahhimo’157, ¶0025, ¶0029, ¶0033).
Regarding (2), Watakabe teaches that a maximum doping concentration of the gate base region (e.g., P+ type region 48) is higher because during formation of the oxide layer (44) (Watakabe, Fig. 6, Col. 3, lines 42-68), no out diffusion of the P-type dopant is occurred in the gate base region (48) by using layer (40) impervious to diffusion of P-type dopant, and P- type dopant out diffuse from the P+ -type region (36) in a cathode base region (46) under the thick oxide layer (44). Further, a person of ordinary skill in the art would recognize that due to smaller thickness of the oxide layer (44) in the intermediate region, less P- type dopant would out diffuse from the P+ -type region (36) in the intermediate region than that in the cathode base region (46) under thicker oxide layer (44). Thus, the intermediate base region has a maximum doping concentration smaller than that of the gate base region (48) and greater than that of the P-type cathode region (46) (Watakabe, Fig. 6, Col. 3, lines 42-68).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the power semiconductor device of Watakabe by forming the base layer including P-type doping regions having different dopant concentrations as taught by Watakabe to have the power semiconductor device, wherein a maximum doping concentration of the gate base region is higher than a maximum doping concentration of the intermediate base region and wherein the maximum doping concentration of the intermediate base region is higher than a maximum doping concentration of the cathode base region, in order to provide a thyristor with lower on-state voltage and improved turn-off (Watakabe, Col. 4, lines 43-50).
Regarding claim 2, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 1. Further, Watakabe discloses the power semiconductor device, wherein the intermediate base region (e.g., P-type region under oxide regions 44 having smaller thickness) (Watakabe, Fig. 6, Col. 3, lines 42-68; Col. 4, lines 6-21) includes a region between a gap (e.g., filled with oxide layer 44) between the gate electrode (56) and the cathode region (52) on one side and the second junction (e.g., between the drift layer 30 and the bottom of the base layer 36) on the other side.
Regarding claim 3, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 2. Further, Watakabe discloses the power semiconductor device, wherein the intermediate base region (e.g., P-type region under oxide regions 44 having smaller thickness) (Watakabe, Fig. 6, Col. 3, lines 42-68; Col. 4, lines 6-21) additionally includes at least one of (e.g., an adjacent region under the oxide layer 44 having smaller thickness and between the gate electrode 56 and the second junction between the P-type layer 36 and the N-type drift layer 30) - an adjacent region between the gate electrode (56) and the second junction (e.g., between the drift layer 30 and the bottom of the base layer 36) and - an adjacent region between the cathode region and the second junction.
Regarding claim 4, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 1. Further, Watakabe discloses the power semiconductor device, wherein a maximum doping concentration of the gate base region (e.g., P+ type region 48) (Watakabe, Fig. 6, Col. 3, lines 42-68; Col. 4, lines 33-38) in an area closest to the first main side (e.g., a top surface of the P-type base layer 36) is higher than a maximum doping concentration of the cathode base region (e.g., P-type region 46) closest to the first main side.
Regarding claim 5, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 1. Further, Watakabe discloses the power semiconductor device, wherein the first depth (e.g., 20 mm to 50 mm) is ta minimum depth of the cathode base region (46) (Watakabe, Fig. 6, Col. 4, lines 33-38), wherein the second depth (e.g., 45 mm to 80 mm) is a maximum depth of the gate base region (48), wherein the at least two values of the third depth (e.g., two values of depths between a first depth and a second depth) are larger than the first depth and less than the second depth.
Regarding claim 6, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 1. Further, Watakabe discloses the power semiconductor device, wherein the first depth (e.g., 20 mm to 50 mm) is a minimum distance of the cathode base region (46) (Watakabe, Fig. 6, Col. 4, lines 33-38) to the drift layer (30), wherein the second depth (e.g., 45 mm to 80 mm) is a maximum distance of the gate electrode (56) to the drift layer (30), wherein the at least two values of the third depth (e.g., two values of depths between a first depth and a second depth) are larger than the first depth and less than the second depth.
Regarding claim 7, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 1. Further, Watakabe discloses the power semiconductor device, wherein the first depth has a value (e.g., 20 mm to 50 mm) (Watakabe, Fig. 6, Col. 4, lines 33-38) in a rnage between 5 mm and 100 mm (e.g., a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03)).
Regarding claim 8, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 1. Further, Watakabe discloses the power semiconductor device, wherein a part of the second junction (e.g., between the drift layer 30 and the bottom of the base layer 36) (Watakabe, Fig. 6, Col. 4, lines 33-38) which is located between the cathode base region (46) and the drift layer (30) is at least partially located in a first plane (e.g., a plane corresponding to a bottom surface of 46) and wherein a part of the second junction which is located between the gate base region (48) and the drift layer (30) is at least partially located in a second plane (e.g., a plane corresponding to a bottom surface of 48), and wherein the part of the second junction which is located between the intermediate base region (e.g., P-type region under oxide regions 44 having smaller thickness) (Watakabe, Fig. 6, Col. 3, lines 42-68; Col. 4, lines 6-21) and the drift layer (30) is located between the first and the second plane.
Regarding claim 12, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 1. Further, Watakabe does not specifically discloses that at the first main side the cathode region has a form out of a group consisting of a circle, a rectangle, an octagon and a hexagon.
However, Rahimo’157 teaches forming a semiconductor device comprising a plurality of GCT cells including cathode layers (4) arranged as stripes radially to a center of a circle (Rahimo’157, Figs. 5-6, ¶0055).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the power semiconductor device of Watakabe/Rahimo/ Rahimo’157 by forming a plurality of GCT cells including cathode layers arranged as stripes as taught by Rahimo’157 to have the power semiconductor device, wherein at the first main side the cathode region has a form out of a group consisting of a rectangle, in order to provide a semiconductor device with improved performance in view of thermal and electrical characteristics and reduced size (Rahhimo’157, ¶0025, ¶0029, ¶0033, ¶0055).
Regarding claim 15, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 1. Further, Watakabe does not specifically discloses that the gate-commutated thyristor cell is implemented as a component out of a group consisting of an asymmetric integrated gate-commutated thyristor cell, a reverse conducting integrated gate-commutated thyristor cell, a reverse blocking integrated gate-commutated thyristor cell and a bidirectional turn-off thyristor cell.
However, Rahimo’157 teaches forming a reverse conducting power semiconductor device (RC-IGCT) comprising a plurality of integrated IGCT cells including cathode layers (4) arranged as stripes radially to a center of a circle (Rahimo’157, Figs. 3-6, ¶0002, ¶0011, ¶0017, ¶0025-¶0026, ¶0032-¶0033, ¶0051-¶0055).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the power semiconductor device of Watakabe/Rahimo/ Rahimo’157 by forming a reverse conducting power semiconductor device including a plurality of integrated GCT cells as taught by Rahimo’157 to have the power semiconductor device, wherein the gate-commutated thyristor cell is implemented as a component out of a group consisting of a reverse conducting integrated gate-commutated thyristor cell, in order to provide a semiconductor device with improved performance in view of thermal and electrical characteristics and reduced size (Rahhimo’157, ¶0002, ¶0011, ¶0017, ¶0025-¶0026, ¶0032-¶0033, ¶0051-¶0055).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 4,170,502 to Watakabe in view of Rahimo (US 2008/0164490) and Rahimo’157 (US 2013/0207157) as applied to claim 1, and further in view of Nishizawa et al. (US Patent No. 4,984,049, hereinafter Nishizawa).
Regarding claim 9, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 1. Further, Watakabe discloses that the part of the second junction which is located between the intermediate base region (e.g., P-type region under oxide regions 44 having smaller thickness) (Watakabe, Fig. 6, Col. 3, lines 42-68; Col. 4, lines 6-21) and the drift layer (30) includes: - a first base transition region forming a step, but does not specifically disclose - a second base transition region forming a further step and - a plane between the first transition region and the second base transition region.
However, Nishizawa teaches forming a P+ type gate region (24) (Nishizawa, Fig. 22, Col. 1, lines 26-33; Col. 9, lines 38-66) under the gate electrode (28) and including a portion under the oxide (30) between the gate electrode (28) and the cathode region (26), wherein the portion of the P+ type gate region (24) under the oxide (30) has a first step and a second step and a horizontal plane between the first step and the second step, to provide a very small gate resistance to obtain improved thyristor having low on voltage and having large gate turn-off current.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the power semiconductor device of Watakabe/Rahimo/ Rahimo’157 by forming a P+ type gate region in the intermediate region under the oxide between the gate electrode and the cathode region as taught by Nishizawa, wherein the P+ type gate region in the intermediate region has a first step connected to a second step with a horizontal plane to have the power semiconductor device that includes: - a second base transition region forming a further step and - a plane between the first transition region and the second base transition region, in order to provide to provide a very small gate resistance to obtain improved thyristor having low on voltage and having large gate turn-off current (Col. 1, lines 26-33; Col. 9, lines 38-40).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 4,170,502 to Watakabe in view of Rahimo (US 2008/0164490) and Rahimo’157 (US 2013/0207157) as applied to claim 1, and further in view of Arnold et al. (US 2018/0204913, hereinafter Arnold).
Regarding claim 10, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 1. Further, Watakabe does not specifically discloses that a width of the cathode region is in a range between 50 mm and 250 mm.
However, Arnold teaches forming a turn-off power semiconductor device (Arnold, Figs. 5-7, 8, ¶0012, ¶0037-¶0043, ¶0060-¶0061) comprising a plurality of thyristor cells with increased density of separate cathode regions (54a/54b), wherein a cathode region (54a/54b) has a width between 100 mm and 300 mm (Arnold, Figs. 5-7, 8, ¶0043, ¶0060) that overlaps a range between 50 mm and 250 mm.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the power semiconductor device of Watakabe/Rahimo/ Rahimo’157 by forming a turn-off power semiconductor device comprising a plurality of GCT cells including a cathode region having a specific width as taught by Arnold to have the power semiconductor device, wherein a width of the cathode region is in a range between 50 mm and 250 mm, in order to provide improved turn-off power semiconductor device with increased density of separate cathode regions while ensuring a good performance of the turn-off power semiconductor device (Arnold, ¶0001, ¶0012, ¶0017, ¶0043, ¶0060).
Regarding claim 11, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 1. Further, Watakabe does not specifically discloses that a difference between a width of the cathode region and a width of the gate electrode is in a range of 10 mm to 70 mm.
However, Arnold teaches forming a turn-off power semiconductor device (Arnold, Figs. 5-7, 8, ¶0012, ¶0037-¶0043, ¶0060-¶0061) comprising a plurality of thyristor cells, wherein a cathode region (54a/54b) is separated from the gate well region (522) with a distance d more than 2 mm (Arnold, Figs. 5-7, 8, ¶0056).
Thus, a person of ordinary skill in the art would recognize that with a distance between the neighboring cathode regions (54a/54b) of about a width of the cathode region (54a/54b) between 100 mm and 300 mm (Arnold, Figs. 5-7, 8, ¶0043, ¶0056, ¶0060), and with a distance d between the cathode region (54a/54b) and the gate well region (522) of about 2 mm or more, a difference between a width of the cathode region and a width of the gate electrode would be more than 4 mm.
Further, Arnold teaches a turn-off power semiconductor device with reduced lateral dimensions to increase density of separate cathode regions, to increase an electrical and thermal contact area while ensuring a good performance of the turn-off power semiconductor device (Arnold, ¶0012-¶0014).
Thus, Arnold recognizes that reducing lateral dimensions of the GCT cells including a distance between the cathode region and the gate electrode impacts density of separate cathode regions, contact area and operation of the turn-off device. Thus, lateral dimensions of the GCT cells including a distance between the cathode region and the gate electrode is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, lateral dimensions of the GCT cells including a distance between the cathode region and the gate electrode as Arnold has identified lateral dimensions of the GCT cells including a distance between the cathode region and the gate electrode as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific distance between the cathode region and the gate electrode such that a difference between a width of the cathode region and a width of the gate electrode is in a range of 10 mm to 70 mm, in order to provide improved turn-off power semiconductor device with reduced lateral dimensions to increase density of separate cathode regions, to increase an electrical and thermal contact area while ensuring a good performance of the turn-off power semiconductor device as taught by Arnold (¶0012-¶0014, ¶0043, ¶0056, ¶0060) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the power semiconductor device of Watakabe/Rahimo/ Rahimo’157 by optimizing lateral dimensions of the GCT cells including a distance between the cathode region and the gate electrode as taught by Arnold to have the power semiconductor device, wherein a difference between a width of the cathode region and a width of the gate electrode is in a range of 10 mm to 70 mm, in order to provide improved turn-off power semiconductor device with reduced lateral dimensions to increase density of separate cathode regions, to increase an electrical and thermal contact area while ensuring a good performance of the turn-off power semiconductor device (Arnold, ¶0012-¶0014, ¶0043, ¶0056, ¶0060).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 4,170,502 to Watakabe in view of Rahimo (US 2008/0164490) and Rahimo’157 (US 2013/0207157) as applied to claim 1, and further in view of Swanson (US Patent No. 5,369,291).
Regarding claim 13, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 1. Further, Watakabe does not specifically discloses that the anode layer includes a gate anode region and a cathode anode region, wherein a maximum doping concentration of the gate anode region is less than a maximum doping concentration of the cathode anode region.
However, Swanson teaches forming a PNPN thyristor (Swanson, Fig. 1, Col. 2, lines 22-26; lines 30-59; Col. 3, lines 4-45) comprising an anode layer (10/12) including a gate anode region (10) under the gate electrode (32) and a cathode anode region (12) under the cathode region (24) and the cathode electrode (26), wherein a maximum doping concentration of the gate anode region (10) is less than a maximum doping concentration of the cathode anode region (12), the more heavily doped region (12) reduce contact resistance, and more lightly doped region controls injected charge, to provide an improved switching device having improved switching speed and high voltage in the off-state.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the power semiconductor device of Watakabe/Rahimo/ Rahimo’157 by forming an anode layer including more heavily doped region and more lightly doped region as taught by Swanson to have the power semiconductor device, wherein the anode layer includes a gate anode region and a cathode anode region, wherein a maximum doping concentration of the gate anode region is less than a maximum doping concentration of the cathode anode region, in order to reduce contact resistance and control injected charge, and to provide an improved switching device having improved switching speed and high voltage in the off-state (Swanson, Col. 2, lines 22-26; lines 30-59; Col. 3, lines 4-45).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 4,170,502 to Watakabe in view of Rahimo (US 2008/0164490) and Rahimo’157 (US 2013/0207157) as applied to claim 1, and further in view of Kitagawa et al. (US Patent No. 5,223,442, hereinafter Kitagawa).
Regarding claim 13, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 1. Further, Watakabe does not specifically discloses that the anode layer includes a gate anode region and a cathode anode region, wherein a maximum doping concentration of the gate anode region is less than a maximum doping concentration of the cathode anode region.
However, Kitagawa teaches forming a semiconductor device including gate-turn-off thyristor (Kitagawa, Figs. 8A-8C, Col. 1, lines 11-13; Col. 3, lines 16-18; Col. 8, lines 35-54) comprising an anode electrode (40) and an anode layer (35/36) including a gate anode region (36) under the gate electrode (39) and a cathode anode region (35) under the cathode electrode (38) and the cathode region (33), wherein a maximum doping concentration (e.g., low concentration P-type layer 36) of the gate anode region (36) is less than a maximum doping concentration of the cathode anode region (e.g., high concentration P+ -type layer 35), to provide a high withstand voltage semiconductor device of a high reliability.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the power semiconductor device of Watakabe/Rahimo/ Rahimo’157 by forming an anode layer including more heavily doped region and more lightly doped region as taught by Kitagawa to have the power semiconductor device, wherein the anode layer includes a gate anode region and a cathode anode region, wherein a maximum doping concentration of the gate anode region is less than a maximum doping concentration of the cathode anode region, in order to provide a high withstand voltage semiconductor device of a high reliability (Kitagawa, Col. 1, lines 11-13; Col. 3, lines 16-18; Col. 8, lines 35-54).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 4,170,502 to Watakabe in view of Rahimo (US 2008/0164490) and Rahimo’157 (US 2013/0207157) as applied to claim 1, and further in view of Lee (US 2009/0206364).
Regarding claim 14, Watakabe in view of Rahimo and Rahimo’157 discloses the power semiconductor device of claim 1. Further, Watakabe does not specifically discloses that the gate-commutated thyristor cell comprises a buffer layer of the first conductivity type, wherein the buffer layer is located between the drift layer and the anode layer and includes a gate buffer region and a cathode buffer region, wherein a maximum doping concentration of the gate buffer region is higher than a maximum doping concentration of the cathode buffer region.
However, Rahimo teaches forming a gate-commutated thyristor (GCT) (Rahhimo, Figs. 2-3, ¶0026-¶0042, ¶0051-¶0067) comprising modulated main blocking junction provided by the doping density profile the base region and a buffer layer (10) (Rahhimo, Figs. 2-3, ¶0060) of the first conductivity type (N-type), wherein the buffer layer (10) is located between the drift layer (N- type ayer 9) (Rahhimo, Figs. 2-3, ¶0059) and the anode layer (7) and includes a gate buffer region (e.g., under the gate base region 82/82’) (Rahhimo, Figs. 2-3, ¶0051-¶0055) and a cathode buffer region (e.g., under the cathode base region 81), to control field distribution at high turn-off current, to provide faster turn-off, and to turn-off considerably more current at high voltage (Rahimo, ¶0026, ¶0037-¶0038, ¶0041-¶0042).
Further, Lee teaches forming a semiconductor device (Lee, Fig. 1, ¶0003-¶0005, ¶0008-¶0012) comprising a buffer layer (130) having different concentrations according to areas to control hole current injection through the buffer layer (130), wherein a maximum doping concentration of the gate buffer region (e.g., N+ region 134 under the gate electrode 154) is higher than a maximum doping concentration of the emitter buffer region (e.g., N- region 132 under the emitter electrode 154), to reduce turn-off time and to prevent breakdown phenomena (Lee, ¶0009, ¶0012).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the power semiconductor device of Watakabe/Rahimo/ Rahimo’157 by forming a buffer layer between the drift layer and the anode layer as taught by Rahimo, wherein the buffer layer have different concentrations according to areas as taught by Lee to have the power semiconductor device, wherein the gate-commutated thyristor cell comprises a buffer layer of the first conductivity type, wherein the buffer layer is located between the drift layer and the anode layer and includes a gate buffer region and a cathode buffer region, wherein a maximum doping concentration of the gate buffer region is higher than a maximum doping concentration of the cathode buffer region, in order to control field distribution at high turn-off current, to provide faster turn-off, and to turn-off considerably more current at high voltage; and to control hole current injection through the buffer layer to reduce turn-off time and to prevent breakdown phenomena (Rahimo, ¶0026, ¶0037-¶0038, ¶0041-¶0042; Lee, ¶0009, ¶0012).
Response to Arguments
Applicant's arguments filed 01/09/2026 have been fully considered but they are not persuasive.
In response to Applicant's argument that “[T]he Examiner initially identifies the "second main side" as "a bottom side of P-type region 32" but later identifies the same "second main side" as "the top side of the P-type region 36”, the examiner submits that the "second main side" of Watakabe (Fig. 6) is "a bottom side of P-type region 32". The anode electrode 54 of Watakabe is formed on the "second main side" which is “a bottom side of P-type region 32”. The description of the second main side (page 4 of the Office Action) as the top side of the P-type region 36 is unintentional misplacement of the first man side. Although, a person of ordinary skill in the art would recognize from Fig. 6 of Watakabe that the "second main side" is a bottom side of the structure that is "a bottom side of P-type region 32". Thus, the arrangement of the anode electrode 54 of Watakabe on the second main side is clear from Fig. 6 of Watakabe.
In response to Applicant's argument that “[t]he Examiner maps the claimed "cathode electrode arranged on the first main side" to Watakabe's element 58. However, upon review of Watakabe, element 58 is not arranged on the first main side as claimed. Moreover, element 58 does not appear in the recited order "from the first main side to the second main side" as required by claim 1. Specifically, the claimed structure recites that the cathode electrode is the first element in the ordered sequence from the first main side to the second main side, followed by the cathode region, base layer, drift layer, anode layer, and anode electrode. The Examiner's mapping of element 58 to the cathode electrode does not preserve this structural ordering”, the examine submits that “element 58” (the cathode electrode of Watakabe) is arranged on the first main side as claimed. In the instant application, Figs. 1-2, 3A-3B of the original specification show that the cathode electrode (2) is arranged on the first main side (21). Thus, according to the specification, the first main side (21) includes a top surface of the cathode region (9). In Watakabe, the arrangements of the cathode electrode, the cathode region, base layer, drift layer, anode layer, and anode electrode are in the same ordered sequence as that of the instant application.
Thus, the above applicant’s arguments are not persuasive, and the rejection of claim 1 under 35 USC 103 over Watakabe in view of Rahimo/Rahimo’157 is maintained.
Regarding dependent claims 2-15 which depend on the independent claim 1, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/ Primary Examiner, Art Unit 2891