Prosecution Insights
Last updated: October 02, 2026
Application No. 18/280,600

MANUFACTURING SYSTEM AND METHOD OF SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Sep 06, 2023
Priority
Sep 26, 2022 — nonprovisional of PCTJP2022035648
Examiner
WOLDEGEORGIS, ERMIAS T
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hitachi Ltd.
OA Round
3 (Non-Final)
71%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
542 granted / 764 resolved
+2.9% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
45 currently pending
Career history
805
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
70.9%
+30.9% vs TC avg
§102
24.3%
-15.7% vs TC avg
§112
3.9%
-36.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 764 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/1/2026 has been entered. Response to Amendment Claims 1, 3-4, 6-8, 10-11, and 13-14 have been amended; claims 15 and 16 have been newly added; and claims 1-16 are currently pending. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Endo et al. (US 2020/0411339 A1, hereinafter “Endo”) in view of Kasai (US 2022/0221509 A1, hereinafter “Kasai”). In regards to claim 1, Endo discloses (See, for example, Fig. 1) a semiconductor device manufacturing system for processing a wafer, comprising: a semiconductor device manufacturing apparatus including a wafer stage having an upper surface configured to allow the wafer to be placed (“electrostatic chuck 6 for attracting and holding the semiconductor wafer W…”, See Par [0030]), a plurality of heaters disposed inside the wafer stage and below a plurality of regions of the upper surface (“…the heater 6c generate heat by the power supplied by the controller 200… the regions are referred to as “divided regions.” One heater 6c is disposed in each divided region.”, See, for example, Par [0031]), and a controller configured to adjust outputs of a plurality of heater power supplies supplied to the plurality of heaters (“…the control unit 25 adjusts, for each of the divided regions 60, the power supplied to the heater 6c..”, See, for example, Par [0091] and Figs. 1 and 3); and a wafer temperature calculation system configured to determine whether first output values of the plurality of the heater power supplies calculated in advance to implement a target temperature of the wafer during the processing are within an allowable a range that can be implemented to be physically output by the plurality of the heater power supplies (“The power supply unit 20 is provided for each of the heaters 6c disposed in the divided regions 60 of the electrostatic chuck 6 to supply power to a corresponding heater 6c…The measuring unit 24 measures respective resistance values of the heaters 6c based on the measured voltages and measured currents outputted from the power supply units 20 and supplied to the heater 6c…”, See, for example, Par [0052]), and calculate second output values obtained by correcting all of the first output values to values within the allowable range that can be implemented when the first output values are out of the allowable range that can be implemented (“..the holding unit 26 hold a conversion table 260 and a correction table 265.”, See Par [0053]; and “in the correction table 265, individual tables 267 are stored for the respective frequencies 266 of the power source. In each individual table 267, individual tables 269 are stored for the respective region IDs 268 that identify the divided regions 60 where the heaters 6c are provided. In each individual table 269, a temperature correction value is stored in association with a magnitude of the source voltage V.sub.S. In the present embodiment, the magnitude of the source voltage V.sub.S stored in the individual table 269 is the square of an effective value (RMS value) of the source voltage V.sub.S. The correction table 265 is an example of correction data.”, See for example, Par [0054]; See also Pars [0057]-[0067]). It is further noted that, as amended, no longer recites that the first output values are calculated “in advance”. The claim therefore places no temporal constraint on when the first output values are calculated, and reads on output values calculated during the processing iof the wafer, as in Endo’s control lop of Pars{0091]-[0093] and Kasai’s feedback control described below. Endo is silent about a wafer temperature calculation system configured to determine whether first output values of the plurality of the heater power supplies which are calculated based on a heat transfer between a first region and at least a second region of the plurality of regions of the upper surface of the wafer stage in advance to implement a target temperature of the wafer during the processing based on a heat transfer between a first region and at least a second region of the plurality of regions of the upper surface of the wafer stage in advance are within an allowable range that can be implemented to be physically output by the plurality of the heater power supplies. Kasai while disclosing temperature control of a mounting base teaches (See, for example, Figs. 3-4) multi-zone temperature control of a wafer-supporting stage having a surface divided into a plurality of regions each provided with an individually controllable heater (See top plate 110 divided into first region Z1 and outer regions Z2-Z4, with heaters 1211-1214, See, Pars [0038]). It teaches calculating the heater output value of one region based on a heat transfer between the region and at least a second, adjacent region of the surface. In particular, it performs feedback control that adjust the operation amount of the heater in an outer side region outside the centermost region so that a temperature difference between the outer side region and the region that is adjacent to the outer side region inward in the direction of the diameter becomes a preset value. It expressly frames this output calculation in terms of the heat transfer between the regions of the surface, explaining that the outer-region heater output is determined so as to manage the inter-region heat flux (See, Par [0074]). Accordingly, it is possible to control the second to fourth regions Z2 to Z4 so that a flux of heat flowing into the first region Z1 becomes zero (See, Par [0066]), thereby minimizing thermal interference between the central first region Z1 and the second to fourth regions Z2 to Z4. Thus, the operation amount (output) supplied to a heater of a first region of the surface is calculated based on a heat transfer between that first region and at least a second region, as recited (See, for example, Pars [0051], [0052]). Moreover, Kasai’s control target is itself set based on the inter-region heat transfer. The preset value (offset amount) stored in the storage unit 13a an used as the control target for each outer region Z2-Z4 is selected so as to null the heat flux into the centermost region Z1(See, Pars [0055], [0066], [0074]). It further teaches that the heater power supplies of the respective regions have a defined maximum output that can be physically supplied (i.e., a range that can be implemented to be physically output by the heater power supplies), disclosing in a worked example that a maximum output of the heater of the first region was 1000 W, and the maximum output of the heaters of the second to fourth regions was 1000 W (See, Par [0089]). Applicant’s own disclosure confirms that the existence of such upper and lower physical output limits, unique to the apparatus, is a known characteristic of the heater power supplies and a routine consideration in setting heater output (See pars [0044] and [0055]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Endo’s wafer temperature calculation system, which independently calculates each region’s heater output, to instead calculate the heater output values based on a heat transfer between a first region and at least a second region of the surface because having per-region feedback control help suppress thermal interference (overshoot/undershoot), improve in-plane temperature uniformity, and keeps each region’s deviation within the desired region. In regards to claim 8, Endo discloses (See, for example, Figs. 1 and 3) a semiconductor device manufacturing method of processing a wafer by using a semiconductor device manufacturing apparatus (See, for example, Pars [0023], [0024] and [0027]) including a wafer stage having an upper surface on which the wafer is placed (“electrostatic chuck 6 for attracting and holding the semiconductor wafer W…”, See Par [0030]), a plurality of heaters disposed inside the wafer stage and below a plurality of regions of the upper surface (“…the heater 6c generate heat by the power supplied by the controller 200… the regions are referred to as “divided regions.” One heater 6c is disposed in each divided region.”, See, for example, Par [0031]), and a controller configured to adjust outputs of a plurality of heater power supplies supplied to the plurality of heaters (“…the control unit 25 adjusts, for each of the divided regions 60, the power supplied to the heater 6c..”, See, for example, Par [0091] and Figs. 1 and 3), the semiconductor device manufacturing method comprising: determining whether first output values of the plurality of the heater power supplies calculated in advance to implement a target temperature of the wafer during the processing are within an allowable a range that can be implemented to be physically output by the plurality the heater power supplies (See, for example Par [0052]); and adjusting, when the first output values are out of the allowable range that can be implemented (See, for example, Par [0057]), the heater power supply by the controller to have second output values calculated by correcting all the first output values to values within the allowable range that can be implemented (See, for example, Pars [0057]-[0067]). Endo is silent about a wafer temperature calculation system configured to determine whether first output values of the plurality of the heater power supplies which are calculated based on a heat transfer between a first region and at least a second region of the plurality of regions of the upper surface of the wafer stage in advance to implement a target temperature of the wafer during the processing based on a heat transfer between a first region and at least a second region of the plurality of regions of the upper surface of the wafer stage in advance are within an allowable a range that can be implemented to be physically output by the plurality of the heater power supplies. Kasai while disclosing temperature control of a mounting base teaches (See, for example, Figs. 3-4) multi-zone temperature control of a wafer-supporting stage having a surface divided into a plurality of regions each provided with an individually controllable heater (See top plate 110 divided into first region Z1 and outer regions Z2-Z4, with heaters 1211-1214, See, Pars [0038]). It teaches calculating the heater output value of one region based on a heat transfer between the region and at least a second, adjacent region of the surface. In particular, Kasai performs feedback control that adjust the operation amount of the heater in an outer side region outside the centermost region so that a temperature difference between the outer side region and the region that is adjacent to the outer side region inward in the direction of the diameter becomes a preset value. It expressly frames this output calculation in terms of the heat transfer between the regions of the surface, explaining that the outer-region heater output is determined so as to manage the inter-region heat flux (See, Par [0074]). Accordingly, it is possible to control the second to fourth regions Z2 to Z4 so that a flux of heat flowing into the first region Z1 becomes zero (See, Par [0066]), thereby minimizing thermal interference between the central first region Z1 and the second to fourth regions Z2 to Z4. Thus, the operation amount (output) supplied to a heater of a first region of the surface is calculated based on a heat transfer between that first region and at least a second region, as recited (See, for example, Pars [0051], [0052]). Moreover, Kasai’s control target is itself set based on the inter-region heat transfer. The preset value (offset amount) stored in the storage unit 13a an used as the control target for each outer region Z2-Z4 is selected so as to null the heat flux into the centermost region Z1(See, Pars [0055], [0066], [0074]). It further teaches that the heater power supplies of the respective regions have a defined maximum output that can be physically supplied (i.e., a range that can be implemented to be physically output by the heater power supplies), disclosing in a worked example that a maximum output of the heater of the first region was 1000 W, and the maximum output of the heaters of the second to fourth regions was 1000 W (See, Par [0089]). Applicant’s own disclosure confirms that the existence of such upper and lower physical output limits, unique to the apparatus, is a known characteristic of the heater power supplies and a routine consideration in setting heater output (See pars [0044] and [0055]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Endo’s wafer temperature calculation system, which independently calculates each region’s heater output, to instead calculate the heater output values based on a heat transfer between a first region and at least a second region of the surface because having per-region feedback control help suppress thermal interference (overshoot/ undershoot), improve in-plane temperature uniformity, and keeps each region’s deviation within the desired region. In regards to claims 2 and 9, Endo discloses (See, for example, Figs. 1 and 3) the wafer is processed in the semiconductor device manufacturing apparatus by using a processing recipe calculated by setting a first temperature distribution of the wafer corresponding to the first output values or a second temperature distribution calculated based on the second output values as a target temperature distribution during the processing (See, for example, Pars [0055]-[0057]). In regards to claims 3 and 10, Endo discloses (See, for example, Figs. 1 and 3) when it is determined that output values of at least one or more heater power supplies among the plurality of the heater power supplies are out of the range that can be implemented, the controller adjusts the outputs of the plurality of heater power supplies by setting, as a target temperature distribution, a second target temperature distribution calculated based on the second output values at which the output values of the at least one or more heater power supplies are within the range that can be implemented (“…the control unit 25 adjusts the power supplied to heater 6c in each of the divided regions 60 such that the temperatures of the heater 6c becomes a predetermined target temperature …”, See, for example, Par [0098]) . In regards to claims 4 and 11, Endo discloses (See, for example, Figs. 1-4) when it is determined that output values of at least one or more heater power supplies among the plurality of the heater power supplies are out of the range that can be implemented, the wafer temperature calculation system calculates the second target temperature distribution such that the output values of the at least one or more heater power supplies are within the range that can be implemented and a value of a predetermined objective function can be minimized (See, for example, Pars [0098]-[0099]). In regards to claims 5 and 12, Endo discloses (See, for example, Figs. 1-4) that the wafer temperature calculation system calculates the second target temperature distribution by sequentially increasing or decreasing the output of each of the plurality of heater power supplies until the value of the objective function is minimum (“…the control unit 25 corrects, for each of the divided regions 60, the temperature of the heater 6c estimated…”, See, for example Pars [0078], [0080], and [0081]). In regards to claim 6, Endo discloses (See, for example, Figs. 1, 3 and 15) that the wafer temperature calculation system and the semiconductor device manufacturing apparatus are communicably connected (“The temperature of the coolant flowing through the flow path 2b, the power supplied to each of the heaters 6c in the electrostatic chuck 6, and the pressure of the heat transfer gas supplied to the backside of the semiconductor wafer W are controlled by the controller 200. Accordingly, the temperature of the semiconductor wafer W attracted to and held on the upper surface of the electrostatic chuck 6 is controlled to a temperature within a predetermined range.”, See for example, Par [0034]), and a first correlation between output values of the plurality of heater power supplies and a temperature distribution of the wafer (See, for example, Pars [0098] and [0099], and also Par [0045]), an upper limit value and a lower limit value of the range that can be implemented of the output of the heater power supply, and an upper limit value and a lower limit value of a temperature of the wafer in a range calculated based on the first correlation (it discloses that the temperature of the semiconductor wafer W held on the electrostatic chuck 6 is controlled to a temperature within a predetermined range, See Par [0034], which is a bounded range of the wafer temperature) are associated with the semiconductor device manufacturing apparatus and stored in the wafer temperature calculation system (“…the control unit 25 controls the power supplied to the heater 6c based on the difference between the estimated temperature and the target temperature… Step S302 is an example of an adjustment step.”, See par [0098]; “…the control unit 25 holds, for each of the divided regions 60, the calculated correction value ..”,See Par [0099]; and also See, for example, Pars [100]- [0106]). In regards to claim 7, Endo discloses (See, for example, Figs. 1, 3 and 15) that when it is determined that output values of at least one or more heater power supplies among the plurality of the heater power supplies are out of the range that can be implemented, the wafer temperature calculation system stores a region of the heater corresponding to the at least one or more heater power supplies (“The power supply unit 20 is provided for each of the heaters 6c disposed in the divided regions 60 of the electrostatic chuck 6 to supply a power to a corresponding heater 6c. … the substrate processing apparatus 100 has forty heaters 6c, and forty power supply units 20 are provided for each of the forty heaters 6c, respectively. Each of the power supply units 20 includes a switch SW 21, an ammeter 22, and a voltmeter 23. Although it is not shown in FIG. 3, one power supply unit 20 is provided for each of one or more heaters 5b disposed in the support 5a. …The SW 21 is turned on or off under the control of the control unit 25 and the power from a power source 27 is supplied to a corresponding heater 6c through the SW 21 during an ON period. …” See, for example, Pars [0050] and [0051; See also Pars [0054] and [0056]), and includes a display device configured to display the region of the heater (See, for example, Pars [0106] and [0107]). In regards to claim 13, Endo discloses (See, for example Figs. 1, 3 and 15) the second target temperature distribution is calculated by using a first correlation (it discloses that the temperature of the semiconductor wafer W held on the electrostatic chuck 6 is controlled to a temperature within a predetermined range, See Par [0034], which is a bounded range of the wafer temperature) between output values of the plurality of heater power supplies and a temperature distribution of the wafer (See, Par [0098], and “…the control unit 25 measures the temperature of each of the divided regions 60 using the IR camera 51 (S303). The temperature of each of the divided regions 60 measured by the IR camera 51 is an example of a second temperature.”, See Par [0099]), an upper limit value and a lower limit value of the allowable range of the output of the heater power supply, or an upper limit value and a lower limit value of an allowable range of a temperature of the wafer calculated based on the first correlation, which are stored in association with the semiconductor device manufacturing apparatus (“…the control unit 25 controls the power supplied to the heater 6c based on the difference between the estimated temperature and the target temperature… Step S302 is an example of an adjustment step.”, See par [0098]; “…the control unit 25 holds, for each of the divided regions 60, the calculated correction value ..”,See Par [0099]; and also See, for example, Pars [100]- [0106]). In regards to claim 14, Endo discloses (See, for example, Figs. 1, 3 and 15) that when it is determined that output values of at least one or more heater power supplies among the plurality of the heater power supplies are out of the range that can be implemented, a region of the heater corresponding to the at least one or more heater power supplies is stored (“The power supply unit 20 is provided for each of the heaters 6c disposed in the divided regions 60 of the electrostatic chuck 6 to supply a power to a corresponding heater 6c. … the substrate processing apparatus 100 has forty heaters 6c, and forty power supply units 20 are provided for each of the forty heaters 6c, respectively. Each of the power supply units 20 includes a switch SW 21, an ammeter 22, and a voltmeter 23. Although it is not shown in FIG. 3, one power supply unit 20 is provided for each of one or more heaters 5b disposed in the support 5a. …The SW 21 is turned on or off under the control of the control unit 25 and the power from a power source 27 is supplied to a corresponding heater 6c through the SW 21 during an ON period. …” See, for example, Pars [0050] and [0051; See also Pars [0054] and [0056]), and the region of the heater is displayed (See, for example, Pars [0106] and [0107]). In regards to claim 15 and 16, Endo as modified above discloses that the wafer temperature calculation system is configured to calculate the second output values obtained by correcting all of the first values within the range that can be implemented before the start of the processing of the wafer (the data used to determine and correct the heater power supply output, the conversion table 260 and the correction table 265 are created and stored in the holding unit 26 in advance of the actual process (See, Pars [0053], [0055], [0056]), by the calibration sequence of Figs. 13 and 14 (“The conversion table 260, the correction table 265, the recipe, and the like are created in advance by an operator of the substrate processing system 10 and stored in the holding unit 26.”, See Par [0055], See also Pars [0088]-[0101]). In those sequences, the power supplied to the heater 6c in each divided region 60 is adjusted so that the heater resistance corresponds to a predetermined target temperature, the actual region temperature is measured with the IR camera 51, and a correction value is calculated and stored, all prior to processing a production wafer (See Pars [0098]-[0099]). In another way, applicant’s own specification acknowledges that, in the related art, a target in-plane temperature distribution and the corresponding heater output are calculated from a previously obtained relational expression before the wafer is processed (See, current application PG Pub Par [0005]). Therefore, calculating the corrected output values before the start of processing is a known and conventional practice in the art.) Response to Arguments Applicant's arguments filed 9/1/2026 have been fully considered but they are not persuasive. Applicant argues that Endo merely corrects heater power supply output so the substrate temperature matches a target value based on the difference between actual and target heater temperature, and does not evaluate whether the output values are within a range that can be physically output (See Remarks p. 15). The argument attacks Endo individually. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); See also In In re Merck & Co., Inc., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Endo was not relied upon for the physical-output-range determination; Kasai was, as set forth above. Endo is relied upon for the multi-zone stage, the per-region heater power supply unit 20, and the correction of all of the output values using the stored tables (See, Endo, Pars [0050]-0067]). Applicant argues that Kasai does not teach setting output values in consideration of inter-region heat transfer while recognizing the value may exceed the implementable range (remarks pp. 16-17). Applicant’s own characterization of Kasai concedes the first half: Applicant states that Kasai determines a temperature difference between region Z1 and region Z2 and controls “the heat transfer between” the regions “as much as possible” (Remarks, 9.16, Citing Kasai Pars [0051]-[0052], [0066]). That is the recited calculation of heater output values based on a heat transfer between a first region and at least a second region. Kasai further teaches that the outer-region output is set so the heat flux into Z1 becomes zero (See Par [0066]) and frames the output determination in terms of managing inter-region heat flux (See, Par [0074]). As to the second half, Kasai discloses that each region’s heater power supply has a defined maximum physical output 1000W for the heater of the first region an d1000W fo the heaters of the second to fourth regions (See, Par [0089]). A skilled artisan setting heater outputs against a known maximum necessarily determines whether a required output falls within what the supply can deliver. Applicant’s own specification confirms this is routine, describing the upper and lower limit values in the range that can be output by the heater power supply 202 as a known characteristic unique to each apparatus (See current application PG Pub Par [0044], [0055], and [0047] as quoted at Remarks p. 12). Applicant argues the combination requires impermissible hindsight and lacks a reasonable expectation of success (Remarks p. 19) The motivation is supplied by Kasai itself, not by Applicant’s disclosure. Kasai expressly teaches that per-region independent feedback control, Endo’s approach produces overshoot and undershoot in the central region because thermal interference between regions is not taken into account, an that controlling the outer regions relative to the inner region keeps each region’s deviation within the desired range and shortens settling time (Kasai, Pars [0064]-[0066], [0074], [0090]-[0091]). A skilled artisan improving Endo’s forty-zone electrostatic chuck would look to Kasai’s solution to the very problem Endo’s control scheme exhibits. Both references are Tokyo Electron disclosures directed to multi-zone heater control of a wafer-supporting stage whose region temperatures are estimated from heater resistance (See, Endo, Pars [0052]; Kasai Par [0044]), so the combination is of analogues elements performing their established functions with predictable results. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007). Applicant’s assertion that only “Applicant has determined” a system avoiding out-of-range output values and improving yield (Remarks pp. 19-20) is unsupported attorney argument. Arguments of counsel cannot take the place of evidence, In re Schulze, 346 F.2d 600, 602, 145 USPQ 716, 718 (CCPA 1965) and In re De Blauwe, 736 F.2d 699, 705, 222 USPQ 191, 196 (Fed. Cir. 1984).No declaration or objective evidence of unexpected results has been submitted. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T.. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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Prosecution Timeline

Sep 06, 2023
Application Filed
Nov 13, 2025
Non-Final Rejection (signed) — §103
Dec 16, 2025
Non-Final Rejection mailed — §103
Mar 13, 2026
Response Filed
Jun 02, 2026
Final Rejection mailed — §103
Sep 01, 2026
Request for Continued Examination
Sep 02, 2026
Response after Non-Final Action
Sep 09, 2026
Non-Final Rejection mailed — §103 (current)

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