DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 1 and 3 are pending. Claims 1 and 3 are currently amended.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a grindstone having a size of 10000 or more” which renders the scope of the claim unclear because of the lack of what is being measured in terms of “size” or the dimension of the value “10000”. The specification recites that it is measured in terms of “size of 10000 (#10000)”, which appears, based on available literature, that it may possibly be a size in terms of the abrasive grains of the grindstone (see NPL article titled “Grain sizes: micron, JIS or FEPA?”), however, as per the article there are multiple possible measurement standards/units. Schwandner (US 20120149198 A1) provide evidence that, in the field of endeavor of semiconductor grinding, usually, [and thus not always] such number refers to the grain size “Japanese Industrial Standard JIS R 6001:1998” ([0095-0096], examiner further notes that standards may change over time, or may be discontinued). However, the instant specification does not provide clarity as to what dimension or unit the claimed limitation is with respect to, which renders the claim indefinite, to a person of ordinary skill in the art (including in view of the extrinsic evidence above). The examiner, in consideration of the extrinsic evidence above, will interpret the limitation in the claim to refer to a grain size (unit/standard not specified).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20040038544 A1) in view of Kobayashi (JP 2015082539 A), Zeng (CN 110010458 A), Denda (JP 2004087521 A), Demizu (US 20020167006 A1), Sakou (JP H05337816 A) and Otsuki (JP H03196965 A).
With respect to claim 1, Zhang discloses: A method for processing a wafer comprising; surface-grinding a front surface of the wafer and a back of the wafer surface opposite to the front surface ([0008] describe a lapping process for both sides of the wafer; the process is conventionally done to remove damage from slicing the wafer as in [0003]) and,
double-side polishing both the front surface of the wafer and the back surface of the wafer that has been surface-ground so that removal on the back surface of the wafer is 1/4 or less than that on the front surface of the wafer (double sided polishing to improve the flatness of the wafer as in [0022], see [0003-0004] for background, the polishing is done as in [0017] such that “less wafer material is removed from the back side than the front side and so that the back side has less gloss and a higher roughness than the front side. Accordingly, the front side is visually distinguishable from the back side”, specifically with a ratio of “removal rate ratio is about 10:1, and even more preferably is about 15:1” (which means that the removal of the back is 1/10 - 1/15, which is less than ¼)), the wafer is a silicon wafer ([0013]),
However Zhang does not explicitly disclose that the surface grinding is done with a grindstone having a size of 10000 or more, wherein the double-side polishing is performed so the back surface of the wafer has an arithmetic roughness (Sa) of 1 nm or more in a wavelength length of 10 um to 100 um, the front surface has an arithmetic roughness of 0.1 nm or less, the warp of the wafer is 10 um or less.
Kobayashi, in the same field of endeavor, related to wafer processing, provides that in an abrasive process of the wafer after cutting, a grindstone of #8000 is used (page 3, 2nd paragraph, used to remove roughness from cutting/slicing the wafer), in a double sided process (page 5, 4th paragraph), this step occurs prior to double sided polishing (page 5, 7th paragraph). Kobayashi provides that this method improves productivity (page 6, 2nd paragraph; page 4, 2nd paragraph provides that having a grain size of 8000 or more means that the grains are less than 1 μm).
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Zhang, and have incorporated a double sided grinding process using a grindstone having a size of 8000 or more, as taught by Kobayashi to improve productivity. As for the specifics of a grindstone having a size of 10000 or more, Kobayashi, above is noted to have a size of 8000 or more, MPEP 2144.05 provides that “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. As a range of 10000 or more lies inside a range of 8000 or more from the prior art, the range would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention.
Alternatively, Zeng, in the same field of endeavor, related to wafer processing, teaches of using a grindstone of #6000-10000 to reduce damage (“In addition, preferably, the granularity is 0.5-1 μm grinding wheel (grinding wheel mesh number is 6000-10000). damage layer thereby, grinding wheel using diamond particle size is relatively small, which can make the surface of the semiconductor wafer is small, damage layer is less than 1μm is the best”, page 6, 3rd paragraph).
The range of #6000-10000 in Zeng also overlaps the claimed range of 10000 or more, and as such the claimed range would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention. Alternatively, MPEP 2144.05 provides that discovering workable ranges would have been obvious to a person of ordinary skill in the art, if the range has been shown to be a result effective variable, and if it has not been demonstrated that the range is critical. The instant disclosure does not provide for the criticality of having a grindstone having a size of 10000 or more, only demonstrating some limited evidence of the effect of the grindstone size on warpage without achieving “unexpected results relative to the prior art range” (see instant fig. 2). See MPEP 716.02 for a discussion on unexpected results, and for demonstrating a difference in kind rather than degree, and the “the showing of unexpected results must be reviewed to see if the results occur over the entire claimed range”
Therefore, it would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention to have selected in Zhang, as modified, a size of the grindstone to be the claimed 10000 or more, in order to select an appropriate grain to reduce damage to the wafer (Zeng provides that smaller grains reduce damage to the wafer).
Regarding the limitation that wherein the double-side polishing is performed so the back surface of the wafer has an arithmetic roughness (Sa) of 1 nm or more, Zhang, teaches that the front of the wafer is a mirror (“the wafer W has the flatness and parallelism [reduced warpage] enabled by simultaneous double-side polishing, has a high gloss mirror finish on the front side due to the finish polishing step” [0023]), and the back surface has less gloss than the front side (“the back surface has less gloss than the front surface after polishing”, [0007]).
Denda, in the same field of endeavor, relating to wafer processing, teaches of providing a back surface of the wafer (specifically a silicon wafer in the best mode section of [0026]) with a arithmetic roughness of 1000 and 3000 Angstroms [1 nm = 10 angstrom] ([0027,0007]). Denda teaches that this range of roughness is needed to distinguish both sides and avoid contamination ([0006-0007]; [0004] provides that specifically the device side of the wafer has a mirror finish), and that this can be achieved with different properties of the polishing pad in double sided polishing ([0020]).
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Zhang, such that the back surface of the wafer has an arithmetic roughness (Sa) of 1 nm or more, as taught by Denda, to avoid contamination and to distinguish both sides of the wafer.
Regarding the specifics of the roughness in a wavelength range of 10 um to 100 um, Demizu, in the same field of endeavor, related to wafer processing, teaches that “The roughness distribution within the contact area of the backside of the wafer is effective when the distribution falls into the wavelength range of 5 to 100 um, or more preferably 10 to 50 um according to the present invention. In case the roughness wavelength is 5um or less, the advantage of the present invention does not appear because the effect of the roughness for the contact surface density is small. In case the roughness wavelength surpasses 100 um, it is undesirable because the evenness of the wafer gets worse”. ([0024]), and this provides for stable holding ([0005])
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to have made in Zhang, as modified, the roughness in a wavelength range of 10 um to 100 um, using the teachings of Demizu to ensure that the roughness distribution within the contact area of the backside of the wafer is effective for stable holding, while not having a undesirable evenness. Regarding the claimed ranges of a wavelength range of 10 um to 100 um, MPEP 2144.05 provides that “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. As a range of roughness wavelength of 10 um to 100 um overlaps/lies inside the ranges from the prior art, the claimed ranges would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention.
Alternatively, MPEP 2144.05 provides that discovering workable ranges would have been obvious to a person of ordinary skill in the art, if the range has been shown to be a result effective variable, and if it has not been demonstrated that the range is critical. The instant disclosure does not provide for the criticality of having roughness wavelength of 10 um to 100 um, only repeating the claimed range throughout the disclosure. See MPEP 716.02 for a discussion on unexpected results, and for demonstrating a difference in kind rather than degree, and the “the showing of unexpected results must be reviewed to see if the results occur over the entire claimed range”
Therefore, it would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention to have selected in Zhang, as modified, a roughness wavelength of 10 um to 100 um, for the reasons given by Demizu of providing effective holding, while reducing undesirable unevenness.
Regarding the limitation that the front surface has an arithmetic roughness of 0.1 nm or less, Sakou, in the same field of endeavor, related to wafer processing (specifically silicon wafers as in the abstract), teaches of providing the silicon wafer with an average roughness [arithmetic roughness] of 0.1 nm or less ([0002,0004]), and that “smoother the roughness, the higher the oxide film withstand voltage, the higher voltage can be applied, and the integrated circuit with large storage capacity can be formed. Roughness is determined by the policing conditions.” ([0002]).
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to have made in Zhang, as modified, the arithmetic roughness of the front surface, to be 0.1 nm or less, as taught by Sakou, by variation of the polishing conditions, for the purpose of allowing a higher voltage application that provides a higher capacity integrated circuit.
Regarding the warp of the wafer is 10 um or less, Otsuki, in the same field of endeavor, related to wafer processing, teaches of a method of double sided polishing wafers (page 2 lines 1-4), where the warpage of the wafer is reduced by changing the shape of the carrier so that the wafer does not rotate within the carrier (page 5 lines 1-7), to result in 1-2 um of warping (page 7 lines 11-13, warpage was very small at 1 to 2 μm). Otsuki teaches that this provides very high speed polishing (page 7 lines 14-15, “the method of the present invention makes it possible to polish semiconductor wafers at high speed while preventing warpage”), and that warpage is undesirable as semiconductors require high precision (page 2 lines 1-4).
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to have made in Zhang, as modified, the warpage of the wafer less than 10 um, using the teachings of Otsuki, as semiconductor wafers require high precision.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Denda (JP 2004087521 A) in view of Demizu (US 20020167006 A1), Sakou (JP H05337816 A) and Otsuki (JP H03196965 A).
With respect to claim 3, Denda discloses A silicon wafer ([0026], best mode section) having front surface which is a mirror and a back surface opposite to the front surface (wafer having a mirrored front and a back surface with roughness as in [0007,0027]; [0004] provides that specifically the device side of the wafer has a mirror finish), wherein, the back surface has an arithmetic roughness (Sa) of 1 nm or more (a arithmetic roughness of 1000 and 3000 Angstroms [1 nm = 10 angstrom] [0027,0007]), however does not explicitly teach a wavelength length of 10 to 100 um, and a warp of 10 um or less, wherein the front surface has an arithmetic roughness of 0.1 nm or less.
Regarding the specifics of the roughness in a wavelength range of 10 um to 100 um, Demizu, in the same field of endeavor, related to wafer processing, teaches that “The roughness distribution within the contact area of the backside of the wafer is effective when the distribution falls into the wavelength range of 5 to 100 um, or more preferably 10 to 50 um according to the present invention. In case the roughness wavelength is 5um or less, the advantage of the present invention does not appear because the effect of the roughness for the contact surface density is small. In case the roughness wavelength surpasses 100 um, it is undesirable because the evenness of the wafer gets worse”. ([0024]), and this provides for stable holding ([0005])
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to have made in Denda, as modified, the roughness in a wavelength range of 10 um to 100 um, using the teachings of Demizu to ensure that the roughness distribution within the contact area of the backside of the wafer is effective for stable holding, while not having a undesirable evenness. Regarding the claimed ranges of a wavelength range of 10 um to 100 um, MPEP 2144.05 provides that “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. As a range of roughness wavelength of 10 um to 100 um overlaps/lies inside the ranges from the prior art, the claimed ranges would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention.
Alternatively, MPEP 2144.05 provides that discovering workable ranges would have been obvious to a person of ordinary skill in the art, if the range has been shown to be a result effective variable, and if it has not been demonstrated that the range is critical. The instant disclosure does not provide for the criticality of having roughness wavelength of 10 um to 100 um, only repeating the claimed range throughout the disclosure. See MPEP 716.02 for a discussion on unexpected results, and for demonstrating a difference in kind rather than degree, and the “the showing of unexpected results must be reviewed to see if the results occur over the entire claimed range”
Therefore, it would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention to have selected in Denda, a roughness wavelength of 10 um to 100 um, for the reasons given by Demizu of providing effective holding, while reducing undesirable unevenness.
Regarding the warp of the wafer is 10 um or less, Otsuki, in the same field of endeavor, related to wafer processing, teaches of a method of double sided polishing wafers (page 2 lines 1-4), where the warpage of the wafer is reduced by changing the shape of the carrier so that the wafer does not rotate within the carrier (page 5 lines 1-7), to result in 1-2 um of warping (page 7 lines 11-13, warpage was very small at 1 to 2 μm). Otsuki teaches that this provides very high speed polishing (page 7 lines 14-15, “the method of the present invention makes it possible to polish semiconductor wafers at high speed while preventing warpage”), and that warpage is undesirable as semiconductors require high precision (page 2 lines 1-4).
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to have made in Denda, as modified, the warpage of the wafer less than 10 um, using the teachings of Otsuki, as semiconductor wafers require high precision.
Regarding the limitation that the front surface has an arithmetic roughness of 0.1 nm or less, Sakou, in the same field of endeavor, related to wafer processing (specifically silicon wafers as in the abstract), teaches of providing the silicon wafer with an average roughness [arithmetic roughness] of 0.1 nm or less ([0002,0004]), and that “smoother the roughness, the higher the oxide film withstand voltage, the higher voltage can be applied, and the integrated circuit with large storage capacity can be formed. Roughness is determined by the policing conditions.” ([0002]).
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to have made in Denda, as modified, the arithmetic roughness of the front surface, to be 0.1 nm or less, as taught by Sakou, by variation of the polishing conditions, for the purpose of allowing a higher voltage application that provides a higher capacity integrated circuit.
Response to Arguments
Applicant's arguments filed 02/11/2026 have been fully considered but they are not persuasive.
Regarding the 35 USC 112(b) rejection (response page 3), the examiner submits that claim 1 remains unclear, as the claim itself does not define what the size means, with respect to the grindstone. The applicant argues that the “Japanese Industrial Standard”, (which is not specified as to what particular standard) is common in the art, and because of that, a person of ordinary skill in the art would understand the meaning of the size. The examiner’s position, as reflected in the 112(b) rejection, is that there are multiple standards, and to be definite, the claim is required to recite what dimension is being measured (which can be through reference to a particular standard or otherwise defined in the claim), and the unit (which can be defined in the claim or through reference to a particular standard or otherwise defined in the claim). The applicant’s arguments are not a substitute for a complete disclosure, are not a substitute for evidence, and in any case, do not actually reference a particular standard, only the “Japanese Industrial Standard”. The examiner notes that standards can change over time, and that any reference to a standard should refer to a particular revision, and also notes that the instant disclosure does not reference a particular standard.
Applicant argues that Zhang does not disclose the claimed roughness parameters, warp, or that the wafer is a silicon wafer (response page 4). The examiner disagrees in part, as Zhang provides for a silicon wafer as in [0013], specifically “polish the front and back sides of semiconductor wafers W sliced from one or more monocrystalline silicon ingots”).
The applicant also argues that Inoue describes a silicon carbide substrate (response pages 4-5), and that the parameters relating to a silicon carbide substrate are different. The arguments are moot, as the amended claims necessitated a rejection that does not rely on Inoue, but the examiner nevertheless submits that as long as a wafer contains silicon, the requirements of the claim are met, for the reason that the claim is open-ended, and does not exclude additional elements. This is consistent with [0027] of the instant specification, which provides for an understanding that the invention is not particularly limited as to the wafer.
Regarding Kobayashi (response page 5), it does not appear that the applicant has presented arguments with the reference, but the applicant has pointed out that the grinding wheel size is 7000 or more, however did not otherwise address the obviousness rejection.
Regarding Zeng (response page 6), the applicant pointed of a portion of Zeng not cited by the examiner, specifically relating to single sided thinning, however did not otherwise address the obviousness rejection.
Regarding Demizu (response page 6), the applicant pointed of a portion of Demizu not cited by the examiner, specifically relating to a wafer surface density and contact pressure, however did not otherwise address the obviousness rejection.
Regarding claim 3 (response page 7-8), the examiner submits that the arguments regarding Inoue are moot, as the amended claims necessitated a rejection that does not rely on Inoue, and again notes that the claim is open ended and does not exclude silicon carbide substrates, as long as the wafer contains silicon. Denda is now applied, and discloses a sincon wafer with a mirrored front and roughened back, with an arithmetic roughness greater than 1 nm (with no upper limit), Demizu teaches the aspects relating to the wavelength, Otsuki teaches aspects related to the warpage, and Sakou teaches aspects related to the front roughness.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Steven Huang whose telephone number is (571)272-6750. The examiner can normally be reached Monday to Thursday 6:30 am to 2:30 pm, Friday 6:30 am to 11:00 am (Eastern Time).
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/Steven Huang/Examiner, Art Unit 3723
/JOEL D CRANDALL/Examiner, Art Unit 3723