DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-13 and 15-22 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Son et al. (US 2022/0190295).
Regarding claims 1 and 18, Son discloses a display substrate and method for preparing, having a display area (DA, figs. 1, 6 and paragraph 0061), a barrier region (MA, figs. 1, 6 and paragraph 0062), and an opening region (OA, figs. 1, 6 and paragraph 0061), and comprising a base substrate (100, fig. 6 and paragraph 0105), wherein the display area and the barrier region surround the opening region (fig. 1), and the barrier region is between the display area and the opening region (figs. 1, 6),
the barrier region comprises at least one barrier wall (600, fig. 6 and paragraphs 0102-0103) at least partially surrounding the opening region, and each of the at least one barrier wall comprises a first metal layer structure (620, fig. 8A and paragraph 0153) and a first stack structure (600, fig. 8a), the first metal layer structure is on a side of the first stack structure away from the base substrate (620, fig. 8A), and at least a side surface, surrounding the opening region, of the first metal layer structure has a first notch (fig. 8A and paragraphs 0149-0153);
the display area comprises a plurality of sub-pixels, each of the plurality of sub-pixels comprises a pixel driver circuit and a light-emitting device, the pixel driver circuit comprises a thin film transistor (TFT, fig. 6 and paragraph 0108) and a connection electrode (CM, fig. 6 and paragraph 0116), and the thin film transistor comprises a first source-drain electrode (DE, fig. 6 and paragraph 0108) and a second source-drain electrode (SE, fig. 6 and paragraph 0108), and the light-emitting device comprises a first electrode (221, fig. 6 and paragraph 0118), a second electrode (223, fig. 6 and paragraph 0124), and a light-emitting material layer (222, fig. 6 and paragraph 0120) between the first electrode and the second electrode, and the connection electrode (CM, fig. 6) is configured to electrically connect the first electrode (221, fig. 6) and the first source-drain electrode (DE, fig. 6 and paragraph 0116); and
the first metal layer structure (620, fig. 8A, 6) is in a same layer as the connection electrode (CM, fig. 6 and paragraph 0153).
Regarding claim 2, Son further discloses wherein the first metal layer structure comprises a first metal sub-layer (622, fig. 8A) and a second metal sub-layer (623, fig. 8A) on a side of the first metal sub-layer away from the base substrate, and the first metal sub-layer is retracted inward relative to the second metal sub-layer in a direction parallel to a board surface of the base substrate to form the first notch (fig. 8A and paragraphs 0147-0153); or,
the first metal layer structure comprises a first metal sub-layer (622, fig. 8A), a second metal sub-layer (623, fig. 8A) on a side of the first metal sub-layer away from the base substrate, and a third metal sub-layer (621, fig. 8A) on a side of the first metal sub-layer near the base substrate, and the first metal sub-layer (622, fig. 8A)is retracted inward relative to the second metal sub-layer and the third metal sub-layer in the direction parallel to the board surface of the base substrate to form the first notch (fig. 8A and paragraphs 0147-0153).
Regarding claim 3, Son further discloses wherein the display area further comprises a first planarization layer on a side of the first source-drain electrode and the second source-drain electrode away from the base substrate (207, 209, fig. 6), the first planarization layer has a first via hole (fig. 6 and paragraph 0116), and the connection electrode (CM, fig. 6) is on a side of the first planarization layer away from the base substrate and is electrically connected with the first source- drain electrode through the first via hole (fig. 6 and paragraph 0116),
the first stack structure comprises a first insulation sub-layer on the base substrate (207,fig. 8A, 6 and paragraph 0114), and
the first insulation sub-layer and the first planarization layer are in a same layer (207, figs. 6, 8A).
Regarding claim 4, Son further discloses wherein the at least one barrier wall comprises a plurality of barrier walls (600, fig. 6);
the first metal layers of the plurality of barrier walls are in a same layer and spaced apart from each other, and the first stack structures of the plurality of barrier walls are in a same layer and spaced apart from each other (fig. 6); or,
the first metal layers of the plurality of barrier walls are in a same layer and spaced apart from each other, and the first stack structures of the plurality of barrier walls are in the same layer and constitute an integral structure; and the integral structure has a barrier groove between the first metal layer structures of adjacent ones of the plurality of barrier walls (fig. 6).
Regarding claim 6, Son further discloses wherein the display area further comprises a first passivation layer (207, fig. 6) on a side of the first planarization layer (205, fig. 6) away from the base substrate, the first passivation layer has a second via hole communicated with the first via hole (fig. 6), the connection electrode is on a side of the first passivation layer away from the base substrate (CM, fig. 6), and is electrically connected with the first source-drain electrode (DE, fig. 6)through the first via hole and the second via hole,
the first stack structure further comprises a second insulation sub-layer (207, fig. 6) arranged on a side of the first insulation sub-layer (205, fig. 6) away from the base substrate, and
the second insulation sub-layer and the first passivation layer are in a same layer (207,fig. 6).
Regarding claim 7, Son further discloses wherein the first insulation
sub-layer has a groove between the first metal layer structures of adjacent ones of the plurality of barrier walls, and the second insulation sub-layer is formed on a side of the first insulation sub-layer away from the base substrate with an equal thickness to form the barrier groove at the position of the groove (310, fig. 8A).
Regarding claim 8, Son further discloses wherein the display area further comprises a second passivation layer (207, 209, fig. 6) arranged on a side of the first source-drain electrode (DE, fig. 6) and the second source-drain electrode (SE, fig. 6) away from the base substrate,
the second passivation layer has a third via hole, and the connection electrode is on a side of the second passivation layer away from the base substrate and is electrically connected with the first source-drain electrode through the third via hole (CM, fig. 6),
the first stack structure comprises a third insulation sub-layer on the base substrate (207, fig. 6), and
the third insulation sub-layer and the second passivation layer are arranged in the same
layer (207, fig. 6).
Regarding claim 9, Son further discloses wherein the at least one barrier wall comprises a plurality of barrier walls (600, fig. 6);
the first metal layers of the plurality of barrier walls are in a same layer and spaced apart from each other, and the first stack structures of the plurality of barrier walls are in a same layer and spaced apart from each other (figs. 6, 8A); or,
the first metal layers of the plurality of barrier walls are in a same layer and spaced apart from each other, and the first stack structures of the plurality of barrier walls are in the same layer and constitute an integral structure (fig. 6).
Regarding claim 10, Son further discloses wherein the third insulation
sub-layer in the integral structure has a barrier groove between the first metal layer structures of adjacent ones of the plurality of barrier walls (310, fig. 8A).
Regarding claim 11, Son further discloses wherein the first stack structure (600, fig. 6) further comprises a first metal layer (610, fig. 8A), the first metal layer is on a side of the first insulation sub-layer near the base substrate (207,fig. 8A), and
the first metal layer is in a same layer as the first source-drain electrode and the second
source-drain electrode (figs. 6, 8A and paragraph 0152).
Regarding claim 12, Son further discloses wherein the pixel driver circuit further comprises a storage capacitor (Cst, fig. 6 and paragraph 0108), the thin film transistor further comprises a first gate electrode (GE, fig. 6 and paragraph 0108), and the first gate electrode is on a side of the first source-drain electrode and the second source-drain electrode near the base substrate (fig. 6),
the storage capacitor comprises a first capacitor plate (CE1, fig. 6) and a second capacitor plate (CE2, fig. 6), the first capacitor plate is in a same layer as the first gate electrode (fig. 6 and paragraph 0108), and the second capacitor plate is on a side of the first capacitor plate away from the base substrate (CE2, fig. 6),
the first stack structure further comprises a second metal layer and a third metal layer, the second metal layer is on a side of the third metal layer away from the base substrate, the second metal layer is in a same layer as the second capacitor plate, and the third metal layer is in the same layer as the first capacitor plate (figs. 6, 8A and paragraph 0152).
Regarding claim 13, Son further discloses wherein the display area further comprises a gate insulation layer between the first gate electrode and the second capacitor plate (203, fig. 6), and the gate insulation layer further extends into the barrier region (fig. 6) and is between the second metal layer and the third metal layer and
wherein the display area further comprises an interlayer insulation layer on a side of the
second capacitor plate (207, fig. 6) away from the base substrate, and the interlayer insulation layer further extends into the barrier region and is on a side of the second metal layer away from the base substrate (fig. 6).
Regarding claim 15, Son further discloses wherein the thin film transistor further comprises a second gate electrode, and the second gate electrode is on a side of the interlayer insulation layer away from the base substrate (GE, fig. 6 and paragraph 0109), the first stack structure further comprises a fourth metal layer, and the fourth metal layer is in a same layer as the second gate electrode (paragraph 0109).
Regarding claim 16, Son further discloses a circuit region which is between the display area and the barrier region and at least partially surrounds the display area, wherein the circuit region comprises a plurality of conductive layers and a plurality of insulation layers between adjacent ones of the plurality of conductive layers (paragraph 0062).
Regarding claim 17, Son further discloses a display device, comprising the display substrate according to claim 1 (fig. 1 and paragraph 0060).
Regarding claim 19, Son further discloses wherein the first metal layer structure comprises a first metal sub-layer (622, fig. 8A) and a second metal sub-layer (623, fig. 8A) on a side of the first metal sub-layer away from the base substrate, and the first metal sub-layer is retracted inward relative to the second metal sub-layer in a direction parallel to a board surface of the base substrate to form the first notch (fig. 8A and paragraphs 0147-0153); or,
the first metal layer structure comprises a first metal sub-layer (622, fig. 8A), a second metal sub-layer (623, fig. 8A) on a side of the first metal sub-layer away from the base substrate, and a third metal sub-layer (621, fig. 8A) on a side of the first metal sub-layer near the base substrate, and the first metal sub-layer (622, fig. 8A)is retracted inward relative to the second metal sub-layer and the third metal sub-layer in the direction parallel to the board surface of the base substrate to form the first notch (fig. 8A and paragraphs 0147-0153).
forming the display area further comprises: forming a first planarization layer on a side of the first source-drain electrode and the second source-drain electrode away from the base substrate (207, 209, fig. 6), the first planarization layer has a first via hole (fig. 6 and paragraph 0116), and the connection electrode (CM, fig. 6) is on a side of the first planarization layer away from the base substrate and is electrically connected with the first source- drain electrode through the first via hole (fig. 6 and paragraph 0116),
the first stack structure comprises a first insulation sub-layer on the base substrate (207,fig. 8A, 6 and paragraph 0114), and
the first insulation sub-layer and the first planarization layer are in a same layer (207, figs. 6, 8A).
Regarding claim 20, Son further discloses wherein the first metal layer structure comprises a first metal sub-layer (622, fig. 8A) and a second metal sub-layer (623, fig. 8A) on a side of the first metal sub-layer away from the base substrate, and the first metal sub-layer is retracted inward relative to the second metal sub-layer in a direction parallel to a board surface of the base substrate to form the first notch (fig. 8A and paragraphs 0147-0153); or,
the first metal layer structure comprises a first metal sub-layer (622, fig. 8A), a second metal sub-layer (623, fig. 8A) on a side of the first metal sub-layer away from the base substrate, and a third metal sub-layer (621, fig. 8A) on a side of the first metal sub-layer near the base substrate, and the first metal sub-layer (622, fig. 8A)is retracted inward relative to the second metal sub-layer and the third metal sub-layer in the direction parallel to the board surface of the base substrate to form the first notch (fig. 8A and paragraphs 0147-0153).
forming the display area further comprises: forming a second passivation layer (207, 209, fig. 6) arranged on a side of the first source-drain electrode (DE, fig. 6) and the second source-drain electrode (SE, fig. 6) away from the base substrate,
the second passivation layer has a third via hole, and the connection electrode is on a side of the second passivation layer away from the base substrate and is electrically connected with the first source-drain electrode through the third via hole (CM, fig. 6),
the first stack structure comprises a third insulation sub-layer on the base substrate (207, fig. 6), and the third insulation sub-layer and the second passivation layer are arranged in the same layer (207, fig. 6).
Regarding claim 21, Son further discloses wherein forming the first metal layer structure and the connection electrode comprises:
forming a connection electrode material layer, and pattern the connection electrode
material layer to form the connection electrode and a first metal layer initial structure (CM, fig. 6 and paragraph 0116);
forming a second planarization layer on a side of the connection electrode and the first
metal layer initial structure away from the base substrate, wherein the second planarization layer comprises a third via hole exposing the connection electrode and an opening exposing the first metal layer initial structure (211,fig. 6 and paragraphs 0116-0117);
forming a first electrode material layer on a side of the second planarization layer away
from the base substrate, etching the first electrode material layer and the initial structure of the first electrode material layer with a same etching solution to form the first electrode and the first notch, and the first electrode is electrically connected with the connection electrode through the third via hole (figs. 6, 8A and paragraphs 0147-0154).
Regarding claim 22, Son further discloses forming a circuit region which is between the display area and the barrier region and at least partially surrounding the display area, the circuit region comprises a plurality of conductive layers, and a plurality of insulation layers between adjacent ones of the plurality of conductive layers, wherein,
after the connection electrode and the first metal layer initial structure are formed, the
plurality of conductive layers and the plurality of insulation layers between the adjacent ones of the plurality of conductive layers are formed, and then the first electrode material layer and the first metal layer initial structure are etched by a same etching solution (paragraph 0062).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2020/0403180 discloses a similar display device with an opening and barrier layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 5/1/26
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