DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4, 9-12, and 16-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
Claim(s) 1, 4, 9-12 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwek (US 20110208885) in view of Tseng (US 20200383012) in view of Nguyen (US 20220365676).
Regarding claim 1, Kwek teaches A method for repairing hanging-up of a communication bus, applied to a central processing unit, comprising: (“to provide a method to detect a hang in the I2C bus and clear the hang” ¶9)… , determining a target hanging-up event generated by the communication bus deployed between the central processing unit and the baseband processing unit; obtaining a target repairing operation corresponding to the target hanging-up event; and according to the target repairing operation, repairing the communication bus. (“Hang prevention module 411 monitors the clock signal on output clock line 413 and is used to clear the hanging at serial clock line 401, while hang prevention module 412 monitors the data signal on output data line 414 and is used to clear the hanging at serial data line 402. “ ¶25); and according to the target connecting mode, determining the target hanging-up event generated by the communication bus, wherein the target hanging-up event comprises a serial- data-line hanging-up event and a serial-clock-line hanging-up event; (“Hang prevention module 411 monitors the clock signal on output clock line 413 and is used to clear the hanging at serial clock line 401, while hang prevention module 412 monitors the data signal on output data line 414 and is used to clear the hanging at serial data line 402. “ ¶25);
the central processing unit is bidirectionally connected to the hot-plug chip by the communication bus; and the hot-plug chip is bidirectionally connected to the baseband processing unit by the communication bus. (“The I2C bus 103 requires two bi-directional bus lines, a serial clock line 101 and a serial data line 102. Collectively, both the serial clock line 101 and the serial data line 102” ¶2) that the central processing unit is serially connected to the hot-plug chip and the baseband processing unit by the communication bus comprises: the central processing unit is connected to the baseband processing unit by the communication bus; or the central processing unit is serially connected to a hot-plug chip and the baseband processing unit by the communication bus. (“The I2C bus 103 requires two bi-directional bus lines, a serial clock line 101 and a serial data line 102. Collectively, both the serial clock line 101 and the serial data line” ¶2)
Kwek discloses the repairing of communications shown above, and communication between a master and slave device (“In the I2C bus communication, the device which initiates a data transfer on the I2C bus 403 and generates the clock signals to permit that transfer is referred as master while any device responding to the transfer is considered a slave. In an embodiment, any of the I2C devices can act as a master or slave device” ¶31), but does not teach between a processor and specifically detecting a communication situation between a central processing unit and a baseband processing unit, determining the target hanging-up event generated by the communication bus deployed between the central processing unit and the baseband processing unit comprises: detecting a target connecting mode at a current moment between the central processing unit and the baseband processing unit; the target connecting mode comprises: the central processing unit is connected to the baseband processing unit by the communication bus; or the central processing unit is serially connected to a hot-plug chip and the baseband processing unit by the communication bus;
Tseng teaches detecting a communication situation between the central processing unit and a baseband processing unit; (“ such data stall conditions have become more prominent and recovery slowed due to a baseband processor of the mobile station being in a limited service and/or out of service state.” ¶105); determining the target hanging-up event generated by the communication bus deployed between the central processing unit and the baseband processing unit comprises: detecting a target connecting mode at a current moment between the central processing unit and the baseband processing unit; (“the monitoring entity 908 may report an aggregated data stall hint to cellular interface 930 (e.g., a cellular baseband processor). Upon receiving the aggregated data stall hint, cellular interface 930 may take one or more actions to mitigate a data/media stall.” ¶114).; the target connecting mode comprises: the central processing unit is connected to the baseband processing unit by the communication bus; or the central processing unit is serially connected to a hot-plug chip and the baseband processing unit by the communication bus; (“ The UE 106 may include a processor that is configured to execute program instructions stored in memory. The UE 106 may perform any of the method embodiments described herein by executing such stored instructions” ¶57. “In general, a radio may include any combination of a baseband processor” ¶58, Figure 3, 300, 302, 330.) ). It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to apply the communication bus hang detection and correcting methods taught by Kwek with the application to a baseband processing unit stall as taught by Tseng. Kwek teaches communications between master and slave devices over a bus. Tseng teaches communications between a processor and a baseband processor (“Similarly, modem 520 may include one or more processors 522…” ¶87, “The baseband processor architecture 800 described in FIG. 8 may be implemented on one or more radios (e.g., radios 329 and/or 330 described above) or modems (e.g., modems 510 and/or 520) ¶100”) over a bus (“ Carrier Medium—a memory medium as described above, as well as a physical transmission medium, such as a bus…” ¶31), which would integrate with the master-slave device communications taught by Kwek.
Kwek and Tseng do not teach when it is detected that the baseband processing unit is in a pulling-out state, sending a first controlling instruction to a programing logic device corresponding to the hot-plug chip, wherein the first controlling instruction is configured for controlling the programing logic device to stop supplying electric power to the hot-plug chip;after the hot-plug chip stops operating, detecting a plugging state of the baseband processing unit; andwhen the plugging state is configured for indicating that the baseband processing unit is in an insertion state, sending a second controlling instruction to the programing logic device, wherein the second controlling instruction is configured for controlling the programing logic device to start supplying the electric power to the hot-plug chip; wherein sending the second controlling instruction to the programing logic device comprises: detecting an initialization progress after the baseband processing unit is inserted, and when the initialization progress reaches a predetermined progress, sending the second controlling instruction to the programing logic device. Nguyen teaches when it is detected that the baseband processing unit is in a pulling-out state, sending a first controlling instruction to a programing logic device corresponding to the hot-plug chip, wherein the first controlling instruction is configured for controlling the programing logic device to stop supplying electric power to the hot-plug chip; (“A hot swappable SMBus buffer (an example of which may be an NXP PCA9511A, the data sheet thereof being incorporated by reference herein in its entirety) may be implemented to address corruption of clock or data lines and, additionally, prevent loading down of an SMBus by an unpowered module. In some examples, during shutdown of a COM Express module, an enable pin on the SMBus buffer shall be pulled low to isolate the local SMBus interface from the main chassis SMBus (e.g., management communications flowing through a BMC or I2C switch of the back-plane PCB) and pulled high during active operation” ¶68) after the hot-plug chip stops operating, detecting a plugging state of the baseband processing unit; and when the plugging state is configured for indicating that the baseband processing unit is in an insertion state, sending a second controlling instruction to the programing logic device, wherein the second controlling instruction is configured for controlling the programing logic device to start supplying the electric power to the hot-plug chip; wherein sending the second controlling instruction to the programing logic device comprises: detecting an initialization progress after the baseband processing unit is inserted, and when the initialization progress reaches a predetermined progress, sending the second controlling instruction to the programing logic device. (“During insertion of the management module, the enable line may be held low until the tray is seated completely and the hot swap controller has enabled the primary voltage power source.” ¶68). It would have been obvious for one of ordinary skill in the art to combine the I2C device communication repair methods taught by Kwek and Tseng with the hot-swap power on/off procedures as taught by Nguyen. Hot swappable devices allow for the replacement of devices without powering down the system (Nguyen ¶59).
Regarding claim 4, Tseng, Nguyen and Kwek teach The method according to claim 1 shown above. Tseng teaches wherein according to the target connecting mode, determining the target hanging-up event generated by the communication bus comprises: when the target connecting mode is that the central processing unit is connected to the baseband processing unit by the communication bus,(“The UE 106 may include a processor that is configured to execute program instructions stored in memory. The UE 106 may perform any of the method embodiments described herein by executing such stored instructions” ¶57. “In general, a radio may include any combination of a baseband processor” ¶58), Figure 3, 300, 302, 330). Kwek teaches the target hanging-up event is the serial clock-line hanging-up event; (“Hang prevention module 411 monitors the clock signal on output clock line 413 and is used to clear the hanging at serial clock line 401” ¶25)
Kwek teaches and when the target connecting mode is that the central processing unit is serially connected to the hot-plug chip and the baseband processing unit by the communication bus, (The I2C bus 103 requires two bi-directional bus lines, a serial clock line 101 and a serial data line 102. Collectively, both the serial clock line 101 and the serial data line” ¶2)
Regarding claim 9, Kwek and Tseng teach the steps of the method according to claim 1. Tseng also teaches One or more non-volatile computer-readable storage mediums storing a computer-readable instruction, wherein the computer-readable instruction, when executed by one or more processors (“…a non-volatile memory such as a Flash, magnetic media, e.g., a hard drive,…The memory medium may store program instructions (e.g., embodied as computer programs) that may be executed by one or more processors” ¶30).
Regarding claim 10, Tseng teaches An electronic device, wherein the electronic device comprises a memory and one or more processors, “The programmable function blocks may range from fine grained (combinatorial logic or look up tables) to coarse grained (arithmetic logic units or processor cores)”¶32) the memory stores a computer-readable instruction, and the computer-readable instruction when executed by the one or more processors, causes the one or more processors to…(“ The memory medium may store program instructions (e.g., embodied as computer programs) that may be executed by one or more processors” ¶30).
Regarding claim 11, Tseng teaches wherein detecting the communication
situation between the central processing unit and the baseband processing unit comprises: obtaining data transmission parameters on the communication bus deployed between the central processing unit and the baseband processing unit; (“Additionally, in some implementations, recovery may be slowed due to the baseband processor falling back to a slower than optimal RAT prior to the data stall condition occurring” ¶105); and according to the data transmission parameters, determining the communication situation between the central processing unit and the baseband processing unit. (“such data stall conditions have become more prominent and recovery slowed due to a baseband processor of the mobile station being in a limited service and/or out of service state” ¶105)
Regarding claim 12, Kwek and Tseng teach the method according to claim 11 as shown above. Tseng also teaches wherein the data transmission parameters
comprises: a transmission speed and a transmission amount. (Further, more expensive interfaces may be re-selected to supplement and/or replace cheaper interfaces when a cheaper interface is unable to connect, loses its connection, and/or provides insufficient performance (e.g., latency and/or throughput)” ¶106).
Regarding claim 16, Tseng and Kwek teach The electronic device according to claim 10 as shown above. Tseng teaches wherein according to the target connecting mode, determining the target hanging-up event generated by the communication bus comprises: when the target connecting mode is that the central processing unit is connected to the baseband processing unit by the communication bus,(“The UE 106 may include a processor that is configured to execute program instructions stored in memory. The UE 106 may perform any of the method embodiments described herein by executing such stored instructions” ¶57. “In general, a radio may include any combination of a baseband processor” ¶58), Figure 3, 300, 302, 330). Kwek teaches the target hanging-up event is the serial clock-line hanging-up event; (“Hang prevention module 411 monitors the clock signal on output clock line 413 and is used to clear the hanging at serial clock line 401” ¶25). Lin teaches and when the target connecting mode is that the central processing unit is serially connected to the hot-plug chip and the baseband processing unit by the communication bus, (““The processor in FIG. 14 integrates functions of the baseband processor and the central processing unit. A person skilled in the art may understand that the baseband processor and the central processing unit may be processors independent of each other, and are interconnected by using technologies such as a bus.” ¶205, “the another plug-in interface may be at least one of a full-frequency interface, a hot plug interface, and a dual-card management interface.” ¶95”).
Claims 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng, Kwek, Nguyen in view of Tanaka (US 20180173465).
Regarding claim 5, Tseng, Nguyen and Kwek teach The method according to claim 1 as shown above. Kwek teaches wherein when the target hanging-up event is the serial-clock-line hanging-up event according to the target repairing operation, (“Hang prevention module 411 monitors the clock signal on output clock line 413 and is used to clear the hanging at serial clock line 401”). They do not teach repairing the communication bus comprises: switching the central processing unit to a general purpose input/output (GPIO) inputting mode; when the central processing unit changes from a high level to a low level in the GPIO inputting mode, switching the central processing unit from the GPIO inputting mode to a GPIO outputting mode; when the central processing unit changes from the low level to the high level in the GPIO outputting mode, switching the central processing unit from the GPIO outputting mode to an IIC mode.
Tanaka teaches repairing the communication bus comprises: switching the central processing unit to a general purpose input/output (GPIO) inputting mode; when the central processing unit changes from a high level to a low level in the GPIO inputting mode, switching the central processing unit from the GPIO inputting mode to a GPIO outputting mode; (“The main controller 301 outputs a bus select signal bus_select and a reset signal touch_reset_n from the general-purpose output terminals 78 and 79 of the general purpose IO port 314, respectively” ¶59); when the central processing unit changes from the low level to the high level in the GPIO outputting mode, switching the central processing unit from the GPIO outputting mode to an IIC mode. (“When the write data is not the last data, after waiting for expiration of the MODE hold time MHT (S90) from time t8 to t10, the host-side board 300 switches the bus select signal bus select output from the general-purpose output terminal 78 to select the I2C communication (S91) by controlling the general-purpose IO port” ¶112). It would be obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the baseband communication monitoring and hang clearing methods taught by Tseng and Kwek with the switching of IO modes as taught by Tanaka. This eliminates the need of mode switching through hardware reset (Tanaka ¶113).
Regarding claim 17, Tseng and Kwek teach The electronic device according to claim 10, as shown above. Tanaka teaches repairing the communication bus comprises: switching the central processing unit to a general purpose input/output (GPIO) inputting mode; when the central processing unit changes from a high level to a low level in the GPIO inputting mode, switching the central processing unit from the GPIO inputting mode to a GPIO outputting mode; (“The main controller 301 outputs a bus select signal bus_select and a reset signal touch_reset_n from the general-purpose output terminals 78 and 79 of the general purpose IO port 314, respectively” ¶59); when the central processing unit changes from the low level to the high level in the GPIO outputting mode, switching the central processing unit from the GPIO outputting mode to an IIC mode. (“When the write data is not the last data, after waiting for expiration of the MODE hold time MHT (S90) from time t8 to t10, the host-side board 300 switches the bus select signal bus select output from the general-purpose output terminal 78 to select the I2C communication (S91) by controlling the general-purpose IO port” ¶112).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/SEAN KEVIN MCNAMARA/ Examiner, Art Unit 2113
/PHILIP GUYTON/ Primary Examiner, Art Unit 2113
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