Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in Japan on 03/24/2021.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 09/18/2023 has/have been considered by the examiner and made of record in the application file.
Claim Interpretation
Claim 6 appears to have been amended in the amended claim set submitted on 09/18/2023 with the following “The semiconductor device according to claim 1, further comprising . . .” to modify claim dependency. However, the claim was not indicated as (currently amended) in the amendment. For the purposes of this examination, it will be interpreted that (currently amended) is recited at the beginning of the claim and the amendment will be considered in this office action.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 6 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 is indefinite in view of claim limitations which are unclear or at least appear to contradict each other. Claim 6 recites the device of claim 1 ”further comprising a circuit substrate including a first circuit board and a second circuit board” in the first three lines. This is interpreted to mean, based on Figure 6, that the circuit substrate (#14a) includes, as part of the structure, two circuit boards (#16a and #16b). However, claim 6 further recites in lines 4 and 5 that “the first conductor includes the first circuit board, and the second conductor includes the second circuit board”. This is interpreted to mean that the first and second conductors (#31a/#31b) include, within their structure, the two circuit boards (#16a/#16b), respectively. These two limitations render the claim indefinite as it is unclear which structures (first/second conductors or circuit substrate) include the two circuit boards or if the circuit substrate is intended to be included in the first/second conductors. For this reason, claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention. Based on support in Figure 6, claim 6 will be interpreted to read as:
Claim 6. The semiconductor device according to claim 1, further comprising a circuit substrate including a first circuit board and a second circuit board, wherein
the first conductor is on the first circuit board, and
the second conductor is on the second circuit board.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5-7, 9-13, and 16-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2012/0256194 A1; Yoshihara et al.; 10/2012; (“Yoshihara”).
Regarding Claim 1. Yoshihara discloses A semiconductor device (Figure 14, power module) comprising:
a first conductor (#23, Figure 14, first lower conductor layer);
a second conductor (#43, Figure 14, second lower conductor layer );
a first transistor chip (#Tr1, Figure 14, first switching element which may be a transistor according to [0018] and is a chip according to [0150]) mounted on the first conductor ([0150], “first lower conductor layer 23, a first switching element Tr1 . . . are bonded by a high-temperature solder 87A”);
a second transistor chip (#Tr2, Figure 14, second switching element which may be a transistor according to [0018] and is a chip according to [0158]) mounted on the second conductor ([0158], “second lower conductor layer 43, a second switching element Tr1 . . . are bonded by a high-temperature solder 97A”);
a plate-shaped P terminal (#P, Figure 14, power supply terminal);
a plate-shaped O terminal (#O, Figure 14, output terminal); and
a plate-shaped N terminal (#N, Figure 14, second power supply terminal);
the first transistor chip having a source pad electrically connected to the O terminal (Figure 14, [0146], #Tr1s have a source electrically connected to the output terminal #O through the first upper conductor layer #24 and wires #25),
the second transistor chip having a source pad electrically connected to the N terminal (Figure 14, [0147], #Tr2s have a source electrically connected to the second power supply terminal #N through the second upper conductor layer #44 and wires #45),
the first transistor chip having a drain pad electrically connected to the first conductor ([0150], “first switching element Tr1 has a drain terminal at its lower surface (-Z direction-side surface) facing the first lower conductor layer 23 . . . the drain terminal is bonded to the first lower conductor layer 23 by the high-temperature solder 87A”),
the second transistor chip having a drain pad electrically connected to the second conductor ([0158], “second switching element Tr2 has a drain terminal at its lower surface (-Z direction-side surface) facing the second lower conductor layer 43 . . . the drain terminal is bonded to the second lower conductor layer 43 by the high-temperature solder 97A”),
the P terminal being electrically connected to the first conductor (Figure 14, [0207], the power supply terminal #P has a leg portion #175 which is electrically connected to #23),
the O terminal being bonded to the second conductor (Figure 14, [0207], the output terminal #O has a leg portion #152 bonded to #43),
as viewed in a thickness direction of the first transistor chip (Figure 14, z-direction), the O terminal including a region overlapping with the first conductor with spacing therebetween in the thickness direction (Figure 14, at least the leg portion #151 of the output terminal #O is overlapping with #23, [0114] describes that #23 extends over the entire upper surface of #21, with spacing therebetween in the z-direction filled by #22 and #24),
the N terminal including a region overlapping with the second conductor with spacing therebetween in the thickness direction (Figure 14, at least the leg portion #178 of the second power supply terminal #N is overlapping with #43, [0125] describes that #43 extends over the entire upper surface of #41, with spacing therebetween in the z-direction filled by #42 and #44).
Regarding Claim 3. Yoshihara discloses A semiconductor device (Figure 14, power module) comprising:
a first conductor (#23, Figure 14, first lower conductor layer);
a second conductor (#43, Figure 14, second lower conductor layer );
a first transistor chip (#Tr1, Figure 14, first switching element which may be a transistor according to [0018] and is a chip according to [0150]) mounted on the first conductor ([0150], “first lower conductor layer 23, a first switching element Tr1 . . . are bonded by a high-temperature solder 87A”);
a second transistor chip (#Tr2, Figure 14, second switching element which may be a transistor according to [0018] and is a chip according to [0158]) mounted on the second conductor ([0158], “second lower conductor layer 43, a second switching element Tr1 . . . are bonded by a high-temperature solder 97A”);
a plate-shaped P terminal (#P, Figure 14, power supply terminal);
a plate-shaped O terminal (#O, Figure 14, output terminal); and
a plate-shaped N termina (#N, Figure 14, second power supply terminal)l;
the first transistor chip having a source pad electrically connected to the O terminal (Figure 14, [0146], #Tr1s have a source electrically connected to the output terminal #O through the first upper conductor layer #24 and wires #25),
the second transistor chip having a source pad electrically connected to the N terminal (Figure 14, [0147], #Tr2s have a source electrically connected to the second power supply terminal #N through the second upper conductor layer #44 and wires #45),
the first transistor chip having a drain pad electrically connected to the first conductor ([0150], “first switching element Tr1 has a drain terminal at its lower surface (-Z direction-side surface) facing the first lower conductor layer 23 . . . the drain terminal is bonded to the first lower conductor layer 23 by the high-temperature solder 87A”),
the second transistor chip having a drain pad electrically connected to the second conductor ([0158], “second switching element Tr2 has a drain terminal at its lower surface (-Z direction-side surface) facing the second lower conductor layer 43 . . . the drain terminal is bonded to the second lower conductor layer 43 by the high-temperature solder 97A”),
the P terminal being electrically connected to the first conductor (Figure 14, [0207], the power supply terminal #P has a leg portion #175 which is electrically connected to #23),
the O terminal being bonded to the second conductor with a bonding material having electrical conductivity (Figure 14, [0193], the output terminal #O has a leg portion #151 bonded to the first upper conductor layer (#24) which is indirectly bonded to #43 as all features are part of the same device, i.e. #O is indirectly bonded to #43 through conductive material #24),
as viewed in a thickness direction of the first transistor chip (Figure 14, z-direction), the O terminal including a region overlapping with the first conductor with spacing therebetween in the thickness direction (Figure 14, at least the leg portion #151 of the output terminal #O is overlapping with #23, [0114] describes that #23 extends over the entire upper surface of #21, with spacing therebetween in the z-direction filled by #22 and #24),
the N terminal including a region overlapping with the second conductor with spacing therebetween in the thickness direction (Figure 14, at least the leg portion #178 of the second power supply terminal #N is overlapping with #43, [0125] describes that #43 extends over the entire upper surface of #41, with spacing therebetween in the z-direction filled by #42 and #44).
Regarding Claim 5. Yoshihara discloses The semiconductor device according to claim 1,wherein at least one of the first conductor and the second conductor includes a heat dissipation plate (Figure 14, both #23 and #43 are thermally connected between heat radiating base #2 and #Tr1/2, used to radiate heat from the switching chips according to [0034], i.e. #23 and #43 may be interpreted as including a heat dissipation plate functioning to transfer heat from the semiconductor chips to heat radiating base #2).
Regarding Claim 6. Yoshihara discloses The semiconductor device according to claim 1, further comprising a circuit substrate (#2, Figure 14, heat dissipation plate which is functioning as a substrate for the entire circuit structure) including a first circuit board (#21, Figure 14, first lower board which may be interpreted as part of the substrate structure) and a second circuit board (#41, Figure 14, second lower board which may be interpreted as part of the substrate structure), wherein
the first conductor is on the first circuit board (Figure 14, #23 is on #21), and
the second conductor is on the second circuit board (Figure 14, #43 is on #41).
Regarding Claim 7. Yoshihara discloses The semiconductor device according to claim 1, further comprising a first conductive member (#25, Figure 14, wire) and a second conductive member (#45, Figure 14, wire), wherein
the source pad of the first transistor chip is connected to the O terminal with the first conductive member (Figure 14, [0150], the source terminal of #Tr1 is electrically connected to #24 and the output terminal, #O, through #25), and
the source pad of the second transistor chip is connected to the N terminal with the second conductive member (Figure 14, [0158], the source terminal of #Tr2 is electrically connected to #44 and the second power supply terminal, #N, through #45).
Regarding Claim 9. Yoshihara discloses The semiconductor device according to claim 1, wherein the O terminal includes a region arranged parallel to the N terminal (Figure 14, the main body portion, #150, of #O is arranged to be at least partially parallel with the main body portion, #176, of #N, both extending in the X direction).
Regarding Claim 10. Yoshihara discloses The semiconductor device according to claim 1, wherein at least one of the P terminal and the first conductor includes a region arranged parallel to the O terminal (Figure 14, the main body portion, #173, of #P is arranged to be at least partially parallel with the main body portion, #150, of #O, both extending in the X direction; #23 also includes a region which is arranged in parallel with the leg portion, #151, of #O, both extending in the Y direction).
Regarding Claim 11. Yoshihara discloses The semiconductor device according to claim 1, wherein at least one of the P terminal and the first conductor includes a region arranged parallel to the O terminal and the N terminal (Figure 14, the main body portion, #173, of #P is arranged to be at least partially parallel with the main body portion, #150, of #O and the main body portion, #176, of #N, all three extending in the X direction; #23 also includes a region which is arranged in parallel with the leg portion, #151, of #O and the transverse portion, #177, of #N, all three extending in the Y direction).
Regarding Claim 12. Yoshihara discloses The semiconductor device according to claim 1, wherein the second conductor includes a region arranged parallel to each of the P terminal, the O terminal, and the N terminal (Figure 14, #43 includes a region which is arranged in parallel with the leg portion, #152, of #O, the transverse portion, #177, of #N, and the transverse portion, #174, of #P, all four elements extending in the Y direction and appearing parallel to one another when viewed in the z-direction).
Regarding Claim 13. Yoshihara discloses The semiconductor device according to claim 1, further comprising a diode chip (#Di1/#Di2, Figure 14, first/second diode elements which are chips according to [0150] and [0158]) electrically connected in parallel with at least one of the first transistor chip ([0106], “the first switching elements Tr1 and the first diode elements Di1 are connected in parallel”) and the second transistor chip ([0110], “the second switching elements Tr2 and the second diode elements Di2 are connected in parallel”).
Regarding Claim 16. Yoshihara discloses The semiconductor device according to claim 1, comprising:
a plurality of said first transistor chips (Figure 14, at least four different #TR1s are observed in the device); and
a plurality of said second transistor chips (Figure 14, at least four different #TR2s are observed in the device).
Regarding Claim 17. Yoshihara discloses The semiconductor device according to claim 1, wherein as viewed in the thickness direction of the first transistor chip (Figure 14, z-direction),
the O terminal is connected to the first transistor chip in a region of the O terminal arranged parallel to the P terminal (Figure 14, when viewed in the z-direction, the leg portion #151 of #O, which is connected to #Tr1 by #24 and #25, is arranged parallel to the leg portion #175 of #P), and
the N terminal is connected to the second transistor chip in a region of the N terminal arranged parallel to the O terminal (Figure 14, when viewed in the z-direction, the leg and transverse portions #178 and #177 of #N, which is connected to #Tr2 by #44 and #45, is arranged parallel to the leg portion #152 of #O).
Regarding Claim 18. Yoshihara discloses The semiconductor device according to claim 7,comprising:
a plurality of said first conductive members , the first conductive members each having an equivalent length (Figure 14, a plurality of #25s connecting each #Tr1 are observed wherein each batch of #25s to a respective #Tr1 have an equivalent length in the x direction, that length being the “minimum length” detailed in Figure 7 and [0184]); and
a plurality of said second conductive members, the second conductive members each having an equivalent length (Figure 14, a plurality of #45s connecting each #Tr2 are observed wherein each batch of #45s to a respective #Tr2 have an equivalent length in the x direction, that length being the “minimum length” detailed in Figure 7 and [0131]).
Regarding Claim 19. Yoshihara discloses The semiconductor device according to claim 1, further comprising a plate-shaped gate control terminal (#G1/#G2, Figure 14, gate terminals) connected to a gate pad of the first transistor chip or a gate pad of the second transistor chip ([0123] and [0135], the gate terminals #G1/#G2 are electrically connected to the gates of #Tr1 and #Tr2 through the controlling conductor layers #28/#48 and the wires #32/#52), wherein
as viewed in the thickness direction of the first transistor chip (Figure 14, z-direction), the gate control terminal has a region overlapping with the first conductor or the second conductor with spacing therebetween in the thickness direction (Figure 14, the portions of #G1/#G2 which extend in the Y direction overlap with the portions of #23/#43 which are located in the bottom right and bottom left corners, respectively).
Regarding Claim 20. Yoshihara discloses The semiconductor device according to claim 19, further comprising a third conductive member (#32/#52, Figure 14, wires), wherein
the gate control terminal is electrically connected to the gate pad of the first transistor chip or the gate pad of the second transistor chip with the third conductive member ([0123] and [0135], the gate terminals #G1/#G2 are electrically connected to the gates of #Tr1 and #Tr2 through the controlling conductor layers #28/#48 and the wires #32/#52).
Regarding Claim 21. Yoshihara discloses The semiconductor device according to claim 1, further comprising a plate-shaped source sense control terminal (#SS1/#SS2, Figure 14, source sense terminals) connected to the source pad of the first transistor chip or the source pad of the second transistor chip ([0122] and [0134], the source sense terminals #SS1/#SS2 are electrically connected to the sources of #Tr1 and #Tr2 through the controlling conductor layers #27/#47 and the wires #31/#51), wherein
as viewed in the thickness direction of the first transistor chip (Figure 14, z-direction), the source sense control terminal has a region overlapping with the first conductor or the second conductor (Figure 14, the portions of #SS1/#SS2 which extend in the Y direction overlap with the portions of #23/#43 which are located in the bottom right and bottom left corners, respectively).
Regarding Claim 22. Yoshihara discloses The semiconductor device according to claim 21, further comprising a fourth conductive member (#31/#51, Figure 14, wires), wherein
the source sense control terminal is connected to the source pad of the first transistor chip or the source pad of the second transistor chip with the fourth conductive member ([0122] and [0134], the source sense terminals #SS1/#SS2 are electrically connected to the sources of #Tr1 and #Tr2 through the controlling conductor layers #27/#47 and the wires #31/#51).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0256194 A1; Yoshihara et al.; 10/2012; (“Yoshihara”) as applied to claim 1 above, and further in view of US 2011/0186999 A1; Momose et al.; 08/2011; (“Momose”).
Regarding Claim 2. Yoshihara discloses The semiconductor device according to claim 1.
Yoshihara does not disclose that the bonding between the O terminal and the second conductor includes at least one of ultrasonic bonding and bonding by welding. Yoshihara describes only that the O terminal and the second conductor are bonded to one another ([0193], “the bonding portion 152b [of #O] is bonded to a +Y direction-side marginal portion of the second lower conductor layer 43”).
However, Momose teaches a semiconductor device (Figure 1) comprising a plurality of terminals (#18 and #20, Figure 1, terminals) bonded to conductive plates (#14b, Figures 1 and 2, circuit patterns) for providing electrical connections to various semiconductor chips (#16, Figure 1, power semiconductor chips) located on the substrates (#14, Figure 1, insulating substrate), wherein the bonding between the terminals and the conductive plates is achieved via ultrasonic bonding (Figure 2, [0031], “in the state where external connection terminal 18, 20 is retained by a jig, bonding end portion 18c, 20a is moved down to abut against circuit pattern 14b of insulating substrate 14, and ultrasonic welding tool 24 is disposed on bonding end portion 18c, 20a . . . ultrasonic welding is performed.”).
Since Yoshihara is silent regarding the method utilized to bond the O terminal to the second conductor, this would motivate one of ordinary skill to seek out teachings such as Momose in order to practice the invention of Yoshihara. It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to consider utilizing the ultrasonic bonding technique from Momose since “ultrasonic welding can be performed at a normal temperature, in a short time and in the atmosphere, and high reliability in bonding portions can be secured” as taught by Momose in [0007].
Regarding Claim 8. Yoshihara discloses The semiconductor device according to claim 1.
Yoshihara does not disclose that the electrical connection between the P terminal and the first conductor includes at least one of bonding with solder, ultrasonic bonding, bonding by welding, bonding with wire, and bonding by sintering. Yoshihara describes only that the P terminal and the first conductor are bonded to one another ([0193], “the bonding portion 175b [of #P] is bonded to the first terminal bonding area 61 [also referred to as #23, see Figure 14]”).
However, Momose teaches a semiconductor device (Figure 1) comprising a plurality of terminals (#18 and #20, Figure 1, terminals) bonded to conductive plates (#14b, Figures 1 and 2, circuit patterns) for providing electrical connections to various semiconductor chips (#16, Figure 1, power semiconductor chips) located on the substrates (#14, Figure 1, insulating substrate), wherein the bonding between the terminals and the conductive plates is achieved via ultrasonic bonding (Figure 2, [0031], “in the state where external connection terminal 18, 20 is retained by a jig, bonding end portion 18c, 20a is moved down to abut against circuit pattern 14b of insulating substrate 14, and ultrasonic welding tool 24 is disposed on bonding end portion 18c, 20a . . . ultrasonic welding is performed.”).
Since Yoshihara is silent regarding the method utilized to bond the P terminal to the first conductor, this would motivate one of ordinary skill to seek out teachings such as Momose in order to practice the invention of Yoshihara. It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to consider utilizing the ultrasonic bonding technique from Momose since “ultrasonic welding can be performed at a normal temperature, in a short time and in the atmosphere, and high reliability in bonding portions can be secured” as taught by Momose in [0007].
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0256194 A1; Yoshihara et al.; 10/2012; (“Yoshihara”) as applied to claim 3 above, and further in view of US 9,129,932 B2; Hayashi et al.; 09/2015; (“Hayashi”).
Regarding Claim 4. Yoshihara discloses The semiconductor device according to claim 3.
Yoshihara does not disclose that the bonding between the O terminal and the second conductor includes at least one of bonding with solder, bonding with wire, and bonding with a sintering material.
However, Hayashi teaches a semiconductor device (Figure 8) comprising a plurality of output terminals (#OUT1 and #OUT2, Figure 8, output terminals) bonded to a conductor (#63, Figure 8, first conductor layer) for providing electrical connections to various semiconductor chips (#Di2 and #Tr2, Figure 8, switching and diode elements) located on the substrate (#4, Figure 8, frame portion), wherein the bonding between the output terminals and the conductor is achieved via bonding with a wire (Figure 8, column 17 line 60 through column 18 line 34, wires 72 and 73 are bonded to the output terminals #OUT1/2 and the first conductor layer #63 to provide electrical signals therebetween).
Since Yoshihara is silent regarding the method utilized to bond the O terminal to the second conductor, this would motivate one of ordinary skill to seek out teachings such as Hayashi in order to practice the invention of Yoshihara. It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to consider utilizing the bonding with a wire technique connecting terminals to conductive layers from Hayashi since doing so requires a reduced surface area for the wire bonds with narrow gaps therebetween and allows for an easy inspection of the quality of individual bonds through the use of imaging as taught by Hayashi in column 17 line 60 through column 18 line 34.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Parasitic Inductance Modeling and Reduction for a Wire Bonded Half Bridge SiC MOSFET Multichip Power Module; Zhang et al.; 05/2019 – Section III and Figures 9-11 detail alternative layouts for P, N, and O terminals to reduce parasitic inductance through mutual inductance cancellation by providing parallel opposing current paths (see Figure 10) and overlapping terminals (see Figure 11).
Parasitic Inductance Modeling and Reduction for Wire-Bonded Half-Bridge SiC Multichip Power Modules; Zhang et al.; 10/2020 – Section III and Figures 10-12 detail alternative layouts for P, N, and O terminals to reduce parasitic inductance through mutual inductance cancellation by providing parallel opposing current paths (see Figure 11) and overlapping terminals (see Figures 11 and 12).
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/TYLER J WIEGAND/Examiner, Art Unit 2812