DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This action is in reply to the Amendments/Response filed on February 6, 2026. No claims have been amended. No additional claims have been added. Claims 1-4 were previously cancelled. Claims 5-12 are currently pending and have been examined.
Response to Amendments
The examiner acknowledges no amendments were made in communications filed on February 6, 2026.
Response to Arguments
The applicant’s arguments, see pages 2-5, filed February 6, 2026 have been fully considered.
IDS: The examiner appreciates the applicant bringing attention to the translation provided for JP 3846706. Please see the updated IDS acknowledging the reference as considered.
103 Rejection: The applicant’s remarks and arguments have been fully considered but are not found persuasive.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The examiner’s notes that within the arguments presented, the applicant mentions all the references cited in their opening, however only addresses Torii within their arguments.
Page 3 of the applicant’s arguments presents that the outer-periphery polishing described in Torii would not include the notch portion, and further Torii would not include polishing the notch solely as Torrii aims to “improve the flatness of the part near the notch without changing the shape of the notch ([0066]).”
While Torii’s disclosure is mainly focused upon the main surface flatness on the double-sided wafer, that does not prevent other teachings driven by the desire to improve the quality of the wafers produced from being applicable and rendering the claims obvious in view of prior art. Both Torii and Morita are analogous to the claimed method by being in the same field of endeavor. That does not require that they be focused on the same problem as well. If there is an advantage to be gained from a teaching, then that provides the motivation for modification. In this case, Morita’s process, which includes a portion polishing of a notch to decrease micro-defects would be an advantage. As the process is a “polishing”, and not a chamfering or cutting step, it’s not considered to change the shape of the notch. The notch would remain intact, just the micro-inconsistencies on the surface of the bevel of the notch would be addressed.
While applicant provides the intent and advantages of the claimed method on pages 4-5, patentability is based upon the claims. So while Torii may not disclose the original purpose as stated within the applicant’s specification, Torii in view of the teaching references render the claims as presented as obvious.
Applicant remarks on page 5 that Tanimoto would not have led a skilled artisan to polish the notch at a higher rate and then a lower rate. The examiner maintains that the cited references do provide precedence for rough polishing (higher rate) followed by fine polishing (lower rate), in order to decrease micro deficiencies and improve wafer quality. The applicant’s arguments are not found persuasive and the rejection from the previous action is maintained.
Claim Interpretation
“a mirror-surface chamfering step of polishing the chamfered portion to form a mirror surface…wherein the mirror-surface chamfering step comprises… a first mirror-surface chamfering process… a second mirror-surface chamfering process…”: The term “chamfering step” is recognized as a phase/part of method that isn’t a discrete, single step, but composed two processes. The naming convention is atypical, but understood.
“a polishing rate…in the second mirror surface chamfering process is smaller than a polishing rate…in the first mirror-surface chamfering process”: Applicant’s specification provides means for understanding the relative term in paragraph [0052].
[0052]:… For example, all of the process time, the number of rotation of a polishing cloth, and the pressing pressure against the wafer are set to be smaller than those in the conditions of the first mirror-surface chamfering process.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5-12 are rejected under 35 U.S.C. 103 as being unpatentable over Torii (US PG Pub No. 20220097200) in view of Morita (US PG Pub No. 201960348270), Tanimoto et al. (US PG Pub No. 20200185215), Kozasa et al. (US PG Pub N0. 20170011903) and Kato (US Patent No. 8454852).
In regards to claim 5, Torii discloses
a method for manufacturing a semiconductor wafer, comprising:
[abstract]: A manufacturing method of a wafer with a notch includes: polishing principal surfaces of the wafer; mirror-polishing a notch chamfered portion of the notch; mirror-polishing an outer-periphery chamfered portion of an outer peripheral portion of the wafer; and finish-polishing one of principal surfaces of the wafer, the finish-polishing being performed after performing the mirror-polishing of the notch chamfered portion, the polishing of the principal surfaces, and the mirror-polishing of the outer-periphery chamfered portion in this order.
a chamfering step ([0025]) of grinding at least a periphery of a wafer having a wafer notch portion to form a chamfered portion having a wafer edge portion and the wafer notch portion;
[0025] Initially, wafers W each having a notch N as shown in FIG. 2 are prepared. An outer-periphery chamfered portion W.sub.C and a notch chamfered portion N.sub.C (see FIG. 4A) are provided on the outer peripheral portion and the notch N of each of the wafers W, respectively, through a primary chamfering step.
a double-side polishing step of polishing both major surfaces of the wafer;
[0042]…a double-side polishing step S2 of lapping the principal surfaces of the wafer W after being processed in the notch mirror-polishing step S1…
a mirror-surface chamfering step of polishing the chamfered portion to form a mirror surface; and
[0042] As shown in FIG. 7, the wafer manufacturing method includes a notch mirror-polishing step S1 of mirror-polishing the notch chamfered portion N.sub.C, a double-side polishing step S2 of lapping the principal surfaces of the wafer W after being processed in the notch mirror-polishing step S1, an outer-periphery mirror-polishing step S3 of mirror-polishing the outer-periphery chamfered portion We of the wafer W after being processed in the double-side polishing step S2, …
a polishing step of polishing at least one of both the major surfaces,
[0042…and a finish-polishing step S4 of finish-polishing the first principal surface W1 of the wafer W after being processed in the outer-periphery mirror-polishing step S3.
wherein the mirror-surface chamfering step comprises:
a first mirror-surface chamfering process of polishing the wafer notch portion in the chamfered portion before the double-side polishing step; and
[0042] As shown in FIG. 7, the wafer manufacturing method includes a notch mirror-polishing step S1 of mirror-polishing the notch chamfered portion N.sub.C, a double-side polishing step S2 of lapping the principal surfaces of the wafer W after being processed in the notch mirror-polishing step S1,
a second mirror-surface chamfering process of polishing the wafer notch portion and the wafer edge portion after the double-side polishing step, and
[0042]:…an outer-periphery mirror-polishing step S3 of mirror-polishing the outer-periphery chamfered portion We of the wafer W after being processed in the double-side polishing step S2, …
Torrii fails to explicitly disclose that the second mirror-surface chamfering process involves a notch portion polishing. A skilled artisan would recognize that as the notch is part of the periphery, it would be polished as the whole periphery is polished.
However, Morita is explicit in teaching a notch and chamfer/bevel polishing in its peripheral grinding step:
[0073] Subsequently, the beveled portion on the periphery of the silicon wafer is subjected to polishing. First, the beveled portion of the notch portion is subjected to polishing. This polishing is performed by pressing a urethane buff shaped like a disk with an end having a tapered shape against the beveled portion of the notch portion while rotating the buff. Note that the polishing on the beveled portion of the notch portion may be polishing by pressing rotating polishing tape against the notch portion.
[0075] In a similar manner, polishing is performed on the beveled portion on the periphery other than the beveled portion of the notch portion.
Torrii and Morita are analogous to the claimed invention as they are in the same field of endeavor, double sided polishing of silicon wafers. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Torrii in view of the teachings of Morita, and include polishing the notch within the second mirror-surface process polishing step, ensuring step-forming microdefects being within an allowed required, providing a good quality of wafer surface (Morita [0014]).
Torrii fails to disclose that polishing rates between the first and second mirror-surface chamfering processes varies, such that “a polishing rate of the wafer notch portion in the second mirror-surface chamfering process is smaller than a polishing rate of the wafer notch portion in the first mirror-surface chamfering process.” Tanimoto discloses varying polishing rates:
[0040] The first polishing step in this embodiment is performed with a view to removing a natural oxide layer having a thickness of around 5 angstrom to 20 angstrom formed on a surface layer of each silicon wafer W and polishing the silicon wafer W to a substantial target thickness, using a polishing agent containing abrasive grains.
[0041] The total polishing amount of the first and second polishing steps is set within a range of roughly 2.5 μm to 10 μm for each surface. In the first polishing step, the double-side polishing is performed to achieve a polishing amount of 80% to 99.5% with respect to the total polishing amount of the first and second polishing steps…
[0042] On the other hand, the second polishing step in this embodiment is performed with a view to reducing the roll off amount of the peripheral portion of the wafer by slightly polishing both surfaces of the silicon wafers W using a polishing agent containing a water-soluble polymer with no abrasive grains…
[0048] The polishing rate in the first polishing step is preferably 0.1 μm/min to 1.0 μm/min, and the polishing rate in the second polishing step is preferably 0.03 μm/min to 0.5 μm/min.
Torrii and Tanimoto are analogous to the claimed invention as they are in the same field of endeavor, double sided polishing of silicon wafers. Tanimoto teaches providing a two step process of rough polishing (performing up to 99.5% of the total polishing during the first step) and fine polishing (the remaining) for a substrate surface wherein obtaining a mirror-surface is the desired outcome.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Torrii in view of the teachings of Tanimoto, and provide Torrii with a first polishing process of the notch with a higher polishing rate than the second polishing process of the notch, in order to prevent “the formation of micro scratches ([0009])” on the surfaces being polished during operation.
Torri fails to disclose explicitly that the final major surface polishing step is a “mirror-surface” polishing step. Torrii discloses a “finish” polishing step.
Kozasa which discloses a mirror finishing polishing process.
[0002] Typically, top and bottom sides of a semiconductor wafer are subjected to a plurality of stages of mirror-polishing. Specifically, the mirror-polishing is roughly divided into a rough polishing for enhancing the flatness of the semiconductor wafer, and a finish polishing for reducing the surface roughness of the semiconductor wafer.
[0003] Further, the mirror-polishing is not only applied to the top and bottom sides of the semiconductor wafer, but also to a chamfered portion of the semiconductor wafer in order to prevent a generation of dust from the chamfered portion.
Kato, also a wafer producing apparatus and method, discloses the end goal for these processes is to manufacture mirror surfaced silicon wafers:
Col. 2 lines 35-48: as shown in FIG. 4(A), it is common to sequentially perform a slicing process for cutting a thin wafer from a single crystal ingot, a chamfering process for preventing a break of the outer edge of the wafer, a lapping process or a double-side grinding process for eliminating variations in the thickness of the wafer, an etching process for removing mechanical damage or contamination introduced by the chamfering, lapping, or grinding, and a mirror polishing process for polishing the chamfered portion and the principal surface or both surfaces of the wafer to a mirror surface. In particular, in order to achieve a rigorous precision of the chamfered shape, chamfering processing is performed again after lapping or grinding of the front and back surfaces.
Torrii, Kato, and Kozasa are analogous to the claimed invention as they are in the same field of endeavor, double sided polishing of silicon wafers.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Torrii in view of the teachings of Kato and Kozasa, and have the final step of polishing being a mirror-surface polishing step of the major surfaces, in order to provide a finished product of high quality.
In regards to claim 6, Torii as modified discloses
the method for manufacturing a semiconductor wafer according to claim 5, wherein the semiconductor wafer is a silicon wafer ([0009]).
[0009] In the manufacturing method of a wafer according to the above aspect of the invention, it is preferable that the wafer is a silicon wafer.
In regards to claim 7, Torii as modified discloses
the method for manufacturing a semiconductor wafer according to claim 5, wherein in polishing the wafer notch portion in the first and second mirror-surface chamfering processes,
the polishing is performed by inserting a circular polishing cloth (disc shaped notch polishing wheel 20 with polishing pad 21 provided all over outer periphery; [0030]; fig. 4A-4B) into the wafer notch portion perpendicular to a wafer surface (see fig. 4A/4B - ann. 1).
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In regards to claim 8, Torii as modified discloses
the method for manufacturing a semiconductor wafer according to claim 6, wherein in polishing the wafer notch portion in the first and second mirror-surface chamfering processes,
the polishing is performed by inserting a circular polishing cloth (disc shaped notch polishing wheel 20 with polishing pad 21 provided all over outer periphery; [0030]; fig. 4A-4B) into the wafer notch portion perpendicular to a wafer surface (see fig. 4A/4B - ann. 1).
In regards to claim 9, Torii as modified discloses
the method for manufacturing a semiconductor wafer according to claim 5, wherein an end surface of the wafer notch portion has (see fig. 4B - ann. 1):
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a first slope continued from one major surface of the wafer and inclined from the one major surface ([0031]: a rounded surface r1 at the border region between the notch chamfered portion N.sub.C and each of the first principal surface W1 and the second principal surface W2);
a second slope continued form the other major surface of the wafer and included from the other major surface ([0031]: a rounded surface r1 at the border region between the notch chamfered portion N.sub.C and each of the first principal surface W1 and the second principal surface W2); and
an end portion constituting an outermost periphery of the wafer (end portion N1, see fig. 4b - ann. 1), and in the second mirror-surface chamfering process, all of the first slope, the second slope, and the end portion of the end surface of the wafer notch portion are polished ([0029-0031]).
[0029] Next, the notch chamfered portion N.sub.C of the wafer W is mirror-polished using a notch polishing unit 2 as shown in FIGS. 4A and 4B.
[0031] At the time of the notch mirror-polishing, since the polishing pad 21 is made of a soft unwoven cloth and the wafer W is inclined during the mirror-polishing, the polishing process progresses while the polishing pad 21 extends not only over an end portion N1 and the notch chamfered portion N.sub.C of the notch N but also over the first principal surface W1 and the second principal surface W2 of the wafer W (sometimes referred to as “over polishing” hereinafter). When such an over polishing occurs, the end portion N1 and the notch chamfered portion N.sub.C of the notch N are mirror-polished as shown in a central figure in FIG. 3A, creating a rounded surface r1 at the border region between the notch chamfered portion N.sub.C and each of the first principal surface W1 and the second principal surface W2…
In regards to claim 10, Torii as modified discloses
the method for manufacturing a semiconductor wafer according to claim 6, wherein an end surface of the wafer notch portion has (see fig. 4B - ann. 1):
a first slope continued from one major surface of the wafer and inclined from the one major surface ([0031]: a rounded surface r1 at the border region between the notch chamfered portion N.sub.C and each of the first principal surface W1 and the second principal surface W2);
a second slope continued form the other major surface of the wafer and included from the other major surface ([0031]: a rounded surface r1 at the border region between the notch chamfered portion N.sub.C and each of the first principal surface W1 and the second principal surface W2); and
an end portion constituting an outermost periphery of the wafer (end portion N1, see fig. 4b - ann. 1), and in the second mirror-surface chamfering process, all of the first slope, the second slope, and the end portion of the end surface of the wafer notch portion are polished ([0029-0031]).
In regards to claim 11, Torii as modified discloses
the method for manufacturing a semiconductor wafer according to claim 7, wherein an end surface of the wafer notch portion has (see fig. 4B - ann. 1):
a first slope continued from one major surface of the wafer and inclined from the one major surface ([0031]: a rounded surface r1 at the border region between the notch chamfered portion N.sub.C and each of the first principal surface W1 and the second principal surface W2);
a second slope continued form the other major surface of the wafer and included from the other major surface ([0031]: a rounded surface r1 at the border region between the notch chamfered portion N.sub.C and each of the first principal surface W1 and the second principal surface W2); and
an end portion constituting an outermost periphery of the wafer (end portion N1, see fig. 4b - ann. 1), and in the second mirror-surface chamfering process, all of the first slope, the second slope, and the end portion of the end surface of the wafer notch portion are polished ([0029-0031]).
In regards to claim 12, Torii as modified discloses
the method for manufacturing a semiconductor wafer according to claim 8, wherein an end surface of the wafer notch portion has (see fig. 4B - ann. 1):
a first slope continued from one major surface of the wafer and inclined from the one major surface ([0031]: a rounded surface r1 at the border region between the notch chamfered portion N.sub.C and each of the first principal surface W1 and the second principal surface W2);
a second slope continued form the other major surface of the wafer and included from the other major surface ([0031]: a rounded surface r1 at the border region between the notch chamfered portion N.sub.C and each of the first principal surface W1 and the second principal surface W2); and
an end portion constituting an outermost periphery of the wafer (end portion N1, see fig. 4b - ann. 1), and in the second mirror-surface chamfering process, all of the first slope, the second slope, and the end portion of the end surface of the wafer notch portion are polished ([0029-0031]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON KHALIL HAWKINS whose telephone number is (571)272-5446. The examiner can normally be reached M-F; 8-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brian Keller can be reached at (571) 272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON KHALIL HAWKINS/Examiner, Art Unit 3723
/BRIAN D KELLER/Supervisory Patent Examiner, Art Unit 3723