DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This action is in reply to the Amendments/Response filed on April 24/2026. No claims have been amended. No additional claims have been added. Claims 5-12 are currently pending and have been examined.
Response to Amendments
The examiner fully acknowledges there were no amendments to claims in communcations filed on April 24/2026.
Response to Arguments
The applicant’s arguments, see pages 2-4, filed April 24/2026 have been fully considered.
102 rejections: The examiner finds that the arguments presented by the applicant to be persuasive, regarding the 103 rejection of record of claim 5, which applied Torii (US PG Pub No. 20200185215) in view of Morita (201960348270), Tanimoto (20200185215), Kozasa (20170011903) and Kato (US Patent No. 8454852). Specifically regarding the reference of Torri, the applicant remarked that Torri's paragraphs [0032-0036], in their description of the double sided polishing process, specifically state that the notch is not polished ([0036]) in order to maintain the desired notch profile. So while Moritia describes a step of polishing the beveled notch portion of a wafer, Torri's process is intentional in not polishing the notch in order to maintain a specific profile. As such, the previous rejection is considered improper, and finality revoked.
Upon further consideration, Morita is considered to disclose the method steps described in the claims. Please see the updated rejection set forth within the action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Morita (201960348270), Tanimoto (20200185215), Kozasa (20170011903) and Kato (US Patent No. 8454852).
In regards to claim 5, Morita discloses
a method for manufacturing a semiconductor wafer (abstract), comprising:
Abstract: Provided are a method of polishing a silicon wafer and a method of producing a silicon wafer which can reduce the formation of step-forming microdefects on a silicon wafer.
a chamfering step of grinding at least a periphery of a wafer having a wafer notch portion to form a chamfered portion having a wafer edge portion and the wafer notch portion;
[0005] The beveling adjusts the shape of a peripheral end portion of the silicon wafer to a predetermined shape using a beveling apparatus. This beveling is also performed on the notch portion.
[0066] …a peripheral end of the silicon wafer is subjected to a primary beveling procedure (rough beveling)... In this manner, the periphery of the silicon wafer is worked into a predetermined rounded shape.
a double-side polishing step of polishing both major surfaces of the wafer;
[0067] After that, the main surfaces of the silicon wafer are subjected to a primary planarization procedure. In the primary planarization procedure, the silicon wafer is placed between a pair of lapping plates parallel to each other, and while lapping liquid which is for example a mixture of abrasive grains of alumina or the like, a dispersant, and water is supplied between the lapping plates, the plates are rotated and slid under a predetermined pressure.
a mirror-surface chamfering step ([0068], [0073] and [0075]) of polishing the chamfered portion to form a mirror surface; and
a mirror polishing step of mirror polishing at least one of both the major surfaces,
[0072] After that, the front surface and the back surface of the silicon wafer are subjected to double-side polishing using a double-side polishing apparatus. The double-side polishing is performed by fitting the silicon wafer into an opening of a carrier plate; then holding the carrier plate between an upper plate and a lower plate to each of which a polishing cloth is attached; flowing a slurry, in which for example abrasive grains of colloidal silica or the like are contained in an alkali solution, into the space between the upper and lower and plates and the wafer; and rotating the upper and lower plates and the carrier plate in opposite directions. Thus, irregularities on the surfaces of the wafer can be reduced, so that a high flatness wafer can be obtained.
wherein the mirror-surface chamfering step ([0068], [0073] and [0075]) comprises:
a first mirror-surface chamfering process ([0068]) of polishing the wafer notch portion in the chamfered portion before the double-side polishing step; and
[0068] Next, the notch portion of the silicon wafer having been subjected to the primary planarization procedure is subjected to beveling. Specifically, for example, a metal-bonded or resin-bonded grindstone is pressed against the notch portion of the silicon wafer while being rotated, and the grindstone is moved along the contour of the notch portion, thereby performing beveling on the notch portion of the silicon wafer. The beveled notch portion may be further subjected to known tape beveling.
a second mirror-surface chamfering process ([0073] and [0075]) of polishing the wafer notch portion and the wafer edge portion after the double-side polishing step, and
[0073] Subsequently, the beveled portion on the periphery of the silicon wafer is subjected to polishing. First, the beveled portion of the notch portion is subjected to polishing. This polishing is performed by pressing a urethane buff shaped like a disk with an end having a tapered shape against the beveled portion of the notch portion while rotating the buff. Note that the polishing on the beveled portion of the notch portion may be polishing by pressing rotating polishing tape against the notch portion.
[0075] In a similar manner, polishing is performed on the beveled portion on the periphery other than the beveled portion of the notch portion. For example, the silicon wafer is rotated with the back surface of the wafer being held by a suction stage, and a polishing buff made of for example urethane is pressed against the peripheral end portion of the rotating wafer, thereby mirror-finishing the beveled portion on the periphery of the silicon wafer.
Morita fails to disclose that polishing rates between the first and second mirror-surface chamfering processes varies, such that “a polishing rate of the wafer notch portion in the second mirror-surface chamfering process is smaller than a polishing rate of the wafer notch portion in the first mirror-surface chamfering process.” Tanimoto discloses varying polishing rates:
[0040] The first polishing step in this embodiment is performed with a view to removing a natural oxide layer having a thickness of around 5 angstrom to 20 angstrom formed on a surface layer of each silicon wafer W and polishing the silicon wafer W to a substantial target thickness, using a polishing agent containing abrasive grains.
[0041] The total polishing amount of the first and second polishing steps is set within a range of roughly 2.5 μm to 10 μm for each surface. In the first polishing step, the double-side polishing is performed to achieve a polishing amount of 80% to 99.5% with respect to the total polishing amount of the first and second polishing steps…
[0042] On the other hand, the second polishing step in this embodiment is performed with a view to reducing the roll off amount of the peripheral portion of the wafer by slightly polishing both surfaces of the silicon wafers W using a polishing agent containing a water-soluble polymer with no abrasive grains…
[0048] The polishing rate in the first polishing step is preferably 0.1 μm/min to 1.0 μm/min, and the polishing rate in the second polishing step is preferably 0.03 μm/min to 0.5 μm/min.
Morita and Tanimoto are analogous to the claimed invention as they are in the same field of endeavor, double sided polishing of silicon wafers. Tanimoto teaches providing a two step process of rough polishing (performing up to 99.5% of the total polishing during the first step) and fine polishing (the remaining) for a substrate surface wherein obtaining a mirror-surface is the desired outcome.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morita in view of the teachings of Tanimoto, and provide Morita with a first polishing process of the notch with a higher polishing rate than the second polishing process of the notch, in order to prevent “the formation of micro scratches ([0009])” on the surfaces being polished during operation.
Torri fails to disclose explicitly that the final major surface polishing step is a “mirror-surface” polishing step. Morita discloses a “finish” polishing step.
Kozasa which discloses a mirror finishing polishing process.
[0002] Typically, top and bottom sides of a semiconductor wafer are subjected to a plurality of stages of mirror-polishing. Specifically, the mirror-polishing is roughly divided into a rough polishing for enhancing the flatness of the semiconductor wafer, and a finish polishing for reducing the surface roughness of the semiconductor wafer.
[0003] Further, the mirror-polishing is not only applied to the top and bottom sides of the semiconductor wafer, but also to a chamfered portion of the semiconductor wafer in order to prevent a generation of dust from the chamfered portion.
Kato, also a wafer producing apparatus and method, discloses the end goal for these processes is to manufacture mirror surfaced silicon wafers:
Col. 2 lines 35-48: as shown in FIG. 4(A), it is common to sequentially perform a slicing process for cutting a thin wafer from a single crystal ingot, a chamfering process for preventing a break of the outer edge of the wafer, a lapping process or a double-side grinding process for eliminating variations in the thickness of the wafer, an etching process for removing mechanical damage or contamination introduced by the chamfering, lapping, or grinding, and a mirror polishing process for polishing the chamfered portion and the principal surface or both surfaces of the wafer to a mirror surface. In particular, in order to achieve a rigorous precision of the chamfered shape, chamfering processing is performed again after lapping or grinding of the front and back surfaces.
Morita, Kato, and Kozasa are analogous to the claimed invention as they are in the same field of endeavor, double sided polishing of silicon wafers.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morita in view of the teachings of Kato and Kozasa, and have the final step of polishing being a mirror-surface polishing step of the major surfaces, in order to provide a finished product of high quality.
In regards to claim 6, Morita as modified discloses
the method for manufacturing a semiconductor wafer according to claim 5, wherein the semiconductor wafer is a silicon wafer (abastract).
In regards to claim 7, Morita as modified discloses
the method for manufacturing a semiconductor wafer according to claim 5, wherein in polishing the wafer notch portion in the first and second mirror-surface chamfering processes, the polishing is performed by inserting a circular polishing cloth into the wafer notch portion perpendicular to a wafer surface ([0042]).
[0042] First, the notch portion polishing step of performing polishing on the beveled portion of the notch portion is performed. Specifically, as illustrated in FIG. 2A, a polishing pad II with a small diameter is rotated. A slurry S is then supplied to a beveled portion of a notch portion N of a silicon wafer W from a slurry supply means 12, and the notch portion N is pressed against the polishing pad 11 while changing the angle of the silicon wafer W. Thus, the beveled portion of the notch portion N is mirror-finished.
PNG
media_image1.png
247
527
media_image1.png
Greyscale
In regards to claim 8, Morita as modified discloses
the method for manufacturing a semiconductor wafer according to claim 6, wherein in polishing the wafer notch portion in the first and second mirror-surface chamfering processes, the polishing is performed by inserting a circular polishing cloth into the wafer notch portion perpendicular to a wafer surface ([0042]).
Claim(s) 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Morita in view of Tanimoto, Kozasa and Kato as applied to claim 1 above, and further in view of Tori (US PG Pub No. .
In regards to claim 9, Morita as modified discloses
the method for manufacturing a semiconductor wafer according to claim 5, but fails to provide great detail of an end surface of the wafer notch portion.
However, Torii, which also discloses a method for mirror finishing a wafer with a notch. Torri discloses the structure of the wafer resultant of the polishing process:
an end surface of the wafer notch portion has (see fig. 4B - ann. 1):
PNG
media_image2.png
299
953
media_image2.png
Greyscale
a first slope continued from one major surface of the wafer and inclined from the one major surface ([0031]: a rounded surface r1 at the border region between the notch chamfered portion N.sub.C and each of the first principal surface W1 and the second principal surface W2);
a second slope continued form the other major surface of the wafer and included from the other major surface ([0031]: a rounded surface r1 at the border region between the notch chamfered portion N.sub.C and each of the first principal surface W1 and the second principal surface W2); and
an end portion constituting an outermost periphery of the wafer (end portion N1, see fig. 4b - ann. 1), and in the second mirror-surface chamfering process, all of the first slope, the second slope, and the end portion of the end surface of the wafer notch portion are polished ([0029-0031]).
[0029] Next, the notch chamfered portion N.sub.C of the wafer W is mirror-polished using a notch polishing unit 2 as shown in FIGS. 4A and 4B.
[0031] At the time of the notch mirror-polishing, since the polishing pad 21 is made of a soft unwoven cloth and the wafer W is inclined during the mirror-polishing, the polishing process progresses while the polishing pad 21 extends not only over an end portion N1 and the notch chamfered portion N.sub.C of the notch N but also over the first principal surface W1 and the second principal surface W2 of the wafer W (sometimes referred to as “over polishing” hereinafter). When such an over polishing occurs, the end portion N1 and the notch chamfered portion N.sub.C of the notch N are mirror-polished as shown in a central figure in FIG. 3A, creating a rounded surface r1 at the border region between the notch chamfered portion N.sub.C and each of the first principal surface W1 and the second principal surface W2…
Torri and Morita are analogous to the claimed invention as they are in the same field of polishing silicon wafers that are chamfered and beveled.
Therefore, it would be obvious to a person of ordinary skill in the art to recognize that a wafer polished using the steps described by Morita as modified would result in the claimed profile of the produced wafer notch, detailed by Torri.
Claims 10-12 recite the same limitations as claim 9, but depend upon claims 6, 7, and 8 respectively. As such, they are similarly rejected by Morita as modified in further view of Torri.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON KHALIL HAWKINS whose telephone number is (571)272-5446. The examiner can normally be reached M-F; 8-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brian Keller can be reached at (571) 272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON KHALIL HAWKINS/Examiner, Art Unit 3723
Prosecution Insights