Prosecution Insights
Last updated: July 15, 2026
Application No. 18/283,079

Semiconductor Device And Electronic Apparatus

Final Rejection §102§103
Filed
Sep 20, 2023
Priority
Mar 25, 2021 — JP 2021-051402 +2 more
Examiner
WHALEN, DANIEL B
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Energy Laboratory Co., Ltd.
OA Round
2 (Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
813 granted / 1014 resolved
+12.2% vs TC avg
Strong +16% interview lift
Without
With
+15.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
40 currently pending
Career history
1060
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
73.4%
+33.4% vs TC avg
§102
15.9%
-24.1% vs TC avg
§112
7.8%
-32.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1014 resolved cases

Office Action

§102 §103
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 3-7, and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ikeda et al. (US 2020/0127064 A1; hereinafter “Ikeda”). Regarding claim 1, Ikeda teaches a semiconductor device (an imaging display device 110) comprising: an imaging unit (an imaging portion 101 of an imaging display device 110); and a display unit (a display portion 102 of 110) (Figs. 1 and 4A and paragraphs 53-59 and 80), wherein the imaging unit comprises a plurality of photoelectric conversion elements arranged in a matrix (photoelectric conversion elements of pixels arranged in a matrix), wherein the display unit comprises a plurality of display pixel circuits arranged in a matrix (display pixel circuits of pixels arranged in a matrix) and a plurality of display elements arranged in a matrix (display elements of pixels arranged in a matrix) (Figs. 4A, 4C, 6A, and 23A and paragraphs 80-90, 103, and 346-347), wherein the plurality of photoelectric conversion elements are provided in a first layer (111) (Figs. 4A and 23A and paragraphs 347-350), wherein the plurality of display pixel circuits are provided in a second layer (112) over the first layer (Figs. 23A and 25A and paragraph 362), wherein the plurality of display elements are provided in a third layer (113) over the second layer (Figs. 23A and paragraph 363), wherein one of the plurality of display pixel circuits is electrically connected to one of the plurality of display elements (Figs. 6A and 23A and paragraphs 86-90 and 347, 162b is connected to 163), and wherein the semiconductor device is configured to supply imaging data of all columns to the display unit row by row, the imaging data obtained using the plurality of photoelectric conversion elements (transmitting analog image data obtained from the imaging portion 101 having the photoelectric conversion elements of the pixels with columns connected to a circuit 152b functioning a column driver for the imaging portion 101 to the display portion 102 having the display elements of pixels with rows connected to a circuit 155b functioning as a row driver for the display portion 102 without being converted into digital data, and display is performed, wherein the pixels in the imaging portion 101 are each electrically connected to corresponding pixels in the display portion 102 with one-to-one correspondence) (Figs. 1, 4A, 6A, and 7A and paragraphs 56-59 and 80-93). Regarding claim 3, Ikeda teaches wherein the semiconductor device is configured to adjust a voltage of the imaging data and supplying the imaging data to the display unit (Fig. 8A and paragraphs 117-138). Regarding claim 4, Ikeda teaches wherein the display pixel circuit is configured to control emission luminance of the display element (Figs. 8A and 23A and paragraphs 117-138 and paragraphs 368-369). Regarding claim 5, Ikeda teaches wherein the display element is an organic EL element (paragraphs 363-364). Regarding claim 6, Ikeda teaches wherein the display pixel circuit comprises a transistor comprising an oxide semiconductor (Fig. 25A and paragraphs 4 and 362). Regarding claim 7, Ikeda teaches wherein the first layer and the second layer are connected to each other by an adhesive layer (361-362) and a bump (353-354) (Fig. 23A and paragraph 351-359). Regarding claim 9, Ikeda teaches an electronic apparatus comprising: the semiconductor device according to claim 1, and at least one of a mounting unit, a lens, a main body (a main body 901), and a cable, wherein the electronic apparatus is configured to obtain user information through the lens (Fig. 27A and paragraphs 440-441). Regarding claim 10, Ikeda teaches the display pixel circuit further comprising: a first transistor (52/53); and a capacitor (60), wherein one electrode of the capacitor, one of a source and a drain of the first transistor, and one electrode of the display element (11 or 102a as a circuit portion 102a of the display portion 102) are electrically connected to one another (Figs. 6A and 8A and paragraphs 86-87 and 117-118), and wherein the first transistor comprises an oxide semiconductor (paragraph 128). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ikeda. Regarding claim 8, Ikeda teaches an electronic apparatus comprising: the semiconductor device according to claim 1 (Fig. 27A and paragraphs 440-441). While Ikeda does not explicitly teach that the electronic apparatus further comprises at least one of an antenna, a battery, and a microphone, it would have been obvious to one of ordinary skill in the art to include at least one of the antenna, the battery, and the microphone as claimed such as the battery in order to provide the portable electrical power to the various electronic apparatus. Response to Arguments Applicant’s arguments with respect to amended and newly submitted claims have been considered but are moot in view of new grounds of rejections as set forth above in this Office Action. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL WHALEN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Sep 20, 2023
Application Filed
Nov 24, 2025
Non-Final Rejection mailed — §102, §103
Feb 23, 2026
Response Filed
Apr 14, 2026
Final Rejection mailed — §102, §103
Jul 13, 2026
Request for Continued Examination
Jul 14, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685182
METHOD FOR MANUFACTURING PACKAGE STRUCTURE
2y 10m to grant Granted Jul 14, 2026
Patent 12677548
DISPLAY PANEL COMPRISING REPAIR TRANSISTOR AND REPAIR ELECTRODE AND DISPLAY DEVICE THEREOF
3y 1m to grant Granted Jul 07, 2026
Patent 12663671
DISPLAY DEVICE COMPRISING COVER WINDOW INCLUDING DENSITY CONTROL AREA
3y 8m to grant Granted Jun 23, 2026
Patent 12666852
DISPLAY DEVICE HAVING IMPROVED HEAT RADIATING PERFORMANCE
3y 3m to grant Granted Jun 23, 2026
Patent 12628513
FLEXIBLE DISPLAY PANEL INCLUDING ISLAND STRUCTURES CONNECTED AND STRETCHED THROUGH ELECTRICAL CONNECTING STRUCTURES, MANUFACTURING METHOD THEREOF, AND DISPLAY TERMINAL
3y 10m to grant Granted May 12, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
96%
With Interview (+15.8%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1014 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month