DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE AND ELELECTRONIC APPARATUS COMPRISNG STACKED-LAYER STRUCTURE OF IMAGING UNIT AND DISPLAY UNIT
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ikeda et al. (US 2020/0127064 A1; hereinafter “Ikeda”).
Regarding claim 1, Ikeda teaches a semiconductor device (an imaging display device 110) comprising: an imaging unit (an imaging portion of 110); and a display unit (a display portion of 110) (Figs. 1 and 4A and paragraphs 53-59 and 80), wherein the imaging unit comprises a plurality of photoelectric conversion elements arranged in a matrix (photoelectric conversion elements of pixels arranged in a matrix), wherein the display unit comprises a plurality of display pixel circuits arranged in a matrix (display pixel circuits of pixels arranged in a matrix) and a plurality of display elements arranged in a matrix (display elements of pixels arranged in a matrix) (Figs. 4A, 4C, 6A, and 23A and paragraphs 80-90, 103, and 346-347), wherein the plurality of photoelectric conversion elements are provided in a first layer (111) (Figs. 4A and 23A and paragraphs 347-350), wherein the plurality of display pixel circuits are provided in a second layer (112) over the first layer (Figs. 23A and 25A and paragraph 362), wherein the plurality of display elements are provided in a third layer (113) over the second layer (Figs. 23A and paragraph 363), and wherein one of the plurality of display pixel circuits is electrically connected to one of the plurality of display elements (Figs. 6A and 23A and paragraphs 86-90 and 347, 162b is connected to 163).
Regarding claim 2, Ikeda teaches wherein the semiconductor device is configured to obtain imaging data using the plurality of photoelectric conversion elements (), and wherein the semiconductor device is configured to supply the imaging data of all columns to the display unit row by row (Figs. 4A, 4C, 6A and 7A and paragraphs 80-93).
Regarding claim 3, Ikeda teaches wherein the semiconductor device is configured to adjust a voltage of the imaging data and supplying the imaging data to the display unit (Fig. 8A and paragraphs 117-138).
Regarding claim 4, Ikeda teaches wherein the display pixel circuit is configured to control emission luminance of the display element (Figs. 8A and 23A and paragraphs 117-138 and paragraphs 368-369).
Regarding claim 5, Ikeda teaches wherein the display element is an organic EL element (paragraphs 363-364).
Regarding claim 6, Ikeda teaches wherein the display pixel circuit comprises a transistor comprising an oxide semiconductor (Fig. 25A and paragraphs 4 and 362).
Regarding claim 7, Ikeda teaches wherein the first layer and the second layer are connected to each other by an adhesive layer (361-362) and a bump (353-354) (Fig. 23A and paragraph 351-359).
Regarding claim 9, Ikeda teaches an electronic apparatus comprising: the semiconductor device according to claim 1, and at least one of a mounting unit, a lens, a main body (a main body 901), and a cable, wherein the electronic apparatus is configured to obtain user information through the lens (Fig. 27A and paragraphs 440-441).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ikeda.
Regarding claim 8, Ikeda teaches an electronic apparatus comprising: the semiconductor device according to claim 1 (Fig. 27A and paragraphs 440-441). While Ikeda does not explicitly teach that the electronic apparatus further comprises at least one of an antenna, a battery, and a microphone, it would have been obvious to one of ordinary skill in the art to include at least one of the antenna, the battery, and the microphone as claimed such as the battery in order to provide the portable electrical power to the various electronic apparatus.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893