DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/13/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda et al. (US 2020/0127064 A1; hereinafter “Ikeda”) in view of Yang et al. (US 2021/0183914 A1; hereinafter “Yang”).
Regarding claim 1, Ikeda teaches a semiconductor device (an imaging display device 100/110) comprising:
an imaging unit (an imaging portion 101 of an imaging display device 110); and a display unit (a display portion 102 of 110) (Figs. 1 and 4A and paragraphs 53-59 and 80), the imaging unit comprising a plurality of photoelectric conversion elements arranged in a matrix (photoelectric conversion elements 161 of pixels arranged in a matrix), the display unit comprising a plurality of display pixel circuits arranged in a matrix (display pixel circuits 162 of the pixels arranged in a matrix) each comprising a first transistor and a capacitor (each of the display pixel circuits 162 can be represented by a pixel circuit 171 comprising a transistor 53 and a capacitor 60); and a plurality of display elements arranged in a matrix (display elements 163 of the pixels arranged in a matrix) (Figs. 4A, 4C, 6A, 8A, and 23A and paragraphs 80-90, 103, 116-118, and 346-347),
wherein the plurality of photoelectric conversion elements are provided in a first layer (111) (Figs. 4A and 23A and paragraphs 347-350), wherein the plurality of display pixel circuits are provided in a second layer (112) over the first layer (Figs. 23A and 25A and paragraph 362), wherein the plurality of display elements are provided in a third layer (113) over the second layer (Figs. 23A and paragraph 363), wherein one of the plurality of display pixel circuits is electrically connected to one of the plurality of display elements (Figs. 6A and 23A and paragraphs 86-90 and 347, 162b is connected to 163), wherein the semiconductor device is configured to supply imaging data of all columns to the display unit row by row, the imaging data obtained using the plurality of photoelectric conversion elements (transmitting analog image data obtained from the imaging portion 101 having the photoelectric conversion elements of the pixels with columns connected to a circuit 152b functioning a column driver for the imaging portion 101 to the display portion 102 having the display elements of pixels with rows connected to a circuit 155b functioning as a row driver for the display portion 102 without being converted into digital data, and display is performed, wherein the pixels in the imaging portion 101 are each electrically connected to corresponding pixels in the display portion 102 with one-to-one correspondence) (Figs. 1, 4A, 6A, and 7A and paragraphs 56-59 and 80-93),
wherein a gate of the first transistor is electrically connected to one electrode of the capacitor through a first node (a gate of 53 is electrically connected to one electrode of 60 through ND) (Fig. 8A and paragraphs 116-118).
Ikeda does not further teaches that the other electrode of the capacitor, one of a source and a drain of the first transistor, and one electrode of the display element are electrically connected to one another through a second node since Ikeda teaching the pixel circuit 171 as one pixel circuit example does not further teach such display pixel circuit configuration as claimed. Nevertheless, it is well known in the art to provide various display pixel circuit configuration involving at least one transistor and one capacitor in addition to the display element as a single display pixel circuit, including the claimed configuration that the capacitor is connected to the gate of the transistor and the source/drain of the transistor along with the anode/cathode of the display element for obtaining the desired single pixel configuration and obtaining the desired display image output. This is evidenced by Yang teaching a display device comprising: a plurality of display pixel circuits arranged in a matrix (a display panel 110 including pixels P in a matrix) each comprising a first transistor and a capacitor (each pixel P comprising a transistor TR2 and a capacitor C1) (Figs. 1-2 and paragraphs 61-72), wherein a gate of the first transistor is electrically connected to one electrode of the capacitor through a first node (a gate of TR2 is connected to one electrode of C1 at a first node therebetween as shown in Fig. 2), and wherein the other electrode of the capacitor, one of a source and a drain of the first transistor, and one electrode of the display element are electrically connected to one another through a second node (the other electrode of C1, a source/drain of TR2, and one electrode of a display device 710 are electrically connected to one another through a second node therebetween as shown in Fig. 2). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Ikeda with that of Yang for obtaining the desired single pixel configuration and obtaining the desired display image output.
Regarding claim 3, Ikeda teaches wherein the semiconductor device is configured to adjust a voltage of the imaging data and supplying the imaging data to the display unit (Fig. 8A and paragraphs 117-138).
Regarding claim 4, Ikeda teaches wherein the display pixel circuit is configured to control emission luminance of the display element (Figs. 8A and 23A and paragraphs 117-138 and paragraphs 368-369).
Regarding claim 5, Ikeda teaches wherein the display element is an organic EL element (paragraphs 363-364).
Regarding claim 6, Ikeda teaches wherein the display pixel circuit comprises a transistor comprising an oxide semiconductor (Fig. 25A and paragraphs 4 and 362).
Regarding claim 7, Ikeda teaches wherein the first layer and the second layer are connected to each other by an adhesive layer (361-362) and a bump (353-354) (Fig. 23A and paragraph 351-359).
Regarding claim 8, Ikeda teaches an electronic apparatus comprising: the semiconductor device according to claim 1 (Fig. 27A and paragraphs 440-441). While Ikeda does not explicitly teach that the electronic apparatus further comprises at least one of an antenna, a battery, and a microphone, it would have been obvious to one of ordinary skill in the art to include at least one of the antenna, the battery, and the microphone as claimed such as the battery in order to provide the portable electrical power to the various electronic apparatus.
Regarding claim 9, Ikeda teaches an electronic apparatus comprising: the semiconductor device according to claim 1, and at least one of a mounting unit, a lens, a main body (a main body 901), and a cable, wherein the electronic apparatus is configured to obtain user information through the lens (Fig. 27A and paragraphs 440-441).
Regarding claim 10, Yang teaches wherein the first transistor comprises an oxide semiconductor (paragraphs 107-108). Ikeda in view of Yang has been discussed above except that the first transistor further comprises a back gate such that the back gate is connected to the second node. Nevertheless, it would have been obvious to one of ordinary skill in the art to provide the transistor of the display pixel circuit with a double/dual gate transistor having a first/front gate and a second/back gate compared to a single gate transistor in order to improve transistor characteristics. Furthermore, with the double/dual gate transistor utilized as a pixel driving transistor for the display pixel circuit, it would have been obvious to one of ordinary skill in the art that the second/back gate of the double/dual gate transistor is connected to the second node for connecting with the display element as one of design choices.
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot in view of new grounds of rejections as set forth above in this Office Action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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