Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claim 3 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 3 recites the broad recitation “at least two times…higher”, and the claim also recites “at least five times higher” which is the narrower statement of the range/limitation. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims. For the purpose of compact prosecution, examiner will use the broader interpretation and interpret the claim as “wherein a maximum doping concentration of at least one of the at least one first doped region or the at least one second doped region is at least two times higher than a maximum doping concentration of the drift layer”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, and 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimizu et al. (US20200219980A1, hereinafter Shimizu).
Regarding claim 1, Shimizu discloses a power semiconductor device, comprising
a drift layer of a first conductivity type (Fig. 11 drift layer 26 has n type conductivity),
at least two well regions of a second conductivity type being different from the first conductivity type (Fig. 11 p-well regions 28a/28b),
at least one intermediate region (Fig. 11 the intermediate region between p-well regions 28a/28b comprising p-type region 40a and n-type region 27),
a gate provided on the at least one intermediate region (Fig. 11 gate electrode 20 provided on the intermediate region between p-well regions 28a/28b comprising p-type region 40a and n-type region 27), and
a back metal layer provided on the drift layer at a second side opposite a first side of the power semiconductor device (Fig. 11 drain electrode 14 disposed on second side of drift layer 26 opposite gate electrode 20), wherein
the at least two well regions and the at least one intermediate region are provided at the first side of the power semiconductor device (Fig. 11 p well regions 28a/28b and the intermediate region between p-well regions 28a/28b comprising p-type region 40a and n-type region 27 are on the same side of drift layer 26 as gate electrode 20),
the at least one intermediate region is provided between two of the at least two well regions (Fig. 11 the intermediate region comprising p-type region 40a and n-type region 27 is between p-well regions 28a/28b),
the at least one intermediate region comprises at least one first doped region of the first conductivity type and at least one second doped region of the second conductivity type (Figs. 11/12 the intermediate region comprises both p-type region 40a and n-type region 27), and
the at least one first doped region and the at least one second doped region are spaced apart in lateral directions to the at least two well regions (Figs. 11/12 the intermediate region comprising both p-type region 40a and n-type region 27 is spaced apart in a lateral direction from p-well regions 28a/28b).
Regarding claim 2, Shimizu discloses the power semiconductor device according to claim 1,wherein
the at least one intermediate region extends along a main extension direction (Fig. 12 the intermediate region comprising both p-type region 40a and n-type region 27 extends along a first direction), and
the at least one first doped region and the at least one second doped region are provided consecutively along the main extension direction (Fig. 12 the intermediate region comprises a plurality of p-type regions 40a and a plurality of n-type regions 27 which are provided consecutively alternating along a first direction).
Regarding claim 3, Shimizu discloses the power semiconductor device according to claim 1,
wherein a maximum doping concentration of at least one of the at least one first doped region or the at least one second doped region is at least two times higher than a maximum doping concentration of the drift layer (Pars. 223/43 “The n-type impurity concentration of the n-type region 27 is, for example, 5×1015 cm−3 or more and 1×1018 cm−3” and “[t]he n-type impurity concentration of the drift region 26 is, for example, 1×1015 cm−3 or more and 2×1016 cm−3 or less.” Therefore, the maximum of n-type region 27 of 1×1018 cm−3 is at least two times higher than a doping concentration of 2×1016 of drift region 26).
Regarding claim 4, Shimizu discloses the power semiconductor device according to claim 1,
wherein the maximum doping concentration of at least one of the at least one first doped region or the at least one second doped region is at least 1.1014cm-3 and at most 1-1018 cm3 (Par. 223 “The n-type impurity concentration of the n-type region 27 is, for example, 5×1015 cm−3 or more and 1×1018 cm−3.” As Shimizu’s range is fully within the claimed range, the claimed range is also taught by Shimizu, see MPEP 2144.05(I)).
Regarding claim 7, Shimizu discloses the power semiconductor device according to claim 1,
wherein a first depth of the at least two well regions is at most as large as a second depth of the at least one first doped region and as a third depth of the at least one second doped region (Fig. 11 the depth of p-well regions 28a/28b is the same depth as p-type region 40a).
Regarding claim 9, Shimizu discloses the power semiconductor device according to claim 2,
wherein a plurality of first doped regions and a plurality of second doped regions are arranged consecutively alternating along the main extension direction (Fig. 12 the intermediate region comprises a plurality of p-type regions 40a and a plurality of n-type regions 27 which are provided consecutively alternating along a first direction).
Regarding claim 10, Shimizu discloses the power semiconductor device according to claim 1, further comprising
at least two source regions of the first conductivity type (Fig. 11 first n-type sources 30a/30b), wherein
at least one of the at least two source regions is provided on each of the at least two well regions (Fig. 11 there is a first n-type source 30a within p-well 28a and a first n-type source 30b within p-well 28b).
Regarding claim 11, Shimizu discloses the power semiconductor device according to claim 10,
wherein the gate overlaps with the at least two source regions at least in places in lateral direction (Fig. 11 gate electrode 20 overlaps first n-type sources 30a/30b in a first and second direction).
Regarding claim 12, Shimizu discloses a method for producing a power semiconductor device comprising
providing a drift layer of a first conductivity type (Fig. 11 drift layer 26 has n type conductivity),
producing at least two well regions of a second conductivity type being different from the first conductivity type at a first side of the drift layer by a doping process (Fig. 11 p-well regions 28a/28b),
producing at least one intermediate region at the first side of the drift layer by a further doping process (Fig. 11 the intermediate region between p-well regions 28a/28b comprising p-type region 40a and n-type region 27),
providing a gate on the at least one intermediate region (Fig. 11 gate electrode 20 provided on the intermediate region between p-well regions 28a/28b comprising p-type region 40a and n-type region 27), and
providing a back metal layer on the drift layer at a second side of the drift layer opposite the first side (Fig. 11 drain electrode 14 disposed on second side of drift layer 26 opposite gate electrode 20), wherein
the at least one intermediate region is produced between two of the at least two well regions (Fig. 11 the intermediate region comprising p-type region 40a and n-type region 27 is between p-well regions 28a/28b),
the at least one intermediate region comprises at least one first doped region of the first conductivity type and at least one second doped region of the second conductivity type (Fig. 11 the intermediate region comprising p-type region 40a and n-type region 27),
the at least one first doped region and the at least one second doped region are spaced apart in lateral directions to the at least two well regions (Figs. 11/12 the intermediate region comprising both p-type region 40a and n-type region 27 is spaced apart in a lateral direction from p-well regions 28a/28b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US20200219980A1) in view of Zhang et al. (US20140183553A1, hereinafter Zhang).
Regarding claim 5, Shimizu teaches the power semiconductor device according to claim 1.
Shimizu does not appear to teach
wherein a width of at least one of the at least one first doped region or the at least one second doped region is at least 0.5 µm and at most 5 µm.
In analogous arts, Zhang teaches gaps ranging from 0.8 µm, see fig. 4B, to 2.6 µm and in par. 31 Zhang additionally teaches in par. 31 that “it has been recognized by the inventors of the present invention that narrowing down the JFET gap (without sacrificing forward voltage drop) on a conventional MOSFET device could improve the device reliability under high electrical field stressing.” Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore change the size of either p-type regions 40b or n-type regions 27 such that their width is at least 0.5 µm and at most 5 µm, see MPEP 2144.04(VI)(A).
Regarding claim 6, Shimizu teaches the power semiconductor device according to claim 1,
wherein a length of at least one of the at least one first doped region or the at least one second doped region is at least 0.5 µm and at most 1.5 µm.
Shimizu does not appear to teach
wherein a width of at least one of the at least one first doped region or the at least one second doped region is at least 0.5 µm and at most 5 µm.
In analogous arts, Zhang teaches in par. 31 that “it has been recognized by the inventors of the present invention that narrowing down the JFET gap (without sacrificing forward voltage drop) on a conventional MOSFET device could improve the device reliability under high electrical field stressing.” As the gap, and therefore the widths of n-type regions 27 and p-type regions 40a affect the reliability of the device, then this would motivate a person of ordinary skill in the art to also modify the lengths of the individual regions. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore change the size of either p-type regions 40b or n-type regions 27 such that their length is at least 0.5 µm and at most 1.5 µm, see MPEP 2144.04(VI)(A).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US20200219980A1).
Regarding claim 8, Shimizu discloses the power semiconductor device according to claim 7,
wherein at least one of the second depth or the third depth are at least 50 nm and at most 1.5 µm (Par. 47 “The depth of the p-well region 28 is, for example, 0.4 μm or more and 0.8 μm or less.” As the depth of p-well regions 28a/28b as shown in fig. 11 is the same as the depth of p-type region 40a then this would motivate a person of ordinary skill in the art to attempt depths from 40 nm to 80 nm and so Shimizu teaches the disclosed range, see MPEP 2144.05(I)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hoshi et al. (US20170352733A1) teach a semiconductor device similar to applicant’s with similar doped regions and provides additional dopant concentrations.
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812