Prosecution Insights
Last updated: April 19, 2026
Application No. 18/283,897

POWER SEMICONDUCTOR MODULE COMPRISING SWITCH ELEMENTS AND DIODES

Non-Final OA §102
Filed
Sep 25, 2023
Examiner
KEBEDE, BROOK
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hitachi Energy Ltd.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
93%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
887 granted / 1000 resolved
+20.7% vs TC avg
Minimal +4% lift
Without
With
+4.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
28 currently pending
Career history
1028
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
33.9%
-6.1% vs TC avg
§102
31.0%
-9.0% vs TC avg
§112
11.6%
-28.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1000 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 1, 4 and 7 are objected to because of the following informalities: Claim 1 recites the limitation “A power module comprising: a first switch comprising a first switch element and an associated first diode, a second switch comprising a second switch element and an associated second diode, the first switch and the second switch being electrically connected to form a half-bridge, metallizations comprising one or more AC metallizations, one or more DC+ metallizations and one or more DC− metallizations, one or more AC terminals connected to the AC metallizations, one or more DC+ terminals connected to the DC+ metallizations and one or more DC− terminals connected to the DC− metallizations, wherein at least one AC metallization is located between at least one DC− metallization and at least one DC+ metallization, wherein the first switch element, the second switch element, the first diode and the second diode are located next to each other and are located on the DC+ metallizations and AC metallizations, wherein the second switch element and the second diode are located between the first switch element and the first diode” in lines 1-19. However, there is a lack proper antecedent basis for “the AC metallizations” and “the DC+ metallizations” and “the DC− metallizations” in the claim. Changing “the AC metallizations” and “the DC+ metallizations” and “the DC− metallizations” to --the at least one AC metallizations-- and --the at least one DC+ metallizations-- and --the at least one DC− metallizations-- in the claim provides proper antecedent basis. Similar changes should be made for claim 4. The reference number “12” in claim 7 should be deleted since Applicant deleted other reference numbers throughout the claims. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-7 and 9-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by NISHIKIMI et al. (US 2009/0040724). PNG media_image1.png 637 722 media_image1.png Greyscale \ Re Claim 1, NISHIKIMI et al. disclose a power module comprising: a first switch (328, paragraph [0104]) comprising a first switch element and an associated first diode (156, Paragraph [0104]), a second switch (330, Paragraph [0104]) comprising a second switch element and an associated second diode (166, Paragraph [0104]), the first switch and the second switch being electrically connected to form a half-bridge, metallizations (see Fig. 2) comprising one or more AC metallizations (159, Paragraph [0104]), one or more DC+ metallizations (157, Paragraph [0109]) and one or more DC− metallizations (158, Paragraph [0109]), one or more AC terminals connected to the AC metallizations (see Fig. 2), one or more DC+ terminals connected to the DC+ metallizations and one or more DC− terminals connected to the DC− metallizations (see Fig. 2), wherein at least one AC metallization is located between at least one DC− metallization and at least one DC+ metallization (see Fig. 2), wherein the first switch element (328) the second switch element (330), the first diode (156) and the second diode (166) are located next to each other and are located on the DC+ metallizations and AC metallizations, wherein the second switch element and the second diode are located between the first switch element and the first diode (see Figs 2 and 12, and related text Paragraphs [0104] and [0159] – [00162]). Re Claim 2, as applied to claim 1 above, NISHIKIMI et al. disclose all the claimed limitations including wherein the metallizations are arranged in the form of strips parallel to each other (see Figs. 2 and 12). Re Claim 3, as applied to claim 1 above, NISHIKIMI et al. disclose all the claimed limitations including a gate metallization (154 164, Paragraph [0108]) connected to a gate of the second switch element (330), wherein the gate metallization has the form of a strip located between the second switch element (330) and one of the first diode (158) and the second diode (168) located next to the second switch element (see Fig. 2 and Paragraph [0108]). Re Claim 4, as applied to claim 1 above, NISHIKIMI et al. disclose all the claimed limitations including wherein the first switch comprises one or more further first switch elements (328, i.e., elements in second rows of Fig, 2) the switch elements and associated further first diodes (156, i.e., diodes in the second rows of Fig. 2) and the second switch comprises one or more further second switch elements and associated further second diodes (166), wherein the first switch element and the further first switch elements are located next to each other in a row (see Fig. 2) , the second switch element and the further second switch elements are located next to each other in a row, the first diode and the further first diodes are located next to each other in a row and the second diode and the further second diodes are located next to each other in a row (see Fig. 2). Re Claim 5, as applied to claim 4 above, NISHIKIMI et al. disclose all the claimed limitations including wherein the first switch element (328) and the one or more further first switch elements (i.e.., other 328) are located on the same one of the metallizations and wherein the second switch element (330) and the one or more further second switch elements (i.e., other 330) are located on the same one of the metallizations (see Figs. 2 and 12). Re Claim 6, as applied to claim 1 above, NISHIKIMI et al. disclose all the claimed limitations including wherein the first switch element is located next to the second diode and the first diode is located next to the second switch element (see Figs. 2 and 12). Re Claim 7, as applied to claim 1 above, NISHIKIMI et al. disclose all the claimed limitations including wherein the first switch element is located next to the second switch element and the first diode is located next to the second diode . Re Claim 9, as applied to claim 1 above, NISHIKIMI et al. disclose all the claimed limitations including wherein the second diode and the second switch element are separated by one of the metallizations on which the first and second switch elements and associated first and second diodes are located. Re Claim 10, as applied to claim 1 above, NISHIKIMI et al. disclose all the claimed limitations including wherein the second switch element and the second diode are located on the same one of the metallizations (see Figs. 2 and 12). Re Claim 11, as applied to claim 1 above, NISHIKIMI et al. disclose all the claimed limitations including wherein the second diode is located closer to the first switch element than to the second switch element (see Figs. 2 and 12). Re Claim 12, as applied to claim 1 above, NISHIKIMI et al. disclose all the claimed limitations including wherein the first switch is a low side switch connected to a DC− terminal and the second switch is a high side switch connected to a DC+ terminal (see Figs. 2 and 12). Re Claim 13, as applied to claim 1 above, NISHIKIMI et al. disclose all the claimed limitations including wherein the first switch is a high side switch connected to a DC+ terminal and the second switch is a low side switch connected to a DC− terminal (see Figs. 2 and 12). Re Claim 14, as applied to claim 1 above, NISHIKIMI et al. disclose all the claimed limitations including at least one additional first switch element, associated additional first diode, additional second switch element and associated additional second diode located in the same column as the first switch element, the second switch element, the first diode and the second diode (see Figs. 2 and 12). Re Claim 15, as applied to claim 1 above, NISHIKIMI et al. disclose all the claimed limitations including wherein the first switch comprises one or more further first switch elements and the second switch comprises one or more further second switch elements, wherein each of the first switch and the second switch has an odd number of switch elements (see Figs. 2 and 12).  Allowable Subject Matter Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure Jones (US 2012/0147633) and Mohn et al. (US 2020/0066686) also disclose similar inventive subject matter. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to BROOK KEBEDE whose telephone number is 571-272-1862. The examiner can normally be reached Monday Friday 8:00 AM 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BROOK KEBEDE/ Primary Examiner, Art Unit 2894 /BK/ February 21, 2026
Read full office action

Prosecution Timeline

Sep 25, 2023
Application Filed
Feb 21, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
93%
With Interview (+4.3%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 1000 resolved cases by this examiner. Grant probability derived from career allow rate.

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