Prosecution Insights
Last updated: October 02, 2026
Application No. 18/284,643

MULTILAYER SUBSTRATE MANUFACTURING METHOD AND WIRING SUBSTRATE

Non-Final OA §103
Filed
Sep 28, 2023
Priority
Mar 30, 2021 — JP 2021-057939 +1 more
Examiner
DINH, TUAN T
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsui Mining & Smelting Co., Ltd.
OA Round
3 (Non-Final)
79%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
944 granted / 1198 resolved
+10.8% vs TC avg
Strong +22% interview lift
Without
With
+22.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
29 currently pending
Career history
1229
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
45.0%
+5.0% vs TC avg
§102
38.5%
-1.5% vs TC avg
§112
6.0%
-34.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1198 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/31/26 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 18-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (‘307) in view of Matsuura et al. (U.S. 2019/0378728). As to claim 18, Uzoh discloses a wiring substrate as shown in figures 1-2 comprising: a first substrate (110, para-0055+) being a rigid substrate; a second substrate (120); and a plurality of bumps (130) interposed between the first and second substrates (110, 120) and bonding the first substrate (110) and the second substrate (120), the bumps (130) comprising no solder in intermediate portions, wherein the bumps (130) are composed of a metal (para-0009+) OR alloy having a melting point of 600°C OR more and have a height of 0.6 µm OR more. Uzoh does not specifically disclose the first substrate comprising a rigid carrier, a release layer on the rigid carrier, and a metal layer on the release layer. Matsuura a multilayer circuit board (26, 38, see figure 2g) as shown in figures 1-2 comprising a first substrate (26) comprising a rigid carrier (12), a release layer (14) on the rigid carrier, and a metal layer (16) on the release layer. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Matsuura employed in the wiring substrate of Uzoh in order to minimize the stress, improve the reliable connection structure for the multilayer lamination. As to claim 19, Uzoh as modified by Matsuura teaches the first substrate (26) further comprises a redistribution layer (18, 20) on the rigid carrier, and wherein the redistribution layer and the second substrate (38) are bonded by the plurality of bumps (34). As to claim 20, Uzoh as modified by Matsuura discloses the rigid carrier (110) is composed of (1) glass, (2) a substrate comprising silicon, or (3) alumina, para-0057, 0059. As to claim 21, Uzoh as modified by Matsuura discloses the bumps (130) are regularly arranged at a pitch (center-to-center distance) of 1 µm or more and 40 µm or less, para-0217. Response to Arguments Applicant’s arguments with respect to claim(s) 18-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached 8am-5pm, M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TUAN T DINH/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Show 2 earlier events
Oct 09, 2025
Applicant Interview (Telephonic)
Dec 01, 2025
Non-Final Rejection mailed — §103
Mar 18, 2026
Response Filed
May 05, 2026
Final Rejection mailed — §103
Jul 24, 2026
Response after Non-Final Action
Jul 31, 2026
Request for Continued Examination
Aug 03, 2026
Response after Non-Final Action
Aug 06, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12750955
EMBEDDED PACKAGE STRUCTURE, POWER SUPPLY APPARATUS, AND ELECTRONIC DEVICE
3y 0m to grant Granted Sep 29, 2026
Patent 12740147
ELECTRONIC DEVICE
2y 8m to grant Granted Sep 15, 2026
Patent 12733099
ELECTRONICS PACKAGING FOR MOVING PLATFORMS
4y 5m to grant Granted Sep 08, 2026
Patent 12733100
REDUCING PRINTED CIRCUIT BOARD AREA FOR SINGLE-SIDED PRINTED CIRCUIT BOARD
3y 9m to grant Granted Sep 08, 2026
Patent 12727086
FLEXIBLE CIRCUIT BOARD AND METHOD OF MANUFACTURING THEREOF
2y 3m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+22.1%)
2y 11m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1198 resolved cases by this examiner. Grant probability derived from career allowance rate.

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